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M16C/5L Group, M16C/56 Group
6.5
Notes on Resets
6.5.1
Power Supply Rising Gradient
When supplying power to the MCU, make sure that the power supply voltage applied to the VCC pin
meets the SVCC conditions.
Symbol
SV
Power supply rising gradient (VCC) (Voltage range: 0 to 2)
CC
VCC
[V]
5.0
2.0
Figure 6.6
SVCC Timing
6.5.2
Power-On Reset
Use the voltage monitor 0 reset together with the power-on reset. To use the power-on reset, set the
LVDAS bit in the OFS1 address to 0 (voltage monitor 0 reset enabled after hardware reset). In this
case, the voltage monitor 0 reset is enabled (the VW0C0 bit and bit 6 in the VW0C register are 1, and
the VC25 bit in the VCR2 register is 1) after power-on reset. Do not disable these bits by a program.
6.5.3
OSDR Bit (Oscillation Stop Detect Reset Detect Flag)
When an oscillator stop detect reset is generated, the MCU is reset and then stopped. This state is
canceled by hardware reset or voltage monitor 0 reset.
Note that the OSDR bit in the RSTFR register is not affected by a hardware reset, but becomes 0 (not
detected) from a voltage monitor 0 reset.
6.5.4
Hardware Reset When VCC < Vdet0
If a hardware reset is executed when the LVDAS bit in the OFS1 address is 0 (voltage monitor 0 reset
enabled after hardware reset) and VCC < Vdet0, the MCU executes the program at the address
indicated by the reset vector when changing the signal applied to the RESET pin from low to high. A
voltage monitor 0 reset is not generated.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Parameter
Power-on
0
Min.
0.05
Minimum value of SVCC
(0 V to 2 V)
6. Resets
Standard
Unit
Typ.
Max.
V/ms
Time
Page 72 of 803
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