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M16C/5L Group, M16C/56 Group
2
PIN (I
C-bus interface interrupt request bit) (b4)
The PIN bit function in read access is described below. See Table 22.9 "Functions Enabled by Writing
to the S10 Register" for the bit function in write access.
Conditions to become 0:
•
Slave address transmission is completed in master mode (including a case of detecting arbitration
lost).
•
1-byte data transmission is completed (including a case of detecting arbitration lost).
•
1-byte data reception is completed (the falling edge of eighth clock is detected when the ACKCLK
bit in the S20 register is 0, or the falling edge of ACK clock when the ACKCLK bit is 1).
•
The WIT bit in the S3D0 register is 1 (I
reception is completed (before ACK clock).
•
In slave receive mode, the MSLAD bit in the S4D0 register is 1, the ALS bit in the S1D0 register is
0 (addressing format), and any of the slave address stored in bits SAD6 to SAD0 in the S0Di
register (i = 0 to 2) is matched with the received slave address (slave address match).
•
In slave receive mode, the MSLAD bit is 0, the ALS bit is 0 (addressing format), and the slave
address stored in bits SAD6 to SAD0 in the S0D0 register is matched with the received slave
address (slave address match).
•
In slave receive mode, the ALS bit in the S1D0 register is 0 (addressing format) and the received
slaved address is 0000000b (general call).
•
In slave receive mode, the ALS bit in the S1D0 register is 1 (free data format) and the slave
address reception is completed.
Conditions to become 1:
•
The S00 register is written.
•
The S20 register is written (when the WIT bit is 1 and the internal WAIT flag is 1).
•
The ES0 bit in the S1D0 register is set to 0 (I
•
The IHR bit in the S1D0 register is set to 1 (I
The IR bit in the IICIC register becomes 1 (interrupt requested) as soon as the PIN bit becomes 0 (I
bus interrupt requested). When the PIN bit is 0, the SCLMM pin output level is low.
However, when all of the following conditions are met, the SCLMM pin does not output a low level
signal:
•
In master mode, arbitration lost is detected by a slave address or data
•
The ALS bit in the S1D0 register is 0 (addressing format)
•
The slave address is not 0000000b (general call) and does not match any of the bits from SAD6 to
SAD0 in registers S0D0 to S0D2.
BB (Bus busy flag) (b5)
The BB bit function in read access is described below. See Table 22.9 "Functions Enabled by Writing to
the S10 Register" for the bit function in write access.
The BB bit indicates the state of the bus system, whether the bus is free or not. The BB bit changes
depending on the SCLMM and SDAMM input signals, regardless of master mode or slave mode.
Conditions to become 0:
•
Stop condition is detected.
•
The ES0 bit in the S1D0 register is set to 0 (I
•
The IHR bit in the S1D0 register is set to 1 (I
Condition to become 1:
•
Start condition is detected.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
2
C-bus interrupt enabled at 8th clock) and 1-byte data
2
C interface disabled).
2
C interface reset).
2
C interface disabled).
2
C interface reset).
2
22. Multi-master I
C-bus Interface
Page 519 of 803
2
C-
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