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M16C/5L Group, M16C/56 Group
7.4.2.1
Voltage Monitor 0 Reset
Table 7.5 lists Steps to Set Voltage Monitor 0 Reset Related Bits.
Table 7.5
Steps to Set Voltage Monitor 0 Reset Related Bits
Step
1
Set the VC25 bit in the VCR2 register to 1 (voltage detector 0 enabled).
2
Wait for td(E-A).
3
Set bits 6 and 7 in the VW0C register to 1.
4
Set bit 2 in the VW0C register to 0 (set this bit to 0 once again after step 3).
5
Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled).
Figure 7.4 shows Voltage Monitor 0 Reset Operation Example.
Internal reset signal
The above assumes the following:
•The VC25 bit in the VCR2 register is 1 (voltage detector 0 enabled).
•The VW0C0 bit in the VW0C register is 1 (voltage monitor 0 reset enabled).
The pins, CPU, and SFRs are initialized when the internal reset signal goes low.
The MCU executes the program at the address indicated by the reset vector when the internal reset signal changes from low to high.
Refer to 4. "Special Function Registers (SFRs)" for the SFR status after reset.
Figure 7.4
Voltage Monitor 0 Reset Operation Example
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
VCC
Vdet0
7. Voltage Detector
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