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REVISION HISTORY
Rev.
Date
Page
1.10 Sep. 01, 2011
213
221
222
227
Timer A
230
231
232
242
243
247
249,253,
257,262,
266
252
256
260
261
261
265
271
275
Timer B
279
284
290
294
M16C/5L, M16C/56 Group User's Manual: Hardware
Figure 14.1 DMAC Block Diagram:
Unified data buses for low/high-order bits with a single data bus.
Table 14.7 Timing at Which the DMAS Bit Value Changes: Changed "selected by setting bits
DSEL4 to DSEL0" to "selected by setting bits DSEL4 to DSEL0 and DMS" in the Timing at which
the bit becomes 1 column of the External source row.
14.3.3 Transfer Cycles:
Added "and the source and destination addresses are both odd addresses" to the second line from
the bottom.
Figure 14.5 DMA Transfer Initiated by External Sources:
Changed "DMAS bit in DMA0" and "DMAS bit in DMA1" to "DMAS bit in the DM0CON register" and
"DMAS bit in the DM1CON register", respectively.
Figure 15.1 Timer A and B Count Sources: Deleted the divide-by-2 circuit on fOCO-F.
Figure 15.2 Timer A Configuration: Corrected "TAiGH to TAiGL" typo to "TAiTGH to TAiTGL".
Table 15.3 I/O Ports: Changed "the port direction bits corresponding to the pins to 0" to "the port
direction bits sharing pins to 0" in note 1.
15.2.11 One-Shot Start Flag (ONSF):
Changed the last sentence of the TA0TGH-TA0TGL bit explanation.
15.2.12 Trigger Select Register (TRGSR):
Changed the last sentence of the bit explanation about bits TA1TGH-TA1TGL, TA2TGH-TA2TGL,
TA3TGH-TA3TGL, and TA4TGH-TA4TGL.
15.3.1.3 Count Source:
Changed "fOCO-F divided by 2, 4, or 8" to "fOCO-F divided by 1 (no division)".
Table 15.7, Table 15.9, Table 15.11, Table 15.13, and Table 15.15 Registers and Settings:
• Added TAOW.
• Changed "TAiTGH and TAiTGL" to "TA0TGH to TA0TGL" in the Bit column of ONSF.
Table 15.8 Event Counter Mode Specifications (When Not Using Two-Phase Pulse Signal
Processing):
• Deleted "by a program" from the first bullet in the Specification column of the Count source row.
• Added "When selecting reload type:" to the Specification column of the Number of counts row.
Table 15.10 Event Counter Mode Specifications (When Processing Two-Phase Pulse Signal with
Timers A2, A3, and A4):
• Added "When selecting reload type:" to the Specification column of the Number of counts row.
Figure 15.9 Relationship between the Two-Phase Pulse (A-Phase and B-Phase) and the Z-Phase:
• Added "(Z-phase)".
• Changed the description of input pulse for ZP input.
15.3.5 One-Shot Timer Mode:
Changed "the timer counter decrements" to "the timer starts" in the explanation.
Table 15.12 One-Shot Timer Mode Specifications:
Changed the descriptions in the Write to timer row.
Table 15.14 PWM Mode Specifications:Changed the Specification in the Count start condition row.
Table 15.17 Registers and Settings in Programmable Output Mode:
Changed "TAiTGH and TAiTGL" to "TA0TGH to TA0TGL" in the Bit column of ONSF.
15.5 Notes on Timer A: Rewritten by common items, and each mode.
Figure 16.1 Timer A and B Count Sources: Deleted the divide-by-2 circuit on fOCO-F.
16.2.3 Timer Bi Register (TBi) (i = 0 to 2): Deleted the description about "TBSR" from the Pulse
Period Measurement Mode, Pulse Width Measurement Mode bit explanation.
16.3.1.3 Count Source:
Changed "fOCO-F divided by 2, 4, or 8" to "fOCO-F divided by 1 (no division)".
16.3.3 Event Counter Mode:
• Changed "TBj overflow or underflow" to "timer Bj" in the Function column of the TCK1 bit in the
register diagram and the explanation of bits MR1 and MR0 explanation.
• Added the TCK1 bit explanation.
Description
Summary
C- 6
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