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M16C/5L Group, M16C/56 Group
12.7.6
Returning from an Interrupt Routine
The FLG register and PC saved in the stack immediately before entering the interrupt sequence are
restored from the stack by executing the REIT instruction at the end of the interrupt routine. Then, the
CPU returns to the program which was being executed before the interrupt request was accepted.
Restore the other registers saved by a program within the interrupt routine using the POPM or a similar
instruction before executing the REIT instruction.
The register bank is switched back to the bank used prior to the interrupt sequence by the REIT
instruction.
12.7.7
Interrupt Priority
If two or more interrupt requests occur at the same sampling points (the point in time at which interrupt
requests are detected), the interrupt with the highest priority is acknowledged.
For maskable interrupts (peripheral function interrupts), any priority level can be selected using bits
ILVL2 to ILVL0. However, if two or more maskable interrupts have the same priority level, their interrupt
priority is selected by hardware, with the highest priority interrupt accepted.
The watchdog timer interrupt and other special interrupts have their priority levels set in hardware.
Figure 12.7 shows the Hardware Interrupt Priority.
Software interrupts are not affected by the interrupt priority. When an instruction is executed, control
always branches to the interrupt routine.
Figure 12.7
Hardware Interrupt Priority
12.7.8
Interrupt Priority Level Select Circuit
The interrupt priority level select circuit selects the highest priority interrupt among sampled interrupt
requests at the same sampling point.
Figure 12.8 shows the Interrupt Priority Select Circuit.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Reset
NMI
DBC
Watchdog timer,
oscillator stop/restart detect,
voltage monitor 2
Peripheral functions
Single-step
Address match
12. Interrupts
High
Low
Page 189 of 803
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