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M16C/5L Group, M16C/56 Group
21.3.5
Special Mode 3 (IE Mode) (UART2)
In this mode, 1 bit of IEBus is approximated by 1 byte of UART mode waveform.
Table 21.21 lists the Registers Used and Settings in IE Mode. Figure 21.29 shows the Bus Collision
Detect Function-Related Bits.
If the TXD2 pin output level and RXD2 pin input level do not match, a UART2 bus collision detect
interrupt request is generated.
Table 21.21
Registers Used and Settings in IE Mode
Register
U2TB
(2)
U2RB
OER, FER, PER, SUM
U2BRG
U2MR
U2C0
U2C1
U2RRM
U2SMR
U2SMR2
U2SMR3
U2SMR4
Notes:
1.
This table does not describe a procedure.
Set the bits not listed above to 0 when writing to registers in IE mode
2.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Bits
0 to 8
Set transmission data.
0 to 8
Reception data can be read.
Error flag
0 to 7
Set bit rate.
SMD2 to SMD0
Set to 110b.
CKDIR
Select internal clock or external clock.
STPS
Set to 0.
PRY
Disabled because PRYE is 0
PRYE
Set to 0.
IOPOL
Select the TXD and RXD input/output polarity.
CLK1, CLK0
Select the count source for the U2BRG register.
CRS
Disabled because CRD is 1
TXEPT
Transmit register empty flag
CRD
Set to 1.
NCH
Select TXD2 pin output format.
CKPOL
Set to 0.
UFORM
Set to 0.
TE
Set to 1 to enable transmission.
TI
Transmit buffer empty flag
RE
Set to 1 to enable reception.
RI
Reception complete flag
(2)
Select the source of UART transmit interrupt.
U2IRS
(2)
Set to 0.
, U2LCH, U2ERE
0 to 3, 7
Set to 0.
ABSCS
Select the sampling timing to detect a bus collision.
ACSE
Set to 1 to use the auto clear function of the transmit enable bit.
SSS
Select the transmit start condition.
0 to 7
Set to 0.
0 to 7
Set to 0.
0 to 7
Set to 0.
21. Serial Interface UARTi (i = 0 to 4)
(1)
Function
.
Page 486 of 803
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