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M16C/5L Group, M16C/56 Group
26.11.3 CPU Rewrite Mode
26.11.3.1 Operating Speed
Select a CPU clock frequency of 16 MHz or less by setting the CM06 bit in the CM0 register and bits
CM17 and CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also,
set the PM17 bit in the PM1 register to 1 (wait state).
26.11.3.2 CPU Rewrite Mode Select
Change FMR01 bit in the FMR0 register, FMR11 bit in the FMR1 register, and FMR60 bit in the FMR6
register while in the following state:
• The PM24 bit in the PM2 register is 0 ( NMI interrupt disabled).
• High is input to the NMI pin.
Change the FMR60 bit while the FMR00 bit in the FMR0 register is 1 (ready).
26.11.3.3 Prohibited Instructions
Do not use the following instructions in EW0 mode:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.
26.11.3.4 Interrupts (EW0 Mode and EW1 Mode)
• Do not use an address match interrupt during command execution because the address match
interrupt vector is located in ROM.
• Do not use a non-maskable interrupt during block 0 erase because fixed vector is located in block 0.
26.11.3.5 Rewrite (EW0 Mode)
If the power supply voltage drops while rewriting the block where the rewrite control program is
stored, the rewrite control program is not correctly rewritten. This may prevent the flash memory from
being rewritten. If this error occurs, use standard serial I/O mode or parallel I/O mode for rewriting.
26.11.3.6 Rewrite (EW1 Mode)
Do not rewrite any blocks in which the rewrite control program is stored.
26.11.3.7 DMA transfer
In EW0 mode, do not use flash memory as a source of the DMA transfer.
In EW1 mode, do not generate a DMA transfer while the FMR00 bit in the FMR0 register is 0 (auto
programming or auto erasing).
26.11.3.8 Wait Mode
To enter wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) before
executing the WAIT instruction.
26.11.3.9 Stop Mode
To enter stop mode, set the FMR01 bit to 0 (CPU rewrite mode disabled), and then disable DMA
transfer before setting the CM10 bit in the CM 1 register to 1 (stop mode).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
26. Flash Memory
Page 699 of 803
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