Advertisement
M16C/5L Group, M16C/56 Group
22.5
Notes on Multi-master I
22.5.1
Limitation on CPU Clock
When the CM07 bit in the CM0 register is 1 (CPU clock is a sub clock), do not access the registers
listed in Table 22.4 "Registers". Set the CM07 bit to 0 (main clock, PLL clock, or on-chip oscillator clock)
to access these registers.
22.5.2
Register Access
Refer to the notes below when accessing the I
edge of the first clock of the slave address or 1-byte data transmission/reception to the falling edge of
an ACK clock is considered to be the transmission/reception period. When the ACKCLK bit is 0 (no
ACK clock), the transmission/reception period is from the rising edge of the first clock of the slave
address or 1-byte data transmission/reception to the falling edge of the eighth clock.
22.5.2.1
S00 Register
Do not write to the S00 register during transmission/reception.
22.5.2.2
S1D0 Register
Do not change bits other than the IHR bit in the S1D0 register during transmission/reception.
22.5.2.3
S20 Register
Do not change bits other than the ACKBIT bit in the S20 register during transmission/reception.
22.5.2.4
S3D0 Register
• Do not use the bit managing instruction (read-modify-write instruction) to access the S3D0 register.
Use the MOV instruction to write to this register.
• Rewrite bits ICK1 and ICK0 when the ES0 bit in the S1D0 register is 0 (I
22.5.2.5
S4D0 Register
Rewrite bits ICK4 to ICK2 when the ES0 bit in the S1D0 register is 0 (I
22.5.2.6
S10 Register
•
Do not use the bit managing instruction (read-modify-write instruction) to access the S10 register.
Use the MOV instruction to write to this register.
•
Do not write to the S10 register when bits MST and TRX change their values.
Refer to operation examples in 22.3 "Operations" for bits MST and TRX change.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
2
C-bus Interface
2
C interface control registers. The period from the rising
2
22. Multi-master I
C-bus Interface
2
C interface disabled).
2
C interface disabled).
Page 545 of 803
Advertisement
