Renesas M16C/50 Series User Manual page 179

M16C/5L Group, M16C/56 Group
10.2.3 Flash Memory Control Register 1 (FMR1)
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
FMR17 (Data Flash Wait Bit) (b7)
This bit is used to select the number of wait states for data flash.
When setting this bit to 0, one wait is inserted to the read cycle of the data flash. The write cycle is not
affected.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
FMR1
Bit Symbol Bit Name
—
Reserved bit
(b0)
Write to FMR6 register
FMR11
enable bit
—
Reserved bits
(b3-b2)
—
Reserved bit
(b4)
—
No register bit. If necessary, set to 0. The read value is undefined.
(b5)
FMR16 Lock bit status flag
FMR17 Data flash wait bit
Address
0221h
Function
The read value is undefined.
0 : Disabled
1 : Enabled
The read value is undefined.
Set to 0
0 : Lock
1 : Unlock
0 : 1 wait
1 : Follow the setting of the PM17 bit in the
PM1 register
10. Processor Mode
Reset Value
00X0 XX0Xb
RW
RO
RW
RO
RW
—
RO
RW
Page 142 of 803