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M16C/5L Group, M16C/56 Group
SCL clock
Figure 21.21 SCL Clock
21.3.3.6
SDA Output Control
When transmitting byte data, the SDA2 pin outputs transmit data for the first to eighth bits, and it is
released to receive an acknowledgment for the ninth bit.
2
In I
C mode, set 9-bit data to the U2TB register. In 9-bit data, set the transmit data to bits b7 to b0 and
set b8 to 1. By setting the UFORM bit in the U2C0 register to 1 (MSB first) and 9-bit data to the U2TB
register, transmit data is output from the SDA2 pin in the following order: b7, b6, b5, b4, b3, b2, b1, b0
and b8. As b8 is 1, the SDA2 pin becomes high-impedance at the ninth bit and an acknowledgment can
be received.
Figure 21.22 U2TB Register Setting (SDA Output)
SCL
(Transmitter) SDA
Figure 21.23 Byte Data Transmission
Set bits DL2 to DL0 in the U2SMR3 register to add no delays or a delay of one to eight U2BRG count
source clock cycles to SDA2 output.
Setting the SDHI bit in the U2SMR2 register to 1 (SDA output disabled) forcibly places the SDA2 pin in
a high-impedance state. Do not write to the SDHI bit at the rising edge of the UART2 transmit/receive
clock as the ABT bit in the U2RB register may inadvertently become 1 (detected).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
To be compatible with SCL low hold from another device, the
high time count starts after high is determined.
1 / (2f
(theoretical value))
SCL
t
t
LOW
F
UART2 Transmit Buffer Register (UiTB)
b15
1
b7
U2TB register ← 01XXh
1 / (2f
(theoretical value))
SCL
Noise filter width + 1 to 1.5 cycles
(high determined delay)
t
t
R
HIGH
b8
b7
1
Transmit data
Set to 1 to release the SDA2 pin
2
3
4
5
b6
b5
b4
b3
Transmit data
21. Serial Interface UARTi (i = 0 to 4)
b0
6
7
8
9
b2
b1
b0
b8
Release (Hi-Z)
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