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M16C/5L Group, M16C/56 Group
21.3.3.7
SDA Digital Delay
When transferring data with the I 2 C-bus, change the data while the SCL clock is low. When SDA is
changed while the SCL clock is a high, the change is recognized as one of the corresponding
conditions (see 21.5.3.3 "Setup and Hold Times When Generating a Start/Stop Condition").
This function delays output from the SDA2 pin. By delaying the change of the SDA, the data can be
changed while the SCL clock is low. This function is enabled by setting bits DL2 to DL0 in the U2SMR3
register to 001b to 111b, and disabled by setting them to 000b.
SCL
U2BRG
count source
When DL2 to DL0 are 000b (no delay)
SDA
When DL2 to DL0 are 001b (1 to 2 cycles of U2BRG count source)
SDA
When DL2 to DL0 are 111b (7 to 8 cycles of U2BRG count source)
SDA
DL2 to DL0: Bits in the U2SMR3 register
Figure 21.24 SDA Output Selection by Setting Bits DL2 to DL0
21.3.3.8
SDA Input
When the IICM2 bit in the U2SMR2 register is set to 0, the first 8 bits of received data (D7 to D0) are
stored in bits 7 to 0 in the U2RB register and the ninth bit (ACK/NACK) is stored in bit 8.
When the IICM2 bit is 1, the first to seventh bits (D7 to D1) of the received data are stored in bits 6 to 0
in the U2RB register and the eighth bit (D0) is stored in bit 8 in the U2RB register. Even when the IICM2
bit is 1, if the CKPH bit in the U2SMR3 register is 1, the same data as when the IICM2 bit is 0 can be
read. To read the data, read the U2RB register after the rising edge of ninth bit of the corresponding
clock pulse.
When receiving byte data, the SDA2 pin is released for the first to eighth bits to receive data, and an
acknowledgment is generated for the ninth bit. NACK is generated when the last byte data is received
in master mode, or when the slave address does not match in slave mode. In all other cases, ACK is
generated.
2
In I
C mode, set 9-bit data to the U2TB register. In 9-bit data, set FFh to b7 to b0 to release the SDA2
pin and set b8 to 0 to generate ACK or 1 to generate NACK.
By setting 00FFh or 01FFh as 9-bit data to the U2TB register, the SDA2 pin becomes high-impedance
for the first to eighth bits, and data can be received. ACK or NACK is generated at the ninth bit.
Read the received data from the U2RB register. When the clock delay function is used, data transfer to
the U2RB register occurs twice and each U2RB register value is different. Refer to Figure 21.15
"Transfer to U2RB Register and Interrupt Timing" for details.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
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21. Serial Interface UARTi (i = 0 to 4)
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