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M16C/5L Group, M16C/56 Group
Table 26.25
Setting of Standard Serial I/O Mode 2
Signal
CNVSS
RESET
P6_5/CLK1
Notes:
1. Control pins and external circuitry will vary depending on the programmer. For more information, refer to the programmer manual.
2. In this example, modes are switched between single-chip mode and standard serial I/O mode by controlling the CNVSS input with
a switch.
Figure 26.27 Circuit Application in Standard Serial I/O Mode 2
26.10 Parallel I/O Mode
In parallel I/O mode, program ROM 1, program ROM 2, and data flash can be rewritten using a parallel
programmer supporting the M16C/5L Group, M16C/56 Group. Contact the parallel programmer
manufacturer for more information. Refer to the user's manual included with your parallel programmer
for instructions.
26.10.1 ROM Code Protect Function
The ROM code protect function disables the flash memory from being read or rewritten during
parallel I/O mode. Refer to 26.4.1 "Optional Function Select Address 1 (OFS1)". The OFS1 address
is located in block 0 of program ROM 1.
When the ROMCR bit in the OFS1 address is 1 (ROMCP1 bit enabled) and the ROMCP1 bit is set to
0, the ROM code protect function is enabled.
To cancel ROM code protect, erase block 0 including the OFS1 address using standard serial I/O
mode or CPU rewrite mode.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Input Level
VCC
VSS → VCC
VSS
TXD output
Monitor output
RXD intput
VCC
Reset input
User reset signal
MCU
P6_7/TXD1
P6_4/RTS1
CNVSS
P6_6/RXD1
P6_5/CLK1
RESET
26. Flash Memory
Page 697 of 803
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