Renesas M16C/50 Series User Manual page 244

M16C/5L Group, M16C/56 Group
13.4 Operations
13.4.1 Refresh Operation Period
To refresh the watchdog timer, the period writing to the WDTR register can be limited to the fixed period
before the underflow. The refresh period can be selected by setting bits WDTRCS1 and WDTRCS0 in
the OFS2 address. The period specified by these bits assumes that an underflow period of the
watchdog timer is 100%. Figure 13.2 shows the refresh operation period for the watchdog timer.
Count starts
(Note 1)
0%
WDTRCS1 and WDTRCS0: Bits in the OFS2 address
Note:
1. In this period, a write to the WDTR register is considered as an incorrect write, and a watchdog timer interrupt or a watchdog
timer reset is generated.
Figure 13.2 Watchdog Timer Refresh Period
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
One watchdog timer cycle
Refresh period
Refresh period
(Note 1)
(Note 1)
25% 50%
Underflow
Refresh period
Refresh period
75% 100%
13. Watchdog Timer
Refresh period
100% (WDTRCS1 to WDTRCS0 = 11b)
75% (WDTRCS1 to WDTRCS0 = 10b)
50% (WDTRCS1 to WDTRCS0 = 01b)
25% (WDTRCS1 to WDTRCS0 = 00b)
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