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M16C/5L Group, M16C/56 Group
26.4.1
Optional Function Select Address 1 (OFS1)
Optional Function Select Address 1
b7
b6 b5 b4
b3
0
1
ROMCR (ROM code protect disable bit) (b2)
ROMCP1 (ROM code protect bit) (b3)
These bits are used to disable the flash memory from being read or rewritten in parallel I/O mode.
Table 26.5
ROM Code Protect
Bit Setting
ROMCR bit
0
0
1
1
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b2
b1
b0
1
OFS1
Bit Symbol
WDTON
Watchdog timer start select bit
—
Reserved bit
(b1)
ROMCR
ROM code protect cancel bit
ROMCP1 ROM code protect bit
—
Reserved bit
(b4)
—
Reserved bit
(b5)
LVDAS
Voltage detector 0 start bit
After-reset count source
CSPROINI
protection mode select bit
ROMCP1 bit
0
1
0
1
Address
FFFFFh
Bit Name
0 : Watchdog timer starts automatically
after reset.
1 : Watchdog timer is in a stopped state
after reset.
Set to 1.
0 : ROM code protection cancelled.
1 : ROMCP1 bit enabled.
0 : ROM code protection enabled.
1 : ROM code protection cancelled.
Set to 1.
Set to 0.
0 : Voltage monitor 0 reset enabled
after hardware reset.
1 : Voltage monitor 0 reset disabled
after hardware reset.
0 : Count source protection mode
enabled after reset.
1 : Count source protection mode
disabled after reset.
ROM Code Protect
Disabled
Enabled
Disabled
26. Flash Memory
Function
Page 659 of 803
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