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M16C/5L Group, M16C/56 Group
6.4.2
Hardware Reset
This reset is triggered by the RESET pin. When the power supply voltage meets the recommended
operating conditions, the MCU resets the pins, CPU, and SFRs when a low-level signal is applied to the
RESET pin.
When changing the signal applied to the RESET pin from low to high, the MCU executes the program
at the address indicated by the reset vector. fOCO-S divided by 8 is automatically selected as the CPU
clock after reset.
The HWR bit in the RSTFR register becomes 1 (hardware reset detected) after hardware reset.
However, if the LVDAS bit in the OFS1 address is 0 (voltage detector 0 reset is enabled after resetting
the hardware), the HWR bit is undefined. Refer to 4. "Special Function Registers (SFRs)" for the
remaining SFR states after reset.
The internal RAM is not reset. When a low-level signal is applied to the RESET pin while writing data to
the internal RAM, the internal RAM becomes undefined.
The procedures for generating a hardware reset are as follows:
When the power supply is stable
(1) Apply a low-level signal to the RESET pin.
(2) Wait for tw(RSTL).
(3) Apply a high-level signal to the RESET pin.
When the power is turned on
(1) Apply a low-level signal to the RESET pin.
(2) Raise the power supply voltage to the recommended operating level.
(3) Wait for td(P-R) until the internal voltage stabilizes.
(4) Wait for
--------------------- -
fOCO S –
(5) Apply a high-level signal to the RESET pin.
Figure 6.4 shows an Reset Circuit Example.
VCC
RESET
Figure 6.4
Reset Circuit Example
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
1
× 20 cycles.
Recommended
operating
VCC
voltage
0 V
RESET
0.2 VCC or below
0 V
0.2 VCC or below
1
× 20 cycles or above
td(P-R) +
fOCO-S
6. Resets
Page 68 of 803
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