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REVISION HISTORY
Rev.
Date
Page
1.10 Sep. 01, 2011
469
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493-494 21.4 Interrupts, 21.4.1 Interrupt Related Registers and 21.4.2 Reception Interrupt: Added.
495
495, 496 21.5.2.2 Transmission and 21.5.2.3 Reception:
497-498 21.5.3.3 Setup and Hold Times When Generating a Start/Stop Condition to 21.5.3.6 Requirements
498
Multi-Master I
Chap. 22. Changed terminology "High-speed clock mode" to "Fast-mode".
505
516
M16C/5L, M16C/56 Group User's Manual: Hardware
Table 21.14 Registers Used and Settings in I
• Added UCLKSEL0 and PCLKR to the Register column.
• Added "When receiving, set FFh." to b0 to b7 of U2TB in the Function column.
• Added b8 to U2TB.
• Added b13 to b15 to U2RB.
• Added b4 to b6 to U2MR.
• Deleted note 1.
Table 21.15 Registers Used and Settings in I
• Changed the function of the SWC bit and CKPH bit.
• Deleted the IFSR2A register.
2
Table 21.16 I
C Mode Functions:
• Added an explanation above the table.
• Rewrote all of the content.
Figure 21.15 Transfer to U2RB Register and Interrupt Timing: Deleted "(1) IICM2 = 0 (ACK and
NACK interrupts), CKPH = 0 (no clock delay)" and "(3) IICM2 = 1 (UART transmit/receive interrupt),
CKPH = 0".
21.3.3.1 Detecting Start and Stop Conditions: Added the last paragraph.
Figure 21.16 Detecting Start and Stop Conditions: Revised.
Figure 21.17 STSPSEL Bit Functions: Revised.
Figure 21.18 Register Setting Procedures for Condition Generation: Added.
21.3.3.3 Arbitration: Rewritten.
21.3.3.4 SCL Control and Clock Synchronization: Added, including Figure 21.19 and Figure 21.20.
21.3.3.5 SCL Clock Frequency: Added, including Figure 21.21.
Table 21.18 Special Mode 2 Specifications: Changed "While transmission" to "For transmit
interrupt", and "While receiving" to "For receive interrupt".
Table 21.20 Registers Used and Settings in Special Mode 2
• Added UCLKSEL0 and PCLKR to the Register column.
• Added b8 to U2TB.
• Added b8, b11, and b13 to b15 to U2RB.
• Added b4 to b6 to U2MR.
• Deleted note 1.
Table 21.21 Registers Used and Settings in IE Mode: Deleted the IFSR2A register.
Table 21.22 SIM Mode Specifications: Changed note 2.
Figure 21.30 Transmit/Receive Timing in SIM Mode: Added the timing when the IR bit in the S2TIC
register becomes 1.
21.5.1 Common Notes on Multiple Modes: Added.
Changed the style of the explanations about the external clock level into bulleted lists.
to Start Transmission/Reception in Slave Mode: Added.
21.5.4 Special Mode 4 (SIM Mode):
Changed the conditions to generate a transmit interrupt request.
2
C-bus Interface
22.2.3 I2C0 Control Register 0 (S1D0): Changed "P2_0/SDAMM pin and P2_1/SCLMM pin" to
"SCLMM pin and SDAMM pin" in the TISS bit explanation.
22.2.8 I2C0 Status Register 0 (S10): Changed explanations for the following bits.
• LRB bit: Rewritten.
• AL bit: Changed "master-slave mode" to "master receive mode" in the third and fourth bullets of
the Conditions to become 1.
• PIN bit: Deleted the description about the MSLAD bit from the second last bullet in the
Conditions become 0.
• PIN bit: Rewrote the conditions for the SCLMM pin not to output a low signal.
C- 11
Description
Summary
2
C Mode (1/2):
2
C Mode (2/2):
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