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M16C/5L Group, M16C/56 Group
23.1.8
CAN0 Mailbox Interrupt Enable Register (C0MIER)
CAN0 Mailbox Interrupt Enable Register
Normal mailbox mode
b31
FIFO mailbox mode
b31
b24b23
00 00
Notes:
1. Write to the C0MIER register only when the associated C0MCTLj register (j = 0 to 31) is 00h and
the corresponding mailbox is not processing a transmission or reception abort request.
2. In FIFO mailbox mode, change the bits in the C0MIER register for the associated FIFO only when:
- The TFE bit in the C0TFCR register is 0 and the TFEST bit is 1, and
- The RFE bit in the C0RFCR register is 0 and the RFEST bit is 1.
3. No interrupt request is generated when the receive FIFO becomes buffer warning from full.
Figure 23.9
C0MIER Register
Interrupts can enabled individually for each mailbox.
In normal mailbox mode (bits 0 to 31) and in FIFO mailbox mode (bits 0 to 23), each bit corresponds to
the mailbox with the same number. These bits enable or disable transmission/reception complete
interrupts for the corresponding mailboxes.
In FIFO mailbox mode, bits 24, 25, 28, and 29 specify whether transmit/receive FIFO interrupts are
enabled/disabled and timing when interrupt requests are generated.
"Buffer warning" indicates a state in which the third unread message is stored in the receive FIFO.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b0
C0MIER
Bit Symbol
—
Interrupt Enable Bit
(b31-b0)
b0
Bit Symbol
—
Interrupt Enable Bit
(b23-b0)
—
Transmit FIFO Interrupt
(b24)
Enable Bit
Transmit FIFO Interrupt
—
Generation Timing
(b25)
Control Bit
—
Reserved
(b27-b26)
—
Receive FIFO Interrupt
(b28)
Enable Bit
Receive FIFO Interrupt
—
Generation Timing
(b29)
Control Bit
—
Reserved
(b31-b30)
(1, 2)
Address
D72Fh-D72Ch
Bit Name
Bit Name
0: Interrupt disabled
1: Interrupt enabled
Bit Name
Bit Name
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
Transmit FIFO interrupt request is
generated
0: Every time transmission is
completed
1: When transmit FIFO becomes
empty due to completion of
transmission
Set to 0.
0: Interrupt disabled
1: Interrupt enabled
Receive FIFO interrupt request is
generated
0: Every time reception is completed
1: When receive FIFO becomes
buffer warning by completion of
reception
Set to 0.
23. CAN Module
Reset Value
Undefined
Function
RW
RW
Function
RW
RW
RW
RW
RW
RW
RW
(3)
RW
Page 565 of 803
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