Page 1 REJ09B0185-0241 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES Before using this material, please visit our website to verify that this is the most updated document available. Rev.2.41 Revision Date:Jan 10, 2006 www.renesas.com http://www.xinpian.net...
Page 2 Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con- tact Renesas Technology Corp.
Page 3 How to Use This Manual Introduction This hardware manual provides detailed information on the M16C/62P Group (M16C/62P, M16C/62PT) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below. XXX Register Symbol Address...
Page 4 • Sample programs • Introduction to the basic functions in the M16C family • Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTES: 1. Before using this material, please visit the our website to confirm that this is the most current document available.
Page 5: Table Of Contents
Table of Contents SFR Page Reference B - 1 Overview Applications ....................1 Performance Outline ...................2 Block Diagram .....................5 Product List ....................7 Pin Configuration..................14 Pin Description ..................25 Central Processing Unit (CPU) Data Registers (R0, R1, R2 and R3)............30 Address Registers (A0 and A1)..............31 Frame Base Register (FB) ................31 Interrupt Table Register (INTB) ..............31 Program Counter (PC) ................31...
Page 6 Brown-out Detection Reset (Hardware Reset 2) ........42 Software Reset..................43 Watchdog Timer Reset................43 Oscillation Stop Detection Reset...............43 Internal Space ...................44 Voltage Detection Circuit Low Voltage Detection Interrupt ..............49 Limitations on Exiting Stop Mode .............51 Limitations on Exiting Wait Mode ..............51 Cold Start-up / Warm Start-up Determine Function ........52 Processor Mode Types of Processor Mode .................54 Setting Processor Modes ................55...
Page 7 10. Clock Generation Circuit 10.1 Types of the Clock Generation Circuit............82 10.1.1 Main Clock..................89 10.1.2 Sub Clock ...................90 10.1.3 On-chip Oscillator Clock ..............91 10.1.4 PLL Clock ...................91 10.2 CPU Clock and Peripheral Function Clock..........93 10.2.1 CPU Clock and BCLK.................93 10.2.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)................93 10.3...
Page 8 12.5 Interrupt Control ..................111 12.5.1 I Flag....................113 12.5.2 IR Bit....................113 12.5.3 ILVL2 to ILVL0 Bits and IPL .............113 12.5.4 Interrupt Sequence ................114 12.5.5 Interrupt Response Time ..............115 12.5.6 Variation of IPL when Interrupt Request is Accepted .......115 12.5.7 Saving Registers ................116 12.5.8 Returning from an Interrupt Routine ..........118 12.5.9...
Page 9 15.2 Timer B....................156 15.2.1 Timer Mode ..................159 15.2.2 Event Counter Mode.................160 15.2.3 Pulse Period and Pulse Width Measurement Mode ......162 16. Three-Phase Motor Control Timer Function 17. Serial Interface 17.1 UARTi (i=0 to 2) ..................176 17.1.1 Clock Synchronous Serial I/O Mode..........189 17.1.2 Clock Asynchronous Serial I/O (UART) Mode........197 17.1.3...
Page 10 19. D/A Converter 20. CRC Calculation 21. Programmable I/O Ports 21.1 Port Pi Direction Register (PDi Register, i = 0 to 13) ......256 21.2 Port Pi Register (Pi Register, i = 0 to 13) ..........256 21.3 Pull-up Control Register 0 to Pull-up Control Register 3 (PUR0 to PUR3 Registers)..............256 21.4 Port Control Register (PCR Register) .............256...
Page 11 24. Precautions 24.1 SFR ......................359 24.1.1 Register Settings ................359 24.2 Reset .......................360 24.3 Bus ......................361 24.4 PLL Frequency Synthesizer ..............362 24.5 Power Control..................363 24.6 Protect .....................365 24.7 Interrupt ....................366 24.7.1 Reading address 00000h ..............366 24.7.2 Setting the SP...................366 24.7.3 The NMI Interrupt ................366 24.7.4 Changing the Interrupt Generate Factor...........367 24.7.5...
Page 12 24.15.6 Program Command ................379 24.15.7 Lock Bit Program Command ............379 24.15.8 Operation speed ................380 24.15.9 Instructions inhibited against use .............380 24.15.10 Interrupts ..................380 24.15.11 How to access ..................380 24.15.12 Writing in the user ROM area ............380 24.15.13 DMA transfer ..................381 24.15.14 Regarding Programming/Erasing Endurance and Execution Time ..381 24.16 Noise .......................382 25.
Page 13 SFR Page Reference Address Register Symbol Page Address Register Symbol Page 0000h 0040h 0001h 0041h 0002h 0042h 0003h 0043h 0004h Processor Mode Register 0 0044h INT3 Interrupt Control Register INT3IC 0005h Processor Mode Register 1 0045h Timer B5 Interrupt Control Register TB5IC 0006h System Clock Control Register 0...
Page 14 Address Register Symbol Page Address Register Symbol Page 0080h 0340h Timer B3, 4, 5 Count Start Flag TBSR 0081h 0341h 0082h 0342h Timer A1-1 Register TA11 0083h 0343h 0084h 0344h Timer A2-1 Register TA21 0085h 0345h 0086h 0346h Timer A4-1 Register TA41 0087h 0347h...
Page 15 Address Register Symbol Page Address Register Symbol Page 0380h Count Start Flag TABSR 141, 158 03C0h A/D Register 0 0381h Clock Prescaler Reset Fag CPSRF 143, 158 03C1h 0382h One-Shot Start Flag ONSF 03C2h A/D Register 1 0383h Trigger Select Register TRGSR 03C3h 0384h...
Page 16: Overview
M16C/62P Group (M16C/62P, M16C/62PT) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin plastic molded QFP.
Page 17: Performance Outline
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Performance Outline Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version). Table 1.1 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version) Item Performance M16C/62P Number of Basic Instructions 91 instructions Minimum Instruction Execution 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) Time...
Page 18 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.2 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(100-pin version) Item Performance M16C/62P M16C/62PT Number of Basic Instructions 91 instructions Minimum Instruction 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) Execution Time 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Operating Mode Single-chip, memory expansion Single-chip...
Page 19 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.3 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version) Item Performance M16C/62P M16C/62PT Number of Basic Instructions 91 instructions Minimum Instruction 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) Execution Time 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Operating Mode Single-chip mode Address Space...
Page 20: Block Diagram
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Block Diagram Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram, Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram. Port P0 Port P1 Port P2 Port P3 Port P4 Port P5...
Page 21 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Port P0 Port P4 Port P6 Port P2 Port P3 Port P5 System clock Internal peripheral functions A/D converter generation circuit (10 bits 8 channels Timer (16-bit) Expandable up to 26 channels) XIN-XOUT Output (timer A): 5 XCIN-XCOUT Input (timer B): 6 UART or...
Page 22: Product List
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Product List Table 1.4 to 1.7 list the product list, Figure 1.3 shows the Type No., Memory Size, and Package, Table 1.8 lists the Product Code of Flash Memory version and ROMless version for M16C/62P, and Table 1.9 lists the Product Code of Flash Memory version for M16C/62PT.
Page 23 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.5 Product List (2) (M16C/62P) As of Dec. 2005 Type No. ROM Capacity Package Type Remarks Capacity M30622MHP-XXXFP 384 Kbytes 16 Kbytes PRQP0100JB-A Mask ROM version M30622MHP-XXXGP PLQP0100KB-A M30623MHP-XXXGP PLQP0128KB-A M30624MHP-XXXFP 24 Kbytes PRQP0100JB-A M30624MHP-XXXGP PLQP0100KB-A...
Page 24 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.6 Product List (3) (T version (M16C/62PT)) As of Dec. 2005 Type No. ROM Capacity Package Type Remarks Capacity M3062CM6T-XXXFP (D) 48 Kbytes 4 Kbytes PRQP0100JB-A Mask ROM T Version version (High reliability M3062CM6T-XXXGP (D) PLQP0100KB-A 85°C version)
Page 25 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.7 Product List (4) (V version (M16C/62PT)) As of Dec. 2005 Type No. ROM Capacity Package Type Remarks Capacity M3062CM6V-XXXFP (P) 48 Kbytes 4 Kbytes PRQP0100JB-A Mask ROM V Version version (High reliability M3062CM6V-XXXGP (P) PLQP0100KB-A 125°C version)
Page 26 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Type No. M 3 0 6 2 6 M H P - X X X F P Package type: FP : Package PRQP0100JB-A (100P6S-A) GP : Package PRQP0080JA-A (80P6S-A), PLQP0100KB-A (100P6Q-A), PLQP0128KB-A (128P6Q-A), ROM No. Omitted for flash memory version and ROMless version Classification...
Page 27 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P Internal ROM Internal ROM (User ROM Area Without Block A, (Block A, Block 1) Operating Block 1) Product Package Ambient Code Program Program Temperature...
Page 28 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.9 Product Code of Flash Memory version for M16C/62PT Internal ROM Internal ROM (User ROM Area (Block A, Block 1) Operating Without Block A, Block 1) Product Package Ambient Code Program Program Temperature Temperature Temperature and Erase...
Page 29: Pin Configuration
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Pin Configuration Figures 1.6 to 1.9 show the Pin Configuration (Top View). PIN CONFIGURATION (top view) P1_0/D8 P12_5 P0_7/AN0_7/D7 P12_6 <VCC2> P0_6/AN0_6/D6 P12_7 P0_5/AN0_5/D5 P5_0/WRL/WR P0_4/AN0_4/D4 P5_1/WRH/BHE P0_3/AN0_3/D3 P5_2/RD P0_2/AN0_2/D2 P5_3/BCLK P0_1/AN0_1/D1 P13_0 P0_0/AN0_0/D0 P13_1 P11_7 P13_2...
Page 30 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.10 Pin Characteristics for 128-Pin Package (1) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin VREF AVCC P9_7 SIN4 ADTRG P9_6 SOUT4 ANEX1 P9_5 CLK4 ANEX0 P9_4 TB4IN...
Page 31 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.11 Pin Characteristics for 128-Pin Package (2) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin P5_6 P5_5 HOLD P5_4 HLDA P13_3 P13_2 P13_1 P13_0 P5_3 BCLK P5_2 P5_1...
Page 32 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.12 Pin Characteristics for 128-Pin Package (3) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin P1_2 P1_1 P1_0 P0_7 AN0_7 P0_6 AN0_6 P0_5 AN0_5 P0_4 AN0_4 P0_3 AN0_3...
Page 33 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview PIN CONFIGURATION (top view) P4_4/CS0 P0_7/AN0_7/D7 <VCC2> P4_5/CS1 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P4_6/CS2 P0_4/AN0_4/D4 P4_7/CS3 P0_3/AN0_3/D3 P5_0/WRL/WR P0_2/AN0_2/D2 P5_1/WRH/BHE P0_1/AN0_1/D1 P5_2/RD P0_0/AN0_0/D0 P5_3/BCLK M16C/62P Group P10_7/AN7/KI3 P5_4/HLDA P10_6/AN6/KI2 P5_5/HOLD (M16C/62P, M16C/62PT) P10_5/AN5/KI1 P5_6/ALE P10_4/AN4/KI0 P5_7/RDY/CLKOUT P10_3/AN3 P6_0/CTS0/RTS0 P10_2/AN2 P6_1/CLK0...
Page 34 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview PIN CONFIGURATION (top view) P1_2/D10 P4_2/A18 P1_1/D9 P4_3/A19 <VCC2> P1_0/D8 P4_4/CS0 P0_7/AN0_7/D7 P4_5/CS1 P0_6/AN0_6/D6 P4_6/CS2 P0_5/AN0_5/D5 P4_7/CS3 P0_4/AN0_4/D4 P5_0/WRL/WR P0_3/AN0_3/D3 P5_1/WRH/BHE P0_2/AN0_2/D2 P5_2/RD P0_1/AN0_1/D1 P5_3/BCLK P0_0/AN0_0/D0 P5_4/HLDA M16C/62P Group P10_7/AN7/KI3 P5_5/HOLD P10_6/AN6/KI2 P5_6/ALE (M16C/62P, M16C/62PT) P10_5/AN5/KI1 P5_7/RDY/CLKOUT P10_4/AN4/KI0...
Page 35 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.13 Pin Characteristics for 100-Pin Package (1) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin P9_6 SOUT4 ANEX1 P9_5 CLK4 ANEX0 P9_4 TB4IN P9_3 TB3IN P9_2 TB2IN SOUT3...
Page 36 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.14 Pin Characteristics for 100-Pin Package (2) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 60 VCC2 P3_0...
Page 37 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview PIN CONFIGURATION (top view) P0_6/AN0_6 P4_3 P0_5/AN0_5 P5_0 P0_4/AN0_4 P5_1 P0_3/AN0_3 P5_2 P0_2/AN0_2 P5_3 P0_1/AN0_1 P5_4 P0_0/AN0_0 P5_5 P10_7/AN7/KI3 P5_6 P10_6/AN6/KI2 M16C/62P Group P5_7/CLKOUT P10_5/AN5/KI1 P6_0/CTS0/RTS0 (M16C/62P, M16C/62PT) P10_4/AN4/KI0 P6_1/CLK0 P10_3/AN3 P6_2/RXD0/SCL0 P10_2/AN2 P6_3/TXD0/SDA0 P10_1/AN1 P6_4/CTS1/RTS1/CTS0/CLKS1 AVSS...
Page 38 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.15 Pin Characteristics for 80-Pin Package (1) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin P9_5 CLK4 ANEX0 P9_4 TB4IN P9_3 TB3IN P9_2 TB2IN SOUT3 P9_0 TB0IN CLK3...
Page 39 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.16 Pin Characteristics for 80-Pin Package (2) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin P3_0 P2_7 AN2_7 P2_6 AN2_6 P2_5 AN2_5 P2_4 AN2_4 P2_3 AN2_3 P2_2 AN2_2...
Page 40: Pin Description
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Pin Description Table 1.17 Pin Description (100-pin and 128-pin Version) (1) Signal Name Pin Name Power Description Type Supply − Power supply VCC1,VCC2 Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin.
Page 41 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.18 Pin Description (100-pin and 128-pin Version) (2) Signal Name Pin Name Power Description Type Supply Main clock VCC1 I/O pins for the main clock generation circuit. Connect a ceramic input resonator or crystal oscillator between XIN and XOUT .
Page 42 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.19 Pin Description (100-pin and 128-pin Version) (3) Signal Name Pin Name Power Description Type Supply Reference VREF VCC1 Applies the reference voltage for the A/D converter and D/A voltage input converter. A/D converter AN0 to AN7, VCC1 Analog input pins for the A/D converter.
Page 43 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.20 Pin Description (80-pin Version) (1) Signal Name Pin Name Power Description Type Supply − (1, 2) Power supply VCC1, VSS Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin. input Analog power AVCC...
Page 44 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.21 Pin Description (80-pin Version) (2) Signal Name Pin Name Power Description Type Supply Reference VREF VCC1 Applies the reference voltage for the A/D converter and D/A voltage input converter. A/D converter AN0 to AN7, VCC1 Analog input pins for the A/D converter.
Page 45: Central Processing Unit (Cpu)
M16C/62P Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b8 b7 Data Registers Address Registers...
Page 46: Address Registers (A0 And A1)
M16C/62P Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU) Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Page 47: Stack Pointer Select Flag (U Flag)
M16C/62P Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU) 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”. The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos.
Page 48: Memory
M16C/62P Group (M16C/62P, M16C/62PT) 3. Memory Memory Figure 3.1 is a Memory Map of the M16C/62P group. The address space extends the 1M bytes from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh.
Page 49: Special Function Register (Sfr)
M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.6 list the SFR information. Table 4.1 SFR Information (1) Address Register Symbol After Reset 0000h 0001h 0002h...
Page 50 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.2 SFR Information (2) Address Register Symbol After Reset 0040h 0041h 0042h 0043h 0044h INT3 Interrupt Control Register INT3IC XX00X000b 0045h Timer B5 Interrupt Control Register TB5IC XXXXX000b 0046h Timer B4 Interrupt Control Register, UART1 BUS Collision Detection Interrupt Control Register TB4IC, U1BCNIC XXXXX000b 0047h...
Page 51 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.3 SFR Information (3) Address Register Symbol After Reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h Flash Identification Register FIDR XXXXXX00b 01B5h Flash Memory Control Register 1 FMR1 0X00XX0Xb 01B6h...
Page 52 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.4 SFR Information (4) Address Register Symbol After Reset 0340h Timer B3, 4, 5 Count Start Flag TBSR 000XXXXXb 0341h 0342h Timer A1-1 Register TA11 0343h 0344h Timer A2-1 Register TA21 0345h 0346h...
Page 53 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.5 SFR Information (5) Address Register Symbol After Reset 0380h Count Start Flag TABSR 0381h Clock Prescaler Reset Fag CPSRF 0XXXXXXXb 0382h One-Shot Start Flag ONSF 0383h Trigger Select Register TRGSR 0384h Up-Down Flag...
Page 54 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.6 SFR Information (6) Address Register Symbol After Reset 03C0h A/D Register 0 03C1h 03C2h A/D Register 1 03C3h 03C4h A/D Register 2 03C5h 03C6h A/D Register 3 03C7h 03C8h A/D Register 4 03C9h 03CAh...
Page 55: Reset
M16C/62P Group (M16C/62P, M16C/62PT) 5. Reset Reset Hardware reset 1, brown-out detection reset (hardware reset 2), software reset, watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer. Hardware Reset 1 The microcomputer resets pins, the CPU and SFR by setting the RESET pin. If the supply voltage meets the recommended operating conditions, the microcomputer resets all pins when an “L”...
Page 56 M16C/62P Group (M16C/62P, M16C/62PT) 5. Reset VCC1, VCC2 More than d(P-R) 20 cycles are needed Microprocessor mode BYTE = H RESET BCLK 28cycles BCLK Content of reset vector FFFFDh FFFFCh FFFFEh Address Microprocessor Content of reset vector mode BYTE = L FFFFCh FFFFEh Address...
Page 57: Brown-Out Detection Reset (Hardware Reset 2)
M16C/62P Group (M16C/62P, M16C/62PT) 5. Reset Table 5.1 Pin Status When RESET Pin Level is “L” Pin Name Status CNVSS = VCC1 CNVSS = VSS BYTE = VSS BYTE = VCC1 Input port Data input Data input Input port Data input Input port P2, P3, P4_0 to P4_3 Input port...
Page 58: Software Reset
M16C/62P Group (M16C/62P, M16C/62PT) 5. Reset Software Reset The microcomputer resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to “1” (microcomputer reset). Then the microcomputer executes the program in an address determined by the reset vector. Set the PM03 bit to “1”...
Page 59: Internal Space
M16C/62P Group (M16C/62P, M16C/62PT) 5. Reset Internal Space Figure 5.3 shows CPU Register Status After Reset. Refer to 4. Special Function Register (SFR) for SFR states after reset. 0000h Data Register(R0) 0000h Data Register(R1) Data Register(R2) 0000h 0000h Data Register(R3) 0000h Address Register(A0) 0000h...
Page 60: Voltage Detection Circuit
M16C/62P Group (M16C/62P, M16C/62PT) 6. Voltage Detection Circuit Voltage Detection Circuit Note The M16C/62PT do not use the voltage detection circuit. However, the cold start-up/warm start-up determine function is available. The voltage detection circuit consists of the reset level detection circuit and the low voltage detection circuit. The reset level detection circuit monitors the voltage applied to the VCC1 pin.
Page 61 M16C/62P Group (M16C/62P, M16C/62PT) 6. Voltage Detection Circuit Voltage Detection Register 1 b7 b6 b5 b4 b3 b2 b1 0 0 0 0 Symbol Address After Reset 0019h 00001000b VCR1 Bit Name Bit Symbol Function — Reserved Bit Set to “0” (b2-b0) Low Voltage Monitor Flag 0 : VCC1 <...
Page 62 M16C/62P Group (M16C/62P, M16C/62PT) 6. Voltage Detection Circuit Low Voltage Detection Interrupt Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 001Fh D4INT Bit Symbol Bit Name Function Low Voltage Detection Interrupt 0 : Disable Enable Bit 1 : Enable STOP Mode Deactivation Control 0 : Disable (do not use the Low voltage...
Page 63 M16C/62P Group (M16C/62P, M16C/62PT) 6. Voltage Detection Circuit 5.0V 5.0V Vdet4 Vdet3r VCC1 Vdet3 Vdet3s RESET Internal Reset Signal VC13 bit in Indefinite VCR1 register Set to “1” by program (reset level detect circuit enable) VC26 bit in Indefinite VCR2 register Set to “1”...
Page 64: Low Voltage Detection Interrupt
M16C/62P Group (M16C/62P, M16C/62PT) 6. Voltage Detection Circuit Low Voltage Detection Interrupt If the D40 bit in the D4INT register is set to “1” (low voltage detection interrupt enabled), the low voltage detection interrupt request is generated when the voltage applied to the VCC1 pin is above or below Vdet4. The low voltage detection interrupt shares the same interrupt vector with the watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.
Page 65 M16C/62P Group (M16C/62P, M16C/62PT) 6. Voltage Detection Circuit Low Voltage detection interrupt generation circuit DF1, DF0 The D42 bit is set to “0” (not detected) by program. The VC27 bit is set to “0” (voltage down detect circuit disabled), Low Voltage detection Circuit the D42 bit is set to “0”.
Page 66: Limitations On Exiting Stop Mode
M16C/62P Group (M16C/62P, M16C/62PT) 6. Voltage Detection Circuit Limitations on Exiting Stop Mode The low voltage detection interrupt is immediately generated and the microcomputer exits stop mode if the CM10 bit in the CM1 register is set to “1” under the conditions below. •...
Page 67: Cold Start-Up / Warm Start-Up Determine Function
M16C/62P Group (M16C/62P, M16C/62PT) 6. Voltage Detection Circuit Cold Start-up / Warm Start-up Determine Function As for the cold start-up/warm start-up determine function, the WDC5 flag in the WDC register determines either cold start-up (reset process) when power-on or warm start-up (reset process) when reset signal is applied during the microcomputer running.
Page 68 M16C/62P Group (M16C/62P, M16C/62PT) 6. Voltage Detection Circuit Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 000Fh 00XXXXXXb Bit Symbol Bit Name Function — High-order Bit of Watchdog Timer (b4-b0) Cold Start / Warm Start Discrimination 0 : Cold Start WDC5 (1, 2)
Page 69: Processor Mode
M16C/62P Group (M16C/62P, M16C/62PT) 7. Processor Mode Processor Mode Note The M16C/62P (80-pin version) and M16C/62PT do not use memory expansion mode, and microprocessor mode. Types of Processor Mode Three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode.
Page 70: Setting Processor Modes
M16C/62P Group (M16C/62P, M16C/62PT) 7. Processor Mode Setting Processor Modes Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register. Table 7.2 shows the Processor Mode After Hardware Reset. Table 7.3 shows the PM01 to PM00 Bits Set Values and Processor Modes.
Page 71 M16C/62P Group (M16C/62P, M16C/62PT) 7. Processor Mode Processor Mode Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0004h 00000000b (CNVSS pin = L) 00000011b (CNVSS pin = H) Bit Symbol Bit Name Function Processor Mode Bit b1 b0 PM00 0 0 : Single-chip mode...
Page 72 M16C/62P Group (M16C/62P, M16C/62PT) 7. Processor Mode Processor Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0005h 0X001000b Bit Symbol Bit Name Function CS2 Area Sw itch Bit 0 : 08000h to 26FFFh (Block A disable) PM10 (Data Block Enable Bit) 1 : 10000h to 26FFFh (Block A enable)
Page 73 M16C/62P Group (M16C/62P, M16C/62PT) 7. Processor Mode Single-Chip Mode PM13=0 Internal RAM Internal ROM 00000h Capacity Address XXXXXh Capacity Address YYYYYh 4 Kbytes 013FFh 48 Kbytes F4000h 00400h 5 Kbytes 017FFh 64 Kbytes F0000h 10 Kbytes 96 Kbytes E8000h 02BFFh Internal RAM 12 Kbytes 033FFh...
Page 74: Bus
M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus Note The M16C/62P (80-pin version) and M16C/62PT do not use bus control pins. During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input/ output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/ WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.
Page 75: Bus Control
M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait. 8.2.1 Address Bus The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or 20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register.
Page 76 M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus Chip Select Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0008h 00000001b Bit Name Bit Symbol Function ____ Output Enable Bit 0 : Chip select output disabled (functions as I/O port) ____ 1 : Chip select output enabled Output Enable Bit...
Page 77 M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus Example 1 Example 2 To access the external area indicated by CSj in the next cycle after To access the internal ROM or internal RAM in the next cycle after accessing the external area indicated by CSi accessing the external area indicated by CSi The address bus and the chip select signal both change state between The chip select signal changes state but the address bus does not...
Page 78: Read And Write Signals
M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus 8.2.4 Read and Write Signals When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD, BHE and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When the data bus is 8 bits wide, use a combination of RD, WR and BHE.
Page 79: Rdy Signal
M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus 8.2.6 RDY Signal This signal is provided for accessing external devices which need to be accessed at low speed. If input on the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in the bus cycle.
Page 80: Hold Signal
M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus 8.2.7 HOLD Signal This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the input on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in process finishes.
Page 81 M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus Table 8.6 Pin Functions for Each Processor Mode Memory Processor Mode Memory Expansion Mode or Microprocessor Mode Expansion Mode 11b (multiplexed 01b(CS2 is for multiplexed bus and bus for the entire others are for separate bus) PM05 to PM04 bits 00b(separate bus) bits space)
Page 82: External Bus Status When Internal Area Accessed
M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus 8.2.9 External Bus Status When Internal Area Accessed Table 8.7 shows the External Bus Status When Internal Area Accessed. Table 8.7 External Bus Status When Internal Area Accessed Item SFR Accessed Internal ROM, RAM Accessed A0 to A19 Address output Maintain status before accessed...
Page 83: Software Wait
M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus 8.2.10 Software Wait Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register.
Page 84 M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus Table 8.8 Bit and Bus Cycle Related to Software Wait CSR Register CSE Register CS3W Bit CSE31W to CSE30W Bit Software Area Bus Mode Register Register CS2W Bit CSE21W to CSE20W Bit Bus Cycle Wait PM20 Bit PM17 Bit...
Page 85 M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus (1) Separate Bus, No Wait Setting Bus cycle Bus cycle BCLK Write signal Read signal Data bus Output Input Address bus Address Address (2) Separate Bus, 1-Wait Setting Bus cycle Bus cycle BCLK Write signal Read signal Output Input...
Page 86 M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus (1) Separate Bus, 3-Wait Setting Bus cycle Bus cycle (1) BCLK Write signal Read signal Data bus Output Input Address Address Address bus (2) Multiplexed Bus, 1- or 2-Wait Setting Bus cycle Bus cycle BCLK Write signal Read signal...
Page 87: Memory Space Expansion Function
M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Memory Space Expansion Function Note The M16C/62P (80-pin version) and M16C/62PT do not use the memory space expansion function. The following describes a memory space extension function. During memory expansion or microprocessor mode, the memory space expansion function allows the access space to be expanded using the appropriate register bits.
Page 88 M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Data Bank Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 000Bh Function Bit Symbol Bit Name — Nothing is assigned. When w rite, set to “0”. —...
Page 89 M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Microprocessor mode Memory expansion mode 00000h 00400h Internal RAM Internal RAM XXXXXh Reserved area Reserved area 04000h (16 Kbytes) 08000h Reserved, external area Reserved, external area (PM10=0: 124 Kbytes) 10000h (PM10=1: 92 Kbytes) 27000h Reserved area Reserved area...
Page 90 M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Memory expansion mode Microprocessor mode 00000h 00400h Internal RAM Internal RAM XXXXXh Reserved area 08000h Reserved, external area Reserved, external area (PM10=0: 124 Kbytes) 10000h (PM10=1: 92 Kbytes) 27000h Reserved area Reserved area 28000h (32 Kbytes)
Page 91 M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Memory expansion mode Microprocessor mode 00000h 00400h Internal RAM Internal RAM XXXXXh Reserved area Reserved area 04000h (16 Kbytes) 08000h Reserved, external area Reserved, external area (PM10=0 : 124 Kbytes) 10000h (PM10=1 : 92 Kbytes) 27000h Reserved area...
Page 92 M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Memory expansion mode Microprocessor mode 00000h 00400h Internal RAM Internal RAM XXXXXh Reserved area Reserved area 08000h Reserved, external area Reserved, external area (PM10=0: 124 Kbytes) 10000h (PM10=1: 92 Kbytes) 27000h Reserved area Reserved area 28000h...
Page 93 M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Figure 9.6 shows the External Memory Connect Example in 4-Mbyte Mode. In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of microcomputer. The 4 Mbyte ROM address input AD21, AD20 and AD19 pins are connected to the CS3, CS2 and CS1 pins of microcomputer, respectively.
Page 94 M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Memory expansion mode where PM13 =0 Microcomputer address ROM address Output from the Microcomputer Pins Bank Access OFS bit in DBR OFS bit in DBR Number Area CS Output Address Output register = 0 register = 1 A16 A15 to A0...
Page 95 M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Memory expansion mode where PM13 =1 ROM address Microcomputer address Output from the Microcomputer Pins Bank Access OFS bit in DBR OFS bit in DBR CS Output Address Output Number Area register = 0 register = 1 A16 A15 to A0...
Page 96 M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Microprocessor mode Microcomputer address ROM address Output from the Microcomputer Pins Bank Access OFS bit in DBR OFS bit in DBR CS Output Address Output Number Area register = 0 register = 1 A16 A15 to A0 000000h 40000h...
Page 97: 10. Clock Generation Circuit
M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10. Clock Generation Circuit 10.1 Types of the Clock Generation Circuit 4 circuits are incorporated to generate the system clock signal : • Main clock oscillation circuit • Sub clock oscillation circuit •...
Page 98 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit CM01 to CM00=00b Sub-clock I/O ports generating circuit PM01 to PM00=00b, CM01 to CM00=01b CLKOUT PM01 to PM00=00b, CM01 to CM00=10b XCIN XCOUT PM01 to PM00=00b, CM01 to CM00=11b fC32 1/32 CM04 PCLK0=1 Sub-clock PCLK0=0...
Page 99 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit System Clock Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0006h 01001000b Bit Symbol Bit Name Function b1 b0 Clock Output Function CM00 0 0 : I/O port P5_7 Select Bit 0 1 : Output fC (Valid only in single-chip...
Page 100 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit System Clock Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol Address After Reset 0007h 00100000b Bit Symbol Bit Name Function (4, 6) All Clock Stop Control Bit 0 : Clock on CM10 1 : All clocks off (stop mode)
Page 101 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit Oscillation Stop Detection Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset (11) 000Ch 0X000000b Bit Symbol Bit Name Function Oscillation Stop, 0: Oscillation stop, re-oscillation detection Re-Oscillation Detection function disabled CM20 (7, 9, 10,11)
Page 102 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit Peripheral Clock Select Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 Symbol Address After Reset 025Eh 00000011b PCLKR Bit Symbol Bit Name Function Timers A, B Clock Select Bit 0 : f2 PCLK0 (Clock source for Timers A , B, and the dead timer)
Page 103 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit (1, 2) PLL Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 Symbol Address After Reset 001Ch 0001X010b PLC0 Bit Symbol Bit Name Function PLL Multiplying Factor b2 b1 b0 Select Bit 0 0 0 : Do not set...
Page 104: Main Clock
M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit The following describes the clocks generated by the clock generation circuit. 10.1.1 Main Clock This clock is used as the clock source for the CPU and peripheral function clocks. This clock is used as the clock source for the CPU and peripheral function clocks.
Page 105: Sub Clock
M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.1.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. In addition, an fc clock with the same frequency as that of the sub clock can be output from the CLKOUT pin.
Page 106: On-Chip Oscillator Clock
M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.1.3 On-chip Oscillator Clock This clock, approximately 1MHz, is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to 13.1 Count source protective mode).
Page 107 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit Using the PLL clock as the clock source for the CPU Set the CM07 bit to “0” (main clock), the CM17 to CM16 bits to “00b” (main clock undivided), and the CM06 bit to “0” (CM16 and CM17 bits enabled).
Page 108: Cpu Clock And Peripheral Function Clock
M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.2 CPU Clock and Peripheral Function Clock Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions. 10.2.1 CPU Clock and BCLK These are operating clocks for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the PLL clock.
Page 109: Power Control
M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.4 Power Control Normal operating mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operating mode in this document. 10.4.1 Normal Operating Mode Normal operating mode is further classified into seven modes.
Page 110 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.4.1.7 On-chip Oscillator Low Power Dissipation Mode The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be selected as in the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the peripheral function clocks. If the sub clock is on, fC32 can be used as the count source for Timers A and B.
Page 111: Wait Mode
M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. However, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watchdog timer count source), the watchdog timer remains active.
Page 112 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.4.2.4 Exiting Wait Mode The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt, low voltage detection interrupt or peripheral function interrupt. If the microcomputer is to be moved out of exit wait mode by a hardware reset, NMI interrupt or low voltage detection interrupt, set the peripheral function interrupt priority ILVL2 to ILVL0 bits to “000b”...
Page 113: Stop Mode
M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode.
Page 114 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.4.3.3 Exiting Stop Mode Stop mode is exited by a hardware reset, NMI interrupt, low voltage detection interrupt or peripheral function interrupt. When the hardware reset, NMI interrupt or low voltage detection interrupt is used to exit stop mode, set all ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to “000b”...
Page 115 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit Main clock oscillation On-chip oscillator clock oscillation On-chip oscillator low power On-chip oscillator mode dissipation mode High-speed mode Middle-speed mode Middle-speed mode Middle-speed mode Middle-speed mode PLL operation mode PLC07=1 (divide by 2) (divide by 4) (divide by 8) (divide by 16)
Page 116 M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit Table 10.8 Allowed Transition and Setting State After Transition High-Speed Mode, Low-Speed Low Power On-chip On-chip Oscillator Stop Wait Middle-Speed Mode Dissipation Operating Oscillator Low Power Mode Mode Mode Mode Mode Mode Dissipation Mode Current High-Speed Mode,...
Page 117: System Clock Protection Function
M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.5 System Clock Protection Function The system clock protection function prohibits the CPU clock from changing clock sources when the main clock is selected the CPU clock source. This prevents the CPU clock from stopping should the program crash. This function is available when the main clock is selected as the CPU clock source.
Page 118: Oscillation Stop And Re-Oscillation Detect Function
M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.6 Oscillation Stop and Re-oscillation Detect Function The oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and re- oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation detection interrupt are generated.
Page 119: How To Use Oscillation Stop And Re-Oscillation Detect Function
M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.6.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer interrupt and low voltage detection interrupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
Page 120: 11. Protection
M16C/62P Group (M16C/62P, M16C/62PT) 11. Protection 11. Protection Note The M16C/62PT do not use the PRC3 bit in the PRCR register. In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily.
Page 121: Interrupt
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12. Interrupt Note The M16C/62P (80-pin version) do not use INT3 to INT5 interrupt of peripheral function. The M16C/62PT (100-pin version) do not use low voltage detection interrupt. The M16C/62PT (80-pin version) do not use low voltage detection interrupt and INT3 to INT5 interrupt of peripheral function.
Page 122: Software Interrupts
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 12.2.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 12.2.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set to “1” (the operation resulted in an overflow).
Page 123: Hardware Interrupts
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.3 Hardware Interrupts Hardware interrupts are classified into two types − special interrupts and peripheral function interrupts. 12.3.1 Special Interrupts Special interrupts are non-maskable interrupts. 12.3.1.1 NMI Interrupt An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details about the NMI interrupt, refer to the 12.7 NMI Interrupt.
Page 124: Interrupts And Interrupt Vector
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector.
Page 125: Relocatable Vector Tables
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.4.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 12.2 lists the Relocatable Vector Tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses.
Page 126: Interrupt Control
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and ILVL2 to ILVL0 bits in the each interrupt control register to enable/ disable the maskable interrupts.
Page 127 M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt INTi (0 to 5) Interrupt Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0044h XX00X000b INT3IC 0048h XX00X000b S4IC/INT5IC 0049h XX00X000b S3IC/INT4IC 005Dh to 005Fh XX00X000b INT0IC to INT2IC Bit Name Bit Symbol Function...
Page 128: I Flag
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.5.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts. 12.5.2 IR Bit The IR bit is set to “1”...
Page 129: Interrupt Sequence
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.5.4 Interrupt Sequence An interrupt sequence − what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed − is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
Page 130: Interrupt Response Time
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.5.5 Interrupt Response Time Figure 12.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed.
Page 131: Saving Registers
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.5.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first.
Page 132 M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP , at the time of acceptance of an interrupt request, is even or odd. If the stack pointer is even, the FLG register and the PC are saved,16 bits at a time.
Page 133: Returning From An Interrupt Routine
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.5.8 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
Page 134: 12.5.10 Interrupt Priority Level Select Circuit
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.5.10 Interrupt Priority Level Select Circuit The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt requests are sampled at the same sampling point. Figure 12.10 shows the Interrupts Priority Select Circuit. Priority level of each interrupt Level 0 (initial value) Highest...
Page 135: Int Interrupt
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.6 INT Interrupt INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in the IFSR register. INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively. To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to “1”...
Page 136: Nmi Interrupt
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.7 NMI Interrupt An NMI interrupt is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register. This pin cannot be used as an input port.
Page 137: Address Match Interrupt
M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt 12.9 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi register. Use the AIER0 and AIER1 bits in the AIER register and AIER20 and AIER21 bits in the AIER2 register to enable or disable the interrupt.
Page 138 M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0009h XXXXXX00b AIER Bit Symbol Bit Name Function Address Match Interrupt 0 0 : Interrupt disabled AIER0 Enable Bit 1 : Interrupt enabled Address Match Interrupt 1...
Page 139: 13. Watchdog Timer
M16C/62P Group (M16C/62P, M16C/62PT) 13. Watchdog Timer 13. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.
Page 140: Count Source Protective Mode
M16C/62P Group (M16C/62P, M16C/62PT) 13. Watchdog Timer Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 000Fh 00XXXXXXb Bit Symbol Bit Name Function — High-order Bit of Watchdog Timer (b4-b0) Cold Start / Warm Start Discrimination 0 : Cold Start WDC5 (1, 2)
Page 141: 14. Dmac
M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC 14. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address.
Page 142 M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC Table 14.1 DMAC Specifications Item Specification No. of Channels 2 (cycle steal method) Transfer Memory Space • From any address in the 1-Mbyte space to a fixed address • From a fixed address to any address in the 1-Mbyte space •...
Page 143 M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC DMA0 Request Factor Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03B8h DM0SL Bit Name Function Bit Symbol DSEL0 DMA Request Factor Select Bit (NOTE 1) DSEL1 DSEL2 DSEL3 —...
Page 144 M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC DMA1 Request Factor Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03BAh DM1SL Bit Name Function Bit Symbol DSEL0 DMA Request factor Select Bit (NOTE 1) DSEL1 DSEL2 DSEL3 —...
Page 145 M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC DMAi Control Register (i=0,1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 002Ch 00000X00b DM0CON 003Ch 00000X00b DM1CON Bit Symbol Bit Name Function Transfer Unit Bit Select Bit 0 : 16 bits DMBIT 1 : 8 bits Repeat Transfer Mode Select Bit...
Page 146 M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC DMAi Source Pointer (i = 0, 1) (b23) (b19) (b16) (b15) (b8) Symbol Address After Reset 0022h to 0020h Indeterminate SAR0 0032h to 0030h Indeterminate SAR1 Function Setting Range Set the source address of transfer 00000h to FFFFFh Nothing is assigned.
Page 147: Transfer Cycles
M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC 14.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer. During memory extension and microprocessor modes, it is also affected by the BYTE pin level.
Page 148 M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address BCLK Address Dummy CPU use Source Destination CPU use cycle RD signal WR signal Data bus Dummy CPU use Source...
Page 149: Dma Transfer Cycles
M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC 14.2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 14.2 lists the DMA Transfer Cycles. Table 14.3 lists the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No.
Page 150: Dma Enable
M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC 14.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to “1” (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register is “1”...
Page 151: Channel Priority And Dma Transfer Timing
M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC 14.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to “1”...
Page 152: 15. Timers
M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers 15. Timers Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TA1IN, TA1OUT, TA2IN, TA2OUT and TB pins. Do not use the function which needs these pins. Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either Timer A (five) and Timer B (six).
Page 153 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers PCLK0 bit = 0 Clock prescaler · Main clock f1 or f2 fC32 · PLL clock XCIN 1/32 · On-chip oscillator PCLK0 bit = 1 Reset clock Set the CPSR bit in the CPSRF register to “1” (= prescaler reset) Timer B2 overflow or underflow f1 or f2...
Page 154: Timer A
M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers 15.1 Timer A Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TA1IN and TA1OUT pins of Timer A1, and TA2IN and TA2OUT pins of Timer A2 . [Precautions when using Timer A1 and Timer A2] Set the MR2 to •...
Page 155 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Timer Ai Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0396h to 039Ah TA0MR to TA4MR Bit Name Bit Symbol Function Operation Mode Select Bit b1 b0 TMOD0 0 0 : Timer mode...
Page 156 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0380h TABSR Bit Name Bit Symbol Function TA0S Timer A0 Count Start Flag 0 : Stops counting 1 : Starts counting TA1S Timer A1 Count Start Flag TA2S...
Page 157 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers One-Shot Start Flag b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 0382h ONSF Bit Symbol Bit Name Function TA0OS Timer A0 One-Shot Start Flag The timer starts counting by setting this bit to “1” w hile the TMOD1 to TMOD0 bits in the TAiMR TA1OS Timer A1 One-Shot Start Flag...
Page 158 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Clock Prescaler Reset Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0381h 0XXXXXXXb CPSRF Bit Symbol Bit Name Function — Nothing is assigned. When w rite, set to “0”. —...
Page 159: Timer Mode
M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers 15.1.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 15.1). Figure 15.8 shows TAiMR Register in Timer Mode. Table 15.1 Specifications in Timer Mode Item Specification Count source f1, f2, f8, f32, fC32 Count Operation •...
Page 160 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Timer Ai Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0396h to 039Ah TA0MR to TA4MR Bit Name Bit Symbol Function TMOD0 Operation Mode Select Bit b1 b0 0 0 : Timer mode TMOD1...
Page 161: Event Counter Mode
M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers 15.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timer A2, A3 and A4 can count two-phase external signals. Table 15.2 lists Specifications in Event Counter Mode (when not processing two-phase pulse signal).
Page 162 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Timer Ai Mode Register (i=0 to 4) (when not using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0396h to 039Ah TA0MR to TA4MR Bit Name Bit Symbol Function TMOD0...
Page 163 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Table 15.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with Timer A2, A3 and A4) Item Specification Count Source • Two-phase pulse signals input to TAiIN or TAiOUT pins (i=2 to 4) Count Operation •...
Page 164 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Timer A2 Mode Register (i=2 to 4) (when using two-phase pulse signal processing) b7 b6 b5 b4 b2 b1 b0 0 0 0 1 Symbol Address After Reset 0398h to 039Ah TA2MR to TA4MR Bit Name Bit Symbol Function...
Page 165 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers 15.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-phase pulse signal processing. This function can only be used in Timer A3 event counter mode during two-phase pulse signal processing, free- running type, x4 processing, with Z-phase entered from the ZP pin.
Page 166: One-Shot Timer Mode
M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers 15.1.3 One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger (see Table 15.4). When the trigger occurs, the timer starts up and continues operating for a given period. Figure 15.12 shows the TAiMR Register in One-Shot Timer Mode.
Page 167 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Timer Ai Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0396h to 039Ah TA0MR to TA4MR Bit Name Bit Symbol Function TMOD0 Operation Mode Select Bit b1 b0 1 0 : One-shot timer mode TMOD1...
Page 168: Pulse Width Modulation (Pwm) Mode
M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers 15.1.4 Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 15.5). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 15.13 shows TAiMR Register in PWM Mode.
Page 169 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Timer Ai Mode Register (i= 0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0396h to 039Ah TA0MR to TA4MR Bit Name Bit Symbol Function TMOD0 Operation Mode Select Bit b1 b0 1 1 : PWM mode TMOD1...
Page 170 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers × (2 − 1) 1 / f Count source “H” Input signal to TAiIN pin “L” Trigger is not generated by this signal × n 1 / f “H” PWM pulse output from TAiOUT pin “L”...
Page 171: Timer B
M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers 15.2 Timer B Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TB1IN pin of Timer B1. [Precautions when using TimerB2] • Event Counter Mode The external input signals cannot be counted. Set the TCK1 bit in the TB1MR register to “1”...
Page 172 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Timer Bi Mode Register (i=0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset TB0MR to TB2MR 039Bh to 039Dh 00XX0000b 035Bh to 035Dh 00XX0000b TB3MR to TB5MR Bit Name Bit Symbol Function Operation Mode Select Bit...
Page 173 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0380h TABSR Bit Name Bit Symbol Function TA0S Timer A0 Count Start Flag 0 : Stops counting 1 : Starts counting TA1S Timer A1 Count Start Flag TA2S...
Page 174: Timer Mode
M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers 15.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 15.6). Figure 15.19 shows TBiMR Register in Timer Mode. Table 15.6 Specifications in Timer Mode Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation •...
Page 175: Event Counter Mode
M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers 15.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 15.7). Figure 15.20 shows TBiMR Register in Event Counter Mode. Table 15.7 Specifications in Event Counter Mode Item...
Page 176 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Timer Bi Mode Register (i=0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset TB0MR to TB2MR 039Bh to 039Dh 00XX0000b TB3MR to TB5MR 035Bh to 035Dh 00XX0000b Bit Name Bit Symbol Function TMOD0...
Page 177: Pulse Period And Pulse Width Measurement Mode
M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers 15.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 15.8). Figure 15.21 shows TBiMR Register in Pulse Period and Pulse Width Measurement Mode.
Page 178 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Timer Bi Mode Register (i=0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset TB0MR to TB2MR 039Bh to 039Dh 00XX0000b TB3MR to TB5MR 035Bh to 035Dh 00XX0000b Bit Name Bit Symbol Function TMOD0...
Page 179 M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Count source “H” Measurement pulse “L” Transfer Transfer (indeterminate value) (measured value) Reload register counter transfer timing (NOTE 1) (NOTE 1) (NOTE 2) Timing at which counter reaches “0000h” “1” TBiS bit “0” “1” IR bit in TBiIC register “0”...
Page 180: Timer B
M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function 16. Three-Phase Motor Control Timer Function Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not use this function. Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 16.1 lists the Three-phase Motor Control Timer Functions Specifications.
Page 181 M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function INV00 to INV07: Bits in INVC0 Register INV10 to INV15: Bits in INVC1 Register DUi, DUBi: Bits in IDBi Register (i=0,1) TA1S to TA4S: Bits in TABSR Register PWCOM: Bits in TB2SC Register INV03 INV13 ICTB2 Register n=1 to 15...
Page 182 M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function Three-Phase Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 After Reset Symbol Address 0348h INVC0 Function Bit Symbol Bit Name Interrupt Enable Output 0 : The ICTB2 counter is incremented by one on the rising edge of Timer A1 reload control signal Polarity Select Bit INV00...
Page 183 M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function Three-Phase Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 After Reset Symbol Address 0349h INVC1 Function Bit Symbol Bit Name Timer A1, A2 and A4 Start 0 : Timer B2 underflow INV10 Trigger Select Bit 1 : Timer B2 underflow and w rite to Timer B2...
Page 184 M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function (1, 2, 3) Timer B2 Interrupt Generation Frequency Set Counter Symbol Address After Reset 034Dh Indeterminate ICTB2 Function Setting Range When the INV01 bit is set to “0” (the ICTB2 counter increments w henever 1 to 15 Timer B2 underflow s) and the setting value is n , Timer B2 interrupt is generated every n th time Timer B2 underflow occurs.
Page 185 M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function Timer B2 Special Mode Register b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 039Eh XXXXXX00b TB2SC Bit Name Bit Symbol Function Timer B2 Reload Timing 0 : Timer B2 underflow Sw itching Bit 1 : Timer A output at odd-numbered PWCOM...
Page 186 M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function (1, 2) Dead Time Timer Symbol Address After Reset 034Ch Indeterminate Function Setting Range If setting value is n , the timer stops w hen counting n times a count 1 to 255 source selected by the INV12 after start trigger occurs.
Page 187 M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0380h TABSR Bit Name Bit Symbol Function TA0S Timer A0 Count Start Flag 0 : Stops counting 1 : Starts counting TA1S Timer A1 Count Start Flag...
Page 188 M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function Timer Ai Mode Register (i=1, 2, 4) b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0 Symbol Address After Reset TA1MR, TA2MR 0397h, 0398h 039Ah TA4MR Bit Name Bit Symbol Function TMOD0...
Page 189 M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to “1”. When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to control three- phase PWM outputs (U, U, V, V, W and W).
Page 190 M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function Sawtooth Waveform as a Carrier Wave Sawtooth Wave Signal Wave Timer B2 Timer A4 Start Trigger Signal Timer A4 One-Shot Pulse Rewrite the IDB0 and IDB1 Transfer the counter to the three- registers phase shift register U-Phase Output...
Page 191: 17. Serial Interface
M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17. Serial Interface Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include CLK2, CTS2/RTS2 and SIN pins. Do not use the function which needs these pins. Serial interface is configured with 5 channels: UART0 to UART2, SI/O3 and SI/O4. 17.1 UARTi (i=0 to 2) Note...
Page 192 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface PCLK1 f2SIO f1SIO or f2SIO f1SIO Main clock, PLL clock, or on-chip oscillator clock f8SIO f32SIO (UART0) TXD0 RXD polarity polarity RXD0 reversing circuit reversing UART reception SMD2 toSMD0 circuit 010, 100, 101, 110 Transmit/ Receive 1/16...
Page 193 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface PCLK1 f2SIO f1SIO or f2SIO f1SIO Main clock, PLL clock, or on-chip oscillator clock f8SIO f32SIO (UART1) TXD1 RXD polarity reversing polarity RXD1 reversing circuit UART reception SMD2 to SMD0 circuit Transmit/ 010, 100, 101, 110 Receive 1/16 receive...
Page 194 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface PCLK1 f2SIO f1SIO or f2SIO f1SIO Main clock, PLL clock, or on-chip oscillator clock f8SIO f32SIO (UART2) TXD2 RXD polarity reversing polarity RXD2 circuit reversing UART reception SMD2 to SMD0 circuit Transmit/ 010, 100, 101, 110 receive Receive 1/16...
Page 195: Uart
M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface IOPOL No reverse RXDi RXD data reverse circuit Reverse Clock synchronous type UART (7 bits) PRYE UART Clock STPS (8 bits) synchronous UART(7 bits) type disabled UARTi receive register PAR enabled UART Clock synchronous type UART SMD2 to SMD0...
Page 196 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface UARTi Transmit Buffer Register (i=0 to 2) (b15) (b8) Symbol Address After Reset 03A3h to 03A2h Indeterminate U0TB 03ABh to 03AAh Indeterminate U1TB 037Bh to 037Ah Indeterminate U2TB Function Transmit data Nothing is assigned. When w rite, set to “0”. —...
Page 197 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface (1, 2, 3) UARTi Bit Rate Generator Register (i=0 to 2) Symbol Address After Reset 03A1h Indeterminate U0BRG 03A9h Indeterminate U1BRG 0379h Indeterminate U2BRG Function Setting Range Assuming that set value = n, UiBRG divides the count source by n + 1 00h to FFh NOTES : Write to this register w hile serial interface is neither transmitting nor receiving.
Page 198 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface UARTi Transmit/Receive Mode Register (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03A0h, 03A8h, 0378h U0MR to U2MR Bit Symbol Bit Name Function Serial I/O Mode Select Bit b2 b1 b0 0 0 0 : Serial interface disabled SMD0...
Page 199 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface UARTi Transmit/Receive Control Register 0 (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03A4h, 03ACh, 037Ch 00001000b U0C0 to U2C0 Bit Name Function Bit Symbol UiBRG Count Source b1 b0 CLK0 Select Bit...
Page 200 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface UARTi Transmit/Receive Control Register 1 (i=0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03A5h, 03ADh 00XX0010b U0C1, U1C1 Bit Symbol Bit Name Function Transmit Enable Bit 0 : Transmission disabled 1 : Transmission enabled Transmit Buffer Empty Flag 0 : Data present in UiTB register...
Page 201 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface UART Transmit/Receive Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03B0h X0000000b UCON Bit Symbol Bit Name Function UART0 Transmit Interrupt Factor 0 : Transmit buffer empty (Tl = 1) U0IRS Select Bit 1 : Transmission completed (TXEPT = 1)
Page 202 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface UARTi Special Mode Register 2 (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 036Eh, 0372h, 0376h X0000000b U0SMR2 to U2SMR2 Bit Name Function Bit Symbol C Mode Select Bit 2 See Table 17.13 I C Mode Functions IICM2...
Page 203 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface UARTi Special Mode Register 4 (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 036Ch, 0370h, 0374h U0SMR4 to U2SMR4 Bit Name Function Bit Symbol Start Condition Generate Bit 0 : Clear STAREQ 1 : Start...
Page 204: Clock Synchronous Serial I/O Mode
M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 17.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 17.2 lists the Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode.
Page 205 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Table 17.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Function UiTB 0 to 7 Set transmission data UiRB 0 to 7 Reception data can be read Overrun error flag UiBRG 0 to 7 Set a bit rate...
Page 206 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Table 17.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 17.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 17.4 lists the P6_4 Pin Functions during clock synchronous serial I/O mode.
Page 207 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface (1) Example of Transmit Timing (when internal clock is selected) Transfer clock “1” TE bit in “0” Data is set in the UiTB register UiC1 register “1” TI bit in UiC1 register “0” Data is transferred from the UiTB register to the UARTi transmit register “H”...
Page 208 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below. • Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to “0”...
Page 209 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 17.15 shows the Transfer Format. (1) When the UFORM bit in the UiC0 register = 0 (LSB first) CLKi TXDi RXDi...
Page 210 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.1.5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register.
Page 211 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.1.7 CTS/RTS Function When the CTS function is used transmit and receive operation start when “L” is applied to the CTSi/RTSi (i=0 to 2) pin. Transmit and receive operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched to “H”...
Page 212: Clock Asynchronous Serial I/O (Uart) Mode
M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. Table 17.5 lists the UART Mode Specifications. Table 17.5 UART Mode Specifications Item Specification...
Page 213 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Table 17.6 Registers to Be Used and Settings in UART Mode Register Function UiTB 0 to 8 Set transmission data UiRB 0 to 8 Reception data can be read OER,FER,PER,SUM Error flag UiBRG 0 to 7 Set a bit rate UiMR...
Page 214 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Table 17.7 lists the functions of the input/output pins during UART mode. Table 17.8 lists the P6_4 Pin Functions. Note that for a period from when the UARTi operating mode is selected to when transfer starts, the TXDi pin outputs an “H”...
Page 215 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface (1) 8-bit Data Transmit Timing (with a parity and 1 stop bit) The transfer clock stops momentarily, because an “H” single is applied to the CTS pin, when the stop bit is verified. The transfer clock resumes running as soon as an “L”...
Page 216 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface • Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit) UiBRG count source “1” RE bit in UiC1 register “0” Stop bit Start bit RXDi Sampled “L” Receive data taken in Transfer clock Reception triggered when transfer clock...
Page 217 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.2.2 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below. • Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to “0” (reception disabled) (2) Set the RE bit in the UiC1 register to “1”...
Page 218 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.2.4 Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 17.22 shows Serial Data Logic Switching. (1) When the UiLCH bit in the UiC1 Register = 0 (No Reverse) “H”...
Page 219 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.2.6 CTS/RTS Function When the CTS function is used transmit operation start when “L” is applied to the CTSi/RTSi (i=0 to 2) pin. Transmit operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched to “H” during a transmit operation, the operation stops before the next data.
Page 220 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.3 Special Mode 1 (I C mode) C mode is provided for use as a simplified I C interface compatible mode. Table 17.10 lists the specifications of the I C mode. Table 17.11 to 17.12 lists the registers used in the I C mode and the register values set.
Page 221 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Start and stop condition generation block SDAi DMA0, DMA1 request STSPSEL=1 (UART1: DMA0 only) SDA(STSP) Delay SCL(STSP) circuit STSPSEL=0 IICM2=1 Transmission UARTi transmit, register NACK interrupt ACKC=1 ACKC=0 request IICM=1 and UARTi IICM2=0 SDHI ACKD register DMA0...
Page 222 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Table 17.11 Registers to Be Used and Settings in I C Mode (1) Register Function Master Slave UiTB 0 to 7 Set transmission data Set transmission data UiRB 0 to 7 Reception data can be read Reception data can be read ACK or NACK is set in this bit ACK or NACK is set in this bit...
Page 223 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Table 17.12 Registers to Be Used and Settings in I C Mode (2) Register Function Master Slave UiSMR3 0, 2, 4 and NODC Set to “0” Set to “0” CKPH See Table 17.13 I C Mode Functions See Table 17.13 I C Mode Functions...
Page 224 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Table 17.13 C Mode Functions Function Clock Synchronous Serial I/O C Mode (SMD2 to SMD0 = 010b, IICM = 1) Mode (SMD2 to SMD0 = 001b, IICM2 = 0 IICM2 = 1 IICM = 0) (NACK/ACK interrupt) (UART transmit/receive interrupt) CKPH = 0...
Page 225 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface (1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi D8 (ACK, NACK) SDAi ACK interrupt (DMA1 request), NACK interrupt...
Page 226 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state.
Page 227 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Table 17.14 STSPSEL Bit Functions Function STSPSEL = 0 STSPSEL = 1 Output of SCLi and SDAi Pins Output of transfer clock and data Output of a start/stop condition Output of start/stop condition is according to the STAREQ, accomplished by a program using RSTAREQ and STPREQ bit...
Page 228 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 17.26 Transfer to UiRB Register and Interrupt Timing. The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin.
Page 229 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.3.8 Initialization of Transmission/Reception If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial interface operates as described below. • The transmit shift register is initialized, and the content of the UiTB register is transferred to the transmit shift register.
Page 230: Special Mode 2
M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.4 Special Mode 2 Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 17.15 lists the Special Mode 2 Specifications. Table 17.16 lists the Registers to Be Used and Settings in Special Mode 2.
Page 231 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface P1_3 P1_2 P9_3 P7_2(CLK2) P7_2(CLK2) P7_1(RXD2) P7_1(RXD2) P7_0(TXD2) P7_0(TXD2) Microcomputer Microcomputer (Master) (Slave) P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) Microcomputer (Slave) Figure 17.29 Serial Bus Communication Control Example (UART2) Rev.2.41 Jan 10, 2006 Page 216 of 390 REJ09B0185-0241 http://www.xinpian.net 提供单片机解密、IC解密、芯片解密业务...
Page 232 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Table 17.16 Registers to Be Used and Settings in Special Mode 2 Register Function UiTB 0 to 7 Set transmission data UiRB 0 to 7 Reception data can be read Overrun error flag UiBRG 0 to 7 Set a bit rate...
Page 233 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register. Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
Page 234 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface “H” Slave control input “L” “H” Clock input (CKPOL=0, CKPH=0) “L” Clock input “H” (CKPOL=1, CKPH=0) “L” Data output timing “H” “L” Data input timing Indeterminate NOTES : 1. UART2 output is an N-channel open drain and must be pulled-up externally. Figure 17.31 Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) “H”...
Page 235: Special Mode 3 (Ie Mode)
M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.5 Special Mode 3 (IE mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 17.17 lists the Registers to Be Used and Settings in IE Mode. Figure 17.33 shows the Bus Collision Detect Function-Related BitsBus Collision Detect Function-Related Bits.
Page 236 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface (1) The ABSCS Bit in the UiSMR Register (Bus collision detect sampling clock select) (i=0 to 2) If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Transfer clock TXDi RXDi Trigger signal is applied to the TAjIN pin...
Page 237: Special Mode 4 (Sim Mode) (Uart2)
M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected. Table 17.18 lists the SIM Mode Specifications.
Page 238 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Table 17.19 Registers to Be Used and Settings in SIM Mode Register Function U2TB 0 to 7 Set transmission data U2RB 0 to 7 Reception data can be read OER,FER,PER,SUM Error flag U2BRG 0 to 7 Set a bit rate U2MR...
Page 239 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface (1) Transmit Timing Transfer clock “1” TE bit in U2C1 register “0” (Note 1) Data is written to the UARTi register “1” TI bit in U2C1 register “0” Data is transferred from the UiTB register to the UARi transmit register Stop Parity...
Page 240 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Microcomputer SIM card TXD2 RXD2 Figure 17.35 SIM Interface Connection 17.1.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to “1”. The parity error signal is output when a parity error is detected while receiving data. This is achieved by pulling the TXD2 output low with the timing shown in Figure 17.36.
Page 241 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.1.6.2 Format When direct format, set the PRYE bit in the U2MR register to “1”, the PRY bit to “1”, the UFORM bit in the U2C0 register to “0” and the U2LCH bit in the U2C1 register to “0”. When data are transmitted, data set in the U2TB register are transmitted with the even-numbered parity, starting from D0.
Page 242: Si/O3 And Si/O4
M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.2 SI/O3 and SI/O4 Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include SIN3 pin of SI/O3. SI/O3 is only for transmission. Reception is impossible. SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os. Figure 17.38 shows the SI/O3 and SI/O4 Block Diagram, and Figure 17.39 to Figure 17.40 show the SI/O3 and SI/O4- related registers.
Page 243 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface SI/Oi Control Register (i=3, 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0362h 01000000b 0366h 01000000b Bit Symbol Bit Name Function Internal Synchronous b1 b0 Clock Select Bit 0 0 : Selecting f1SIO or f2SIO SMi0 0 1 : Selecting f8SIO...
Page 244 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface (1, 2, 3) SI/Oi Bit Rate Generation Register (i=3, 4) Symbol Address After Reset 0363h Indeterminate S3BRG 0367h Indeterminate S4BRG Function Setting Range Assuming that set value = n, BRGi divides the count source by n + 1 00h to FFh NOTES : Write to this register w hile serial interface is neither transmitting nor receiving.
Page 245 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Table 17.20 SI/O3 and SI/O4 Specifications Item Specification Transfer Data Format • Transfer data length: 8 bits Transfer Clock • SMi6 bit in SiC (i=3, 4) register = 1 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f8SIO, f32SIO.
Page 246: Si/Oi Operation Timing
M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.2.1 SI/Oi Operation Timing Figure 17.41 shows the SI/Oi Operation Timing. 0.5 to 1.0 cycle (max.) "H" SI/Oi internal clock "L" "H" CLKi output "L" "H" Signal written to the "L" SiTRR register (NOTE 2) SOUTi output "H"...
Page 247 M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface 17.2.3 Functions for Setting an S i Initial Value If the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output can be fixed high or low when not transferring.
Page 248: 18. A/D Converter
M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter 18. A/D Converter The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7, P9_5, P9_6, and P0_0 to P0_7, and P2_0 to P2_7.
Page 249 M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter CKS1 A/D conversion rate selection CKS2 φAD Software trigger A/D trigger ADTRG VREF Resistor ladder AVSS VCUT Successive conversion register ADCON1 register ADCON0 register AD0 register (16) AD1 register (16) AD2 register (16) Decoder AD3 register (16) for A/D register...
Page 250 M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03D6h 00000XXXb ADCON0 Bit Symbol Bit Name Function Analog Input Pin Select Bit Function varies w ith each operation mode A/D Operation Mode Select Bit 0 b4 b3 0 0 : One-shot mode...
Page 251 M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter A/D Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03D4h ADCON2 Bit Name Function Bit Symbol A/D Conversion Method Select 0 : Without sample and hold 1 : With sample and hold A/D Input Group Select Bit b2 b1...
Page 252 M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter A/D Register i (i=0 to 7) Symbol Address After Reset Indeterminate 03C1h to 03C0h 03C3h to 03C2h Indeterminate 03C5h to 03C4h Indeterminate 03C7h to 03C6h Indeterminate 03C9h to 03C8h Indeterminate 03CBh to 03CAh Indeterminate 03CDh to 03CCh Indeterminate...
Page 253: Mode Description
M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter 18.1 Mode Description 18.1.1 One-Shot Mode In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 18.2 shows the One-Shot Mode Specifications. Figure 18.5 shows the ADCON0 and ADCON1 Registers (One-shot Mode). Table 18.2 One-Shot Mode Specifications Item...
Page 254 M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03D6h 00000XXXb ADCON0 Bit Symbol Bit Name Function (2, 3) Analog Input Pin Select Bit b2 b1 b0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected...
Page 255: Repeat Mode
M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter 18.1.2 Repeat Mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 18.3 shows the Repeat Mode Specifications. Figure 18.6 shows the ADCON0 and ADCON1 Registers (Repeat Mode).
Page 256 M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03D6h 00000XXXb ADCON0 Bit Symbol Bit Name Function (2, 3) Analog Input Pin Select Bit b2 b1 b0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected...
Page 257: Single Sweep Mode
M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter 18.1.3 Single Sweep Mode In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 18.4 shows the Single Sweep Mode Specifications. Figure 18.7 shows the ADCON0 Register and ADCON1 Register (Single Sweep Mode).
Page 258 M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03D6h 00000XXXb ADCON0 Bit Symbol Bit Name Function Analog Input Pin Select Bit Invalid in single sw eep mode A/D Operation Mode Select b4 b3 Bit 0...
Page 259: Repeat Sweep Mode 0
M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter 18.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code. Table 18.5 shows the Repeat Sweep Mode 0 Specifications. Figure 18.8 shows the ADCON0 Register and ADCON1 Registers (Repeat Sweep Mode 0).
Page 260 M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03D6h 00000XXXb ADCON0 Bit Symbol Bit Name Function Analog Input Pin Select Bit Invalid in repeat sw eep mode 0 A/D Operation Mode Select b4 b3 Bit 0...
Page 261: Repeat Sweep Mode 1
M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter 18.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage selectively applied to all pins is repeatedly converted to a digital code. Table 18.6 shows the Repeat Sweep Mode 1 Specifications. Figure 18.9 shows the ADCON0 Register and ADCON1 Register (Repeat Sweep Mode 1).
Page 262 M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03D6h 00000XXXb ADCON0 Bit Symbol Bit Name Function Analog Input Pin Select Bit Invalid in repeat sw eep mode 1 A/D Operation Mode Select b4 b3 Bit 0...
Page 263: Function
M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter 18.2 Function 18.2.1 Resolution Select Function The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is set to “1” (10-bit conversion accuracy), the A/D conversion result is stored in the bit 0 to bit 9 in the ADi register (i = 0 to 7).
Page 264: Current Consumption Reducing Function
M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter 18.2.5 18.2.5 Current Consumption Reducing Function When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be separated using the VCUT bit in the ADCON1 register. When separated, no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
Page 265 M16C/62P Group (M16C/62P, M16C/62PT) 18. A/D Converter Microcomputer Sensor equivalent circuit R (7.8kΩ) Sampling time C (1.5pF) Sample and hold enabled: φAD Sample and hold disabled: φAD Figure 18.11 Analog Input Pin and External Sensor Equivalent Circuit Rev.2.41 Jan 10, 2006 Page 250 of 390 REJ09B0185-0241 http://www.xinpian.net...
Page 266: D/A Converter
M16C/62P Group (M16C/62P, M16C/62PT) 19. D/A Converter 19. D/A Converter This is an 8-bit, R-2R type D/A converter. These are two independent D/A converters. D/A conversion is performed by writing to the DAi register (i = 0 to 1). To output the result of conversion, set the DAiE bit in the DACON register to “1”...
Page 267 M16C/62P Group (M16C/62P, M16C/62PT) 19. D/A Converter D/A Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03DCh DACON Bit Name Function Bit Symbol D/A0 Output Enable Bit 0 : Output disabled DA0E 1 : Output enabled D/A1 Output Enable Bit 0 : Output disabled DA1E...
Page 268: Crc Calculation
M16C/62P Group (M16C/62P, M16C/62PT) 20. CRC Calculation 20. CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X + 1) to generate CRC code. The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8 bit units. After the initial value is set in the CRCD register, the CRC code is set in that register each time one byte of data is written to the CRCIN register.
Page 269 M16C/62P Group (M16C/62P, M16C/62PT) 20. CRC Calculation Setup procedure and CRC operation when generating CRC code “80C4h” • CRC operation performed by the M16C CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is divided by the generator polynomial Generator polynomial: X + 1 (1 0001 0000 0010 0001b)
Page 270: Programmable I/O Ports
M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports 21. Programmable I/O Ports Note There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in the M16C/62P (80-pin version) and the M16C/62PT (80-pin version). Set the direction bits in these ports to “1”...
Page 271: 21. Programmable I/O Ports
M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports 21.1 Port Pi Direction Register (PDi Register, i = 0 to 13) Figure 21.7 shows the PDi Registers. This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port.
Page 272 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports Pull-up selection Direction register P0_0 to P0_7, (inside dotted-line P2_0 to P2_7 included) Port latch Data bus (NOTE 1) P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_4, P5_6, (inside dotted-line P11_0 to P11_7 not included) P12_0 to P12_7 P13_0 to P13_7...
Page 273 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports Pull-up selection Direction register P6_1, P6_5, P7_2 “1” Output Data bus Port latch (NOTE 1) Switching between CMOS and Input to respective peripheral functions Pull-up selection P8_2 to P8_4 Direction register Data bus Port latch (NOTE 1) Input to respective peripheral functions...
Page 274 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports Pull-up selection Direction register P6_2, P6_6 Data bus Port latch (NOTE 1) Switching between CMOS and Nch Input to respective peripheral functions Pull-up selection Direction register P6_3, P6_7 “1” Output Port latch Data bus (NOTE 1) Switching between CMOS and Nch...
Page 275 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports Pull-up selection P10_0 to P10_3 (Inside dotted-line Direction register not included) P10_4 to P10_7 (Inside dotted-line included) Data bus Port latch (NOTE 1) Analog input Input to respective peripheral functions Pull-up selection D/A output enabled Direction register P9_3, P9_4...
Page 276 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports Pull-up selection Direction register P8_7 Data bus Port latch (NOTE 1) Pull-up selection Direction register P8_6 “1” Output Data bus Port latch (NOTE 1) NOTES: Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC. VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.
Page 277 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports (1, 2, 3) Port Pi Direction Register (i=0 to 7 and 9 to 13) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset PD0 to PD3 03E2h, 03E3h, 03E6h, 03E7h PD4 to PD7 03EAh, 03EBh, 03EEh, 03EFh PD9 to PD12...
Page 278 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports (2, 3) Port Pi Register (i=0 to 7 and 9 to 13) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03E0h, 03E1h, 03E4h, 03E5h Indeterminate P0 to P3 03E8h, 03E9h, 03ECh, 03EDh Indeterminate P4 to P7...
Page 279 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports Port P14 Control Register (128-Pin Package) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03DEh XX00XXXXb PC14 Bit Name Function Bit Symbol Port P14_0 Bit The pin level on any I/O port w hich is set for input mode can be read by reading the corresponding bit in this P140 register.
Page 280 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports Pull-up Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 03FCh PUR0 Bit Name Function Bit Symbol PU00 P0_0 to P0_3 Pull-Up 0 : Not pulled high 1 : Pulled high PU01 P0_4 to P0_7 Pull-Up...
Page 281 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports Pull-Up Control Register 2 b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 03FEh PUR2 Bit Name Function Bit Symbol PU20 P8_0 to P8_3 Pull-Up 0 : Not pulled high 1 : Pulled high PU21 P8_4 to P8_7 Pull-Up...
Page 282 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports Table 21.2 Unassigned Pin Handling in Single-chip Mode Pin Name Connection Ports P0 to P7, After setting for input mode, connect every pin to VSS via a resistor (pull- P8_0 to P8_4, P8_6 to P8_7, down);...
Page 283 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports Table 21.3 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode Pin Name Connection Ports P0 to P7, After setting for input mode, connect every pin to VSS via a resistor (pull- P8_0 to P8_4, P8_6 to P8_7, down);...
Page 284 M16C/62P Group (M16C/62P, M16C/62PT) 21. Programmable I/O Ports Microcomputer Microcomputer (Input mode) Port P6 to P14 (Input mode) Port P0 to P14 (except for P8_5) (except for P8_5) (Input mode) (Input mode) VCC1 Open (Output mode) Open (Output mode) VCC1 VCC2 Port P4_5 / CS1 HLDA...
Page 285: Flash Memory Version
M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22. Flash Memory Version Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the masked ROM version. In the flash memory version, the flash memory can perform in three rewrite modes: CPU rewrite mode, standard serial I/O mode and parallel I/O mode.
Page 286 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version Table 22.2 Flash Memory Rewrite Modes Overview Flash Memory CPU rewrite Mode Standard Serial I/O Mode Parallel I/O Mode Rewrite Mode Function The User ROM area is rewritten when The user ROM area is The boot ROM area and the CPU executes software commands.
Page 287: Memory Map
M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.1 Memory Map The flash memory contains the user ROM area and the boot ROM area. The user ROM area has space to store the microcomputer operating program in single-chip mode or memory expansion mode and a separate 4-Kbyte space as the block A.
Page 288: Boot Mode
M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.1.1 Boot Mode The microcomputer enters boot mode when a hardware reset occurs while an “H” signal is applied to the CNVSS and P5_0 pins and an “L” signal is applied to the P5_5 pin. A program in the boot ROM area is executed.
Page 289 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version ROM Code Protect Control Address b7 b6 b5 b4 b2 b1 1 1 1 Symbol Address Factory Setting 0FFFFFh ROMCP Bit Symbol Bit Name Function — Reserved Bit Set to “1” (b5-b0) ROM Code Protect Level 1 Set b7 b6 (1, 2, 3, 4)
Page 290: Cpu Rewrite Mode
M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with the microcomputer mounted on a board without using a parallel or serial programmer.
Page 291: Ew0 Mode
M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.1 EW0 Mode The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR11 bit in the FMR1 register to “0”.
Page 292 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 01B7h 00000001b FMR0 Bit Symbol Bit Name Function 0 : Busy (being w ritten or erased) RY/BY Status Flag FMR00...
Page 293 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 01B5h 0X00XX0Xb FMR1 Bit Symbol Bit Name Function — Reserved Bit The value in this bit w hen read is indeterminate (b0) EW1 Mode Select Bit 0: EW0 mode...
Page 294 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.3.1 FMR00 Bit This bit indicates the flash memory operating state. It is set to “0” while the program, block erase, erase all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is set to “1”. 22.3.3.2 FMR01 Bit The microcomputer can accept commands when the FMR01 bit is set to “1”...
Page 295 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.3.6 FMR06 Bit This is a read-only bit indicating an auto program operation state. The FMR06 bit is set to “1” when a program error occurs; otherwise, it is set to “0”. Refer to 22.3.8 Full Status Check. 22.3.3.7 FMR07 Bit This is a read-only bit indicating the auto erase operation status.
Page 296 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version Procedure to Enter EW0 Mode Rewrite control program In boot mode only Single-chip mode, memory expansion Set the FMR05 bit to “1” (user ROM area accessed) mode or boot mode Transfer the rewrite control program in CPU Set the FMR01 bit to “1”...
Page 297 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version Procedure to Enter EW1 Mode Program in the ROM Single-chip mode Set the CM0, CM1, PM1 registers Set the FMR01 bit to “1” (CPU rewrite mode enabled) after writing “0” Set the FMR11 bit to “1” (EW1 mode) after writing “0”...
Page 298 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version Low-power consumption mode or on-chip oscillator low-power consumption mode program Transfer the low-power consumption mode or on-chip oscillator low-power consumption mode Set the FMR01 bit to “1” after setting it to “0” program to a space other than the flash memory (CPU rewrite mode enabled) Jump to the low-power consumption mode or...
Page 299 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.4 Precautions on CPU Rewrite Mode 22.3.4.1 Operating Speed Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to a CPU clock frequency of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode).
Page 300 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.4.9 Writing Command and Data Write commands and data to even addresses in the user ROM area. 22.3.4.10 Wait Mode When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the WAIT instruction.
Page 301: Software Commands
M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.5 Software Commands Software commands are described below. The command code and data must be read and written in 16-bit units, to and from even addresses in the user ROM area. When writing command code, the 8 high-order bits (D15 to D8) are ignored.
Page 302 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.5.4 Program Command (40h) The program command writes 2-byte data to the flash memory. By writing “xx40h” in the first bus cycle and data to the write address in the second bus cycle, an auto program operation (data program and verify) will start. The address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle.
Page 303 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.5.5 Block Erase Command The block erase command erases each block. By writing “xx20h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the second bus cycle, an auto erase operation (erase and verify) will start in the specified block. The FMR00 bit in the FMR0 register indicates whether an auto erase operation has been completed.
Page 304 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.5.6 Erase All Unlocked Block The erase all unlocked block command erases all blocks except the block A. By writing “xxA7h” in the first bus cycle and “xxD0h” in the second bus cycle, an auto erase (erase and verify) operation will run continuously in all blocks except the block A.
Page 305 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.5.8 Read Lock Bit Status Command (71h) The read lock bit status command reads the lock bit state of a specified block. By writing “xx71h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the second bus cycle, the FMR16 bit in the FMR1 register stores information on whether or not the lock bit of a specified block is locked.
Page 306: Data Protect Function
M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.6 Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit to “0” (lock bit enabled). The lock bit allows each block to be individually protected (locked) against program and erase.
Page 307 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version Table 22.5 Status Register Bits in Status Bit in FMR0 Definition Value after Status name Register Register “0” “1” Reset − − − − SR0 (D0) Reserved − − − − SR1 (D1) Reserved −...
Page 308: Full Status Check
M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.3.8 Full Status Check If an error occurs when a program or erase operation is completed, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating a specific error. Therefore, execution results can be confirmed by checking these bits (full status check).
Page 309 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version F u ll s ta tu s c h e c k F M R 0 6 = 1 Y E S ( 1 ) E x e c u te th e c le a r s ta tu s re g is te r c o m m a n d a n d s e t th e S R 4 a n d S R 5 a n d C o m m a n d b its to “0 ”...
Page 310: Standard Serial I/O Mode
M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.4 Standard Serial I/O Mode In standard serial I/O mode, the serial programmer supporting the M16C/62P Group (M16C/62P, M16C/62PT) can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer.
Page 311 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version Table 22.7 Pin Functions (Flash Memory Standard Serial I/O Mode) Power Name Description Supply − VCC1, VCC2, Power Input Apply the Flash Program, Erase Voltage to VCC1 pin and VCC2 to the VCC2 pin. The VCC apply condition is that VCC2 ≤...
Page 312 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version M16C/62P Group (M16C/62P) Flash Memory Version BUSY SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Mode setup method Signal...
Page 313 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Flash Memory Version BUSY SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Connect Mode setup method oscillator...
Page 314 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Flash Memory Version BUSY SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Connect Mode setup method oscillator...
Page 315 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version M16C/62P Group (M16C/62P, M16C/62PT) Flash Memory Version BUSY SCLK 9 10 11 12 13 14 15 16 17 18 19 20 Mode setup method Signal Value CNVSS VCC1 Connect oscillator RESET VSS to VCC1 circuit.
Page 316: Example Of Circuit Application In The Standard Serial I/O Mode
M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.4.2 Example of Circuit Application in the Standard Serial I/O Mode Figure 22.19 and Figure 22.20 show example of Circuit Application in Standard Serial I/O Mode 1 and Mode 2, respectively. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer.
Page 317 M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version VCC2 Microcomputer P6_5/CLK1 P5_0(CE) TXD output P6_7/TXD1 P5_5(EPM) VCC1 Monitor output P6_4/RTS1 RXD intput P6_6/RXD1 CNVSS VCC1 VCC1 Reset input RESET P8_5/NMI User reset signal NOTES: 1. In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVSS input with a switch.
Page 318: Parallel I/O Mode
M16C/62P Group (M16C/62P, M16C/62PT) 22. Flash Memory Version 22.5 Parallel I/O Mode In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer supporting the M16C/62P Group (M16C/62P, M16C/62PT). Contact your parallel programmer manufacturer for more information on the parallel programmer.
Page 319: Electrical Characteristics
M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics 23. Electrical Characteristics 23.1 Electrical Characteristics (M16C/62P) Table 23.1 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit −0.3 to 6.5 Supply Voltage −0.3 to V Supply Voltage +0.1 −0.3 to 6.5 Analog Supply Voltage −0.3 to V Input Voltage +0.3...
Page 320 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.2 Recommended Operating Conditions (1) Standard Symbol Parameter Unit Min. Typ. Max. ≥ V Supply Voltage (V Analog Supply Voltage Supply Voltage Analog Supply Voltage HIGH Input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, 0.8V Voltage P12_0 to P12_7, P13_0 to P13_7...
Page 321 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.3 Recommended Operating Conditions (2) Standard Symbol Parameter Unit Min. Typ. Max. f(XIN) Main Clock Input Oscillation Frequency =3.0V to 5.5V =2.7V to 3.0V 20×V −44 f(XCIN) Sub-Clock Oscillation Frequency 32.768 f(Ring) On-chip Oscillation Frequency f(PLL) PLL Clock Oscillation Frequency...
Page 322 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.4 A/D Conversion Characteristics Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. − Resolution Bits Integral Non-Linearity 10bit AN0 to AN7 input, ±3 Error AN0_0 to AN0_7 input, AN2_0 to AN2_7 input, ANEX0, ANEX1 input External operation amp ±7...
Page 323 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.5 D/A Conversion Characteristics Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. − Resolution Bits − Absolute Accuracy µs Setup Time Output Resistance kΩ Reference Power Supply Input Current (NOTE 2) VREF NOTES: = −20 to 85°C / −40 to 85°C unless otherwise specified.
Page 324 10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (D7, D9, U7 and U9). 11. Customers desiring E/W failure rate information should contact their Renesas technical support representative. Table 23.8 Flash Memory Version Program / Erase Voltage and Read Operation Voltage = 0 to 60 °C(D3, D5, U3, U5), T...
Page 325 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.9 Low Voltage Detection Circuit Electrical Characteristics Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. Low Voltage Detection Voltage =0.8V to 5.5V det4 (1, 2) Reset Level Detection Voltage det3 Electric potential difference of Low Voltage det4 det3 Detection and Reset Level Detection...
Page 326 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Recommended operation voltage d(P-R) Time for Internal Power Supply Stabilization During Powering-On d(P-R) CPU clock Interrupt for (a) Stop mode release d(R-S) STOP Release Time (b) Wait mode release d(W-S) Low Power Dissipation Mode Wait Mode Release Time CPU clock d(R-S)
Page 327 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.11 Electrical Characteristics (1) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. − HIGH P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, −2.0 Output P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, Voltage P11_0 to P11_7, P14_0, P14_1 −...
Page 328 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.12 Electrical Characteristics (2) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. Power Supply Current In single-chip Mask ROM f(BCLK)=24MHz No division, PLL operation =4.0V to 5.5V) mode, the output No division, pins are open and On-chip oscillation other pins are V...
Page 329 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Timing Requirements = −20 to 85°C / −40 to 85°C unless otherwise specified) = 5V, V = 0V, at T Table 23.13 External Clock Input (XIN input) Standard Symbol Parameter Unit Min. Max. External Clock Input Cycle Time 62.5 External Clock Input HIGH Pulse Width...
Page 330 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Timing Requirements = −20 to 85°C / −40 to 85°C unless otherwise specified) = 5V, V = 0V, at T Table 23.15 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min.
Page 331 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Timing Requirements = −20 to 85°C / −40 to 85°C unless otherwise specified) = 5V, V = 0V, at T Table 23.21 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min.
Page 332 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Switching Characteristics = −20 to 85°C / −40 to 85°C unless otherwise specified) = 5V, V = 0V, at T Table 23.27 Memory Expansion and Microprocessor Modes (for setting with no wait) Standard Symbol Parameter Unit...
Page 333 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Switching Characteristics = −20 to 85°C / −40 to 85°C unless otherwise specified) = 5V, V = 0V, at T Table 23.28 Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) Standard Symbol...
Page 334 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Switching Characteristics = −20 to 85°C / −40 to 85°C unless otherwise specified) = 5V, V = 0V, at T Table 23.29 Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area access and multiplex bus selection) Standard Symbol...
Page 335 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling h(TIN-UP) su(UP-TIN) edge is selected) TAiIN input (When count on rising edge is selected)
Page 336 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics c(CK) w(CKH) w(CKL) h(C-Q) TXDi su(D-C) d(C-Q) h(C-D) RXDi w(INL) input w(INH) Figure 23.4 Timing Diagram (2) Rev.2.41 Jan 10, 2006 Page 321 of 390 REJ09B0185-0241 http://www.xinpian.net 提供单片机解密、IC解密、芯片解密业务 010-62245566 13810019655...
Page 337 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) BCLK (Separate bus) WR, WRL, WRH (Separate bus) (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input su(RDY−BCLK) h(BCLK−RDY) (Common to setting with wait and setting without wait) BCLK h(BCLK−HOLD) su(HOLD−BCLK)
Page 338 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (For setting with no wait) Read timing BCLK d(BCLK-CS) h(BCLK-CS) 25ns.max 4ns.min d(BCLK-AD) h(BCLK-AD) 25ns.max 4ns.min d(BCLK-ALE) h(BCLK-ALE) h(RD-AD) -4ns.min 25ns.max 0ns.min d(BCLK-RD) h(BCLK-RD) 25ns.max 0ns.min ac1(RD-DB) (0.5 × t -45)ns.max Hi-Z su(DB-RD)
Page 339 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) Read timing BCLK d(BCLK-CS) h(BCLK-CS) 25ns.max 4ns.min d(BCLK-AD) h(BCLK-AD) 25ns.max 4ns.min h(BCLK-ALE) h(RD-AD) d(BCLK-ALE) 0ns.min 25ns.max -4ns.min d(BCLK-RD) h(BCLK-RD) 25ns.max 0ns.min ac2(RD-DB) (1.5 ×...
Page 340 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode for 2-wait setting and external area access Read timing BCLK h(BCLK-CS) d(BCLK-CS) 4ns.min 25ns.max d(BCLK-AD) h(BCLK-AD) 25ns.max 4ns.min d(BCLK-ALE) h(RD-AD) h(BCLK-ALE) 25ns.max 0ns.min -4ns.min h(BCLK-RD) d(BCLK-RD) 0ns.min 25ns.max ac2(RD-DB) (2.5×t -45)ns.max...
Page 341 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access) Read timing BCLK h(BCLK-CS) d(BCLK-CS) 4ns.min 25ns.max h(BCLK-AD) d(BCLK-AD) 4ns.min 25ns.max d(BCLK-ALE) h(RD-AD) 25ns.max h(BCLK-ALE) 0ns.min -4ns.min h(BCLK-RD) d(BCLK-RD) 0ns.min 25ns.max ac2(RD-DB) (3.5×t -45)ns.max...
Page 342 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplex bus selection ) Read timing BCLK h(BCLK-CS) d(BCLK-CS) h(RD-CS) 4ns.min (0.5×t -10)ns.min 25ns.max d(AD-ALE) h(ALE-AD) (0.5×t -25)ns.min (0.5×t -15)ns.min Address Address...
Page 343 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection ) Read timing BCLK h(RD-CS) h(BCLK-CS) (0.5×t -10)ns.min d(BCLK-CS) 4ns.min 25ns.max d(AD-ALE) h(ALE-AD) (0.5×t -25)ns.min (0.5×tcyc-15)ns.min Address Data input /DBi h(RD-DB) dZ(RD-AD)
Page 344 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.30 Electrical Characteristics (1) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. − HIGH Output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, −0.5 Voltage P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 −...
Page 345 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.31 Electrical Characteristics (2) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. Power Supply Current In single-chip Mask ROM f(BCLK)=10MHz No division =2.7V to 3.6V) mode, the output No division, pins are open and On-chip oscillation other pins are V Flash...
Page 346 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Timing Requirements = −20 to 85°C / −40 to 85°C unless otherwise specified) = 3V, V = 0V, at T Table 23.32 External Clock Input (XIN input) Standard Symbol Parameter Unit Min. Max. External Clock Input Cycle Time (NOTE 2) External Clock Input HIGH Pulse Width...
Page 347 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Timing Requirements = −20 to 85°C / −40 to 85°C unless otherwise specified) = 3V, V = 0V, at T Table 23.34 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min.
Page 348 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Timing Requirements = −20 to 85°C / −40 to 85°C unless otherwise specified) = 3V, V = 0V, at T Table 23.40 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min.
Page 349 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Switching Characteristics = −20 to 85°C / −40 to 85°C unless otherwise specified) = 3V, V = 0V, at T Table 23.46 Memory Expansion and Microprocessor Modes (for setting with no wait) Standard Symbol Parameter Unit...
Page 350 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Switching Characteristics = −20 to 85°C / −40 to 85°C unless otherwise specified) = 5V, V = 0V, at T Table 23.47 Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) Standard Symbol...
Page 351 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Switching Characteristics = −20 to 85°C / −40 to 85°C unless otherwise specified) = 5V, V = 0V, at T Table 23.48 Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area access and multiplex bus selection) Standard Symbol...
Page 352 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During Event Counter Mode TAiIN input (When count on falling h(TIN-UP) su(UP-TIN) edge is selected) TAiIN input (When count on rising edge is selected)
Page 353 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics c(CK) w(CKH) CLKi w(CKL) h(C-Q) TXDi su(D-C) d(C-Q) h(C-D) RXDi w(INL) INTi input w(INH) Figure 23.14 Timing Diagram (2) Rev.2.41 Jan 10, 2006 Page 338 of 390 REJ09B0185-0241 http://www.xinpian.net 提供单片机解密、IC解密、芯片解密业务 010-62245566 13810019655...
Page 354 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) BCLK (Separate bus) WR, WRL, WRH (Separate bus) (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input su(RDY − BCLK) h(BCLK − RDY) (Common to setting with wait and setting without wait) BCLK h(BCLK −...
Page 355 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (for setting with no wait) Read timing BCLK d(BCLK-CS) h(BCLK-CS) 30ns.max 4ns.min d(BCLK-AD) h(BCLK-AD) 30ns.max 4ns.min d(BCLK-ALE) h(BCLK-ALE) h(RD-AD) -4ns.min 0ns.min 30ns.max d(BCLK-RD) h(BCLK-RD) 30ns.max 0ns.min ac1(RD-DB) (0.5 × t -60)ns.max Hi-Z su(DB-RD)
Page 356 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) Read timing BCLK d(BCLK−CS) h(BCLK−CS) 30ns.max 4ns.min d(BCLK−AD) h(BCLK−AD) 30ns.max 4ns.min h(BCLK−ALE) h(RD−AD) d(BCLK−ALE) −4ns.min 0ns.min 30ns.max d(BCLK−RD) h(BCLK−RD) 30ns.max 0ns.min ac2(RD−DB) (1.5 ×...
Page 357 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode ( for 2-wait setting and external area access ) Read timing BCLK h(BCLK-CS) d(BCLK-CS) 4ns.min 30ns.max d(BCLK-AD) h(BCLK-AD) 4ns.min 30ns.max d(BCLK-ALE) h(BCLK-ALE) h(RD-AD) 30ns.max 0ns.min -4ns.min d(BCLK-RD) h(BCLK-RD) 0ns.min 30ns.max ac2(RD-DB)
Page 358 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics = 3V Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access) Read timing BCLK h(BCLK-CS) d(BCLK-CS) 4ns.min 30ns.max h(BCLK-AD) d(BCLK-AD) 4ns.min 30ns.max d(BCLK-ALE) h(RD-AD) 30ns.max h(BCLK-ALE) 0ns.min -4ns.min h(BCLK-RD) d(BCLK-RD) 0ns.min 30ns.max ac2(RD-DB)
Page 359 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (For 2-wait setting, external area access and multiplex bus selection) Read timing BCLK h(BCLK-CS) d(BCLK-CS) h(RD-CS) 4ns.min (0.5 × t -10)ns.min 40ns.max d(AD-ALE) (0.5 × t h(ALE-AD) -40)ns.min (0.5 ×...
Page 360 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode For 3-wait setting, external area access and multiplex bus selection Read timing BCLK h(RD-CS) h(BCLK-CS) (0.5 × t -10)ns.min 6ns.min d(BCLK-CS) 40ns.max d(AD-ALE) (0.5 × t -40)ns.min h(ALE-AD) (0.5 ×...
Page 361: Electrical Characteristics (M16C/62Pt)
M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics 23.2 Electrical Characteristics (M16C/62PT) Table 23.49 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit −0.3 to 6.5 Supply Voltage CC2= −0.3 to 6.5 Analog Supply Voltage CC2= Input Voltage RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, −0.3 to V +0.3...
Page 362 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.50 Recommended Operating Conditions (1) Standard Symbol Parameter Unit Min. Typ. Max. Supply Voltage (V Analog Supply Voltage Supply Voltage Analog Supply Voltage HIGH Input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, 0.8V P12_0 to P12_7, P13_0 to P13_7 Voltage...
Page 363 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.51 A/D Conversion Characteristics Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. − Resolution Bits Integral Non-Linearity 10bit AN0 to AN7 input, ±3 Error AN0_0 to AN0_7 input, AN2_0 to AN2_7 input, ANEX0, ANEX1 input External operation amp ±7...
Page 364 (Rewrite prohibited) 4. Maximum number of E/W cycles for which operation is guaranteed. 5. Ta (ambient temperature)=55 °C. As to the data hold time except Ta=55 °C, please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor.
Page 365 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.56 Power Supply Circuit Timing Characteristics Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. Time for Internal Power Supply Stabilization =4.0V to 5.5V d(P-R) During Powering-On µs STOP Release Time d(R-S) µs Low Power Dissipation Mode Wait Mode d(W-S)
Page 366 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.57 Electrical Characteristics (1) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. − HIGH P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, −2.0 Output P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, Voltage P11_0 to P11_7, P14_0, P14_1 −...
Page 367 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Table 23.58 Electrical Characteristics (2) Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. Power Supply Current In single-chip Mask ROM f(BCLK)=24MHz No division, PLL operation =4.0V to 5.5V) mode, the output No division, pins are open and On-chip oscillation other pins are V...
Page 368 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Timing Requirements = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise = 5V, V = 0V, at T specified) Table 23.59 External Clock Input (XIN input) Standard Symbol Parameter Unit Min.
Page 369 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Timing Requirements = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise = 5V, V = 0V, at T specified) Table 23.60 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 370 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Timing Requirements = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise = 5V, V = 0V, at T specified) Table 23.66 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 371 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics Switching Characteristics = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise = 5V, V = 0V, at T specified) 30pF Figure 23.23 Ports P0 to P10 Measurement Circuit Rev.2.41 Jan 10, 2006 Page 356 of 390...
Page 372 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling h(TIN-UP) su(UP-TIN) edge is selected) TAiIN input (When count on rising edge is selected)
Page 373 M16C/62P Group (M16C/62P, M16C/62PT) 23. Electrical Characteristics c(CK) w(CKH) w(CKL) h(C-Q) TXDi su(D-C) d(C-Q) h(C-D) RXDi w(INL) input w(INH) Figure 23.25 Timing Diagram (2) Rev.2.41 Jan 10, 2006 Page 358 of 390 REJ09B0185-0241 http://www.xinpian.net 提供单片机解密、IC解密、芯片解密业务 010-62245566 13810019655...
Page 374: Precautions
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24. Precautions 24.1 24.1.1 Register Settings Table Table 24.1 Registers with Write-only Bits which can only be written to. Set these registers with immediate values. When establishing the next value by altering the present value, write the present value to the RAM as well as to the register.
Page 375: Reset
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.2 Reset When supplying power to the microcomputer, the power supply voltage applied to the VCC1 pin must meet the conditions of SVCC. Standard Symbol Parameter Unit Min. Typ. Max. Power supply rising gradient (V )(Voltage range 0 to 2.0) 0.05 V/ms...
Page 376 M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.3 • The ROMless version can operate only in the microprocessor mode, connect the CNVSS pin to VCC1. • When resetting CNV pin with “H” input, contents of internal ROM cannot be read out. Rev.2.41 Jan 10, 2006 Page 361 of 390...
Page 377 M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.4 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. Standard Symbol Parameter Unit Min. Typ. Max. Power supply ripple allowable frequency (V (ripple) Power supply ripple allowable =5V) P-P(ripple) amplitude voltage...
Page 378: Power Control
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.5 Power Control • When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized. • Set the MR0 bit in the TAiMR register (i=0 to 4) to “0” (pulse is not output) to use the timer A to exit stop mode.
Page 379 M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions • Suggestions to reduce power consumption Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
Page 380 M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.6 Protect Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to “1”.
Page 381: Interrupt
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.7 Interrupt 24.7.1 Reading address 00000h Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000h during the interrupt sequence.
Page 382 M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.7.4 Changing the Interrupt Generate Factor If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0”...
Page 383 M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.7.6 Rewrite the Interrupt Control Register (a) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register. (b) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used.
Page 384: Dmac
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.8 DMAC 24.8.1 Write to DMAE Bit in DMiCON Register When both of the conditions below are met, follow the steps below. Conditions • The DMAE bit is set to “1” again while it remains set (DMAi is in an active state). •...
Page 385: Timers
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.9 Timers 24.9.1 Timer A 24.9.1.1 Timer A (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts). Always make sure the TAiMR register is modified while the TAiS bit remains “0”...
Page 386 M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.9.1.3 Timer A (One-shot Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
Page 387: Timer B
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.9.2 Timer B 24.9.2.1 Timer B (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains “0”...
Page 388: Serial Interface
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.10 Serial interface 24.10.1 Clock Synchronous Serial I/O 24.10.1.1 Transmission/reception With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmission side that the reception has become ready.
Page 389: Uart
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.10.2 UART 24.10.2.1 Special Mode 1(I C Mode) When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register to “0” and wait for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ, RSTAREQ and STPREQ) from “0”...
Page 390: A/D Converter
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.11 A/D Converter Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref connected), start A/D conversion after passing 1 µs or longer.
Page 391 M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incorrect value may be stored in the ADi register.
Page 392: Programmable I/O Ports
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.12 Programmable I/O Ports If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase output forcible cutoff by input on NMI pin enabled), the P7_2 to P7_5, P8_0 and P8_1 pins go to a high-impedance state. Setting the SM32 bit in the S3C register to “1”...
Page 393: Electric Characteristic Differences Between Mask Rom And Flash Memory Version Microcomputers
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.13 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests conducted in the flush memory version.
Page 394: Flash Memory Version
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.15 Flash Memory Version 24.15.1 Functions to Inhibit Rewriting Flash Memory Rewrite ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode.
Page 395: Operation Speed
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.15.8 Operation speed Before entering CPU rewrite mode (EW0 or EW1 mode), set the CM11 bit in the CM1 register to “0” (main clock), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and CM17 to CM16 bits in the CM1 register.
Page 396: Dma Transfer
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.15.13 DMA transfer In EW1 mode, make sure that no DMA transfers will occur while the FMR00 bit in the FMR0 register = 0 (during the auto program or auto erase period). 24.15.14 Regarding Programming/Erasing Endurance and Execution Time As the number of programming/erasure times increases, so does the execution time for software commands (Program, Block Erase, Erase All Unlock Blocks, and Lock Bit Program).
Page 397: Noise
M16C/62P Group (M16C/62P, M16C/62PT) 24. Precautions 24.16 Noise Connect a bypass capacitor (approximately 0.1 µF) across the VCC1 and XSS pins, and VCC2 and VSS pins using the shortest and thicker possible wiring. Figure 24.5 shows the Bypass Capacitor Connection. Bypass Capacitor Connecting Pattern Connecting Pattern...
Page 398 M16C/62P Group (M16C/62P, M16C/62PT) 25. Differences Depending on Manufacturing Period 25. Differences Depending on Manufacturing Period Table 25.1 and Table 25.2 list the precautions are applicable or not applicable every chip version of M16C/62P flash and ROM external versions. Contact separately about the mask ROM version. Table 25.1 Technical Update Applicable Table of M16C/62P Flash and ROM External Versions (1) Chip Version...
Page 399 M16C/62P Group (M16C/62P, M16C/62PT) 25. Differences Depending on Manufacturing Period Table 25.2 Technical Update Applicable Table of M16C/62P Flash and ROM External Versions (2) Chip Version UPDATE Precaution TECHNICAL When supplying power to the microcomputer, the power supply voltage applied to the VCC1 pin must meet the conditions of ÷...
Page 400 M16C/62P Group (M16C/62P, M16C/62PT) Appendix 1. Package Dimensions Appendix 1.Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP128-14x20-0.50 PLQP0128KB-A 128P6Q-A 0.9g NOTE) DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
Page 401 M16C/62P Group (M16C/62P, M16C/62PT) Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP100-14x14-0.50 PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV 0.6g NOTE) DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
Page 402 M16C/62P Group (M16C/62P, M16C/62PT) Appendix 2. Difference between M16C/62P and M16C/30P Appendix 2. Difference between M16C/62P and M16C/30P Appendix Table 2.1 Function Difference (1) Item M16C/62P M16C/62A Shortest instruction 41.7ns (f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 62.5ns (f(XIN)=16MHz, VCC=4.2V to 5.5V) execution time 100ns (f(BCLK)=10MHz, VCC1=2.7 to 5.5V) 100ns (f(XIN)=10MHz, VCC=2.7V to 5.5V with software one-wait)
Page 403 M16C/62P Group (M16C/62P, M16C/62PT) Appendix 2. Difference between M16C/62P and M16C/30P Appendix Table 2.2 Function Difference (1) Item M16C/62P M16C/62A Timers A, B count Selectable: f1, f2, f8, f32, fC32 Selectable: f1, f8, f32, fC32 source Timer A two-phase Function Z-phase (counter reset) input No function Z-phase (counter reset) input pulse signal processing...
Page 404 M16C/62P Group (M16C/62P, M16C/62PT) Appendix 2. Difference between M16C/62P and M16C/30P Appendix Table 2.3 Function Difference (1) Item M16C/62P M16C/62A User ROM blocks 14 blocks: 4 Kbytes x 3, 8 Kbytes x 3, 7 blocks: 8 Kbytes x 2, 16 Kbytes x1, 32 Kbytes x1, 64 Kbytes x 7 32 Kbytes x 1, 64 Kbytes x 3 (Flash memory: max.
Page 405 M16C/62P Group (M16C/62P, M16C/62PT) Register Index Register Index .....112 .........169 INT0IC to INT5IC ........167 ........169 INVC0 TA21 ........168 ........173 INVC1 TA2MR ......237 AD0 to AD7 .........169 ......... 235 ADCON0 ........169 TA41 ......... 235 ADCON1 ........173 TA4MR ......... 236 ADCON2 ....141, 158, 172 TABSR ........
Page 406 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Jan 31, 2003 Applications are partly revised. Table 1.1.1 is partly revised. Table 1.1.3 is partly revised. Figure 1.1.2 is partly revised. Explanation of “Memory” is partly revised. Explanation of “Hardware Reset 1”...
Page 407 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Figure 1.11.9 is partly revised. WDTS Register in Figure 1.12.2 is partly revised. Figure 1.13.2 is partly revised. Figure 1.13.3 is partly revised. Figure 1.13.5 is partly revised. Table 1.13.3 is partly revised.
Page 408 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Figure 1.25.9 is partly revised. Table 1.26.1 is partly revised. Table 1.26.2 is partly revised. Note 1 of Table 1.26.3 is partly revised. Note 1 of Table 1.26.4 is partly revised. Table 1.26.6 is partly revised.
Page 409 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Figure 1.27.7 is partly revised. Explanation of “Interrupts” is partly revised. Explanation of “Writing in the User ROM Space” is partly revised. Table 1.27.4 is partly revised. Explanation of “Read Array Command”...
Page 410 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Explanation of “Low power Dissipation Mode” is partly revised. Explanation of “Entering Wait mode” is partly revised. Explanation of “(3) Stop Mode” is partly revised. Note 9 is added. Table 1.9.7 is revised.
Page 411 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Notes are deleted. (All notes are indicated in “M16C/62 GROUP (M16C/ 62P) USAGE NOTES”). 208- Note 1 of Figures 1.25.1 to 1.25.5 is partly revised. Table 1.25.1 and 1.25.2 is revised. Figure 1.25.12 is partly revised.
Page 412 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Table 1.27.7 is partly revised. 284- Figures 1.27.13 to 1.27.15 is partly revised. 287- Figures 1.27.16 and 1.27.17 is partly revised. 292- Difference in Mask ROM Version and Flash Memory Version is revised. Difference in Flash Memory Version is revised.
Page 413 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Table 8.1 is added. Note 2 in Figure 8.1 is revised. Figure 8.4 is revised. Table 8.8 is partly revised. Note 5 is added. Note in 9 Memory Space Expansion Function is added. 62-64 Figure 9.7 to 9.9 are revised.
Page 414 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Note 2 in Table 17.16 is revised. Note 2 in Table 17.17 is revised. Note 3 in Table 17.18 is added. Note in 17.2 SI/O3, SIO4 is added. Table 18.1 is revised.
Page 415 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Table 23.30 is revised. Table 23.32 is partly revised. Table 23.43 is partly revised. Figure 23.12 is partly revised. Table 23.45 is partly revised. Table 23.46 is partly revised. Table 23.47 is partly revised.
Page 416 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Figure 1.6 Pin Configuration (Top View) is partly revised. 15-17 Tables 1.10 to 1.12 Pin Characteristics for 128-Pin Package are added. 18-19 Figure 1.7 and 1.8 Pin Configuration (Top View) are partly revised. 20-21 Tables 1.13 to 1.14 Pin Characteristics for 100-Pin Package are added.
Page 417 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary 13.1 Cold Start / Warm Start moved to 5. Reset. Table 14.1 DMAC Specifications is partly revised. 14.1.3 Effect of Software Wait is partly revised. Table 16.1 Three-phase Motor Control Timer Functions Specifications is partly revised.
Page 418 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Figure 19.2 DA0 and DA1 Register is partly revised. Note 2 of Figure 19.3 D/A Converter is added. Figure 20.3 CRC Calculation is partly revised. Note 2 of Figure 21.6 I/O Pin is deleted. Table 22.1 Flash Memory Version Specifications is partly revised.
Page 419 REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Rev. Date Page Summary Table 23.54 Flash Memory Version Electrical Characteristics for 10,000 cycle products is partly revised. Standard (Min.) is partly revised. Note 5 is revised. Table 23.55 Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics is partly revised.
Page 420 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Publication Date : Rev.2.41 Jan 10, 2006 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan http://www.xinpian.net 提供单片机解密、IC解密、芯片解密业务 010-62245566 13810019655...
Page 421 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan http://www.xinpian.net 提供单片机解密、IC解密、芯片解密业务 010-62245566 13810019655...

This manual is also suitable for:

M16c/62p M16c/62pt

Renesas M16C/62P Series Hardware Manual

1 Overview

2 Central Processing Unit (CPU)

24 Precautions

3 Memory

4 Special Function Register (SFR)

5 Reset

6 Voltage Detection Circuit

7 Processor Mode

8 Bus

9 Memory Space Expansion Function

10 Clock Generation Circuit

11 Protection

12 Interrupt

13 Watchdog Timer

14 Dmac

15 Timers

16 Three-Phase Motor Control Timer Function

17 Serial Interface

18 A/D Converter

19 D/A Converter

20 CRC Calculation

21 Programmable I/O Ports

22 Flash Memory Version

23 Electrical Characteristics

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Summary of Contents for Renesas M16C/62P Series