Renesas M16C/50 Series User Manual page 654

M16C/5L Group, M16C/56 Group
VREF
AVSS
Port P0 group
AN0_0
AN0_1
AN0_2
AN0_3
AN0_4
AN0_5
AN0_6
AN0_7
Port P1/P9 group
AN2_0
AN2_1
AN2_2
AN2_3
AN2_4
AN2_5
AN2_6
AN2_7
Port P9 Group
AN3_0
AN3_1
AN3_2
CH2 to CH0: Bits in the ADCON0 register
ADSTBY : Bit in the ADCON1 register
ADGSEL1 to ADGSEL0 : Bits in the ADCON2 register
Figure 24.1 A/D Converter Block Diagram
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
0
Analog circuit
1
ADSTBY
Successive conversion register
AD0 register (16 bits)
AD1 register (16 bits)
AD2 register (16 bits)
AD3 register (16 bits)
AD4 register (16 bits)
AD5 register (16 bits)
AD6 register (16 bits)
AD7 register (16 bits)
Data bus
Port P10 group
ADGSEL1 to 0 CH2 to CH0
= 000b
= 10b
= 10b = 001b
= 10b = 010b
= 10b
= 011b
= 10b = 100b
= 10b
= 101b
= 10b = 110b
= 10b = 111b
ADGSEL1 to 0 CH2 to CH0
= 000b
= 11b
= 11b = 001b
= 11b = 010b
= 11b = 011b
= 11b = 100b
= 11b = 101b
= 11b = 110b
= 11b = 111b
ADGSEL1 to 0
CH2 to CH0
= 000b
= 01b
= 01b
= 001b
= 010b
= 01b
ADCON1 register
ADCON0 register
Decoder
for register
ADCON2 register
ADGSEL1 to 0 CH2 to CH0
= 00b = 000b
AN0
= 00b = 001b
AN1
= 010b
= 00b
AN2
= 00b = 011b
AN3
= 00b = 100b
AN4
= 00b = 101b
AN5
= 00b = 110b
AN6
= 00b = 111b
AN7
Sampling timing signal
Open-circuit detection assist
function timing generator
Switch charge/discharge
AINRST0
AINRST1
24. A/D Converter
Vref
Decoder
for channel
Comparator
selection
VIN
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 0
2 cycles of φAD
VREF
AVSS
Page 617 of 803