Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp.
Page 2 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4 How to Use This Manual This user's manual is written for the M30245 group. The reader of this manual is expected to have the basic knowledge of electric and logic circuits and microcomputers. This manual explains a function of the following kind. •...
Page 5 The figure of each register configuration describes its functions and attributes as follows : X X X r e g i s t e r S y m b o l A d d r e s s W h e n r e s e t X X X X X X B i t s y m b o l...
Page 6: Table Of Contents
Table of Contents Chapter 1. Hardware ............1 Chapter 2. Peripheral Functions Usage ......3 2.1 Protect ..........................4 2.1.1 Overview ..............................4 2.1.2 Protect Operation ............................ 5 www.DataSheet4U.com 2.2 Timer A ..........................6 2.2.1 Overview ..............................6 2.2.2 Operation of Timer A (timer mode) ...................... 12 2.2.3 Operation of Timer A (timer mode, gate function selected) ..............
Page 7 2.5.3 Operation of Serial Interface Special Function (reception in master mode with clock delay) ............................98 2.5.4 Operation of Serial Interface Special Function (transmission in slave mode ....... 102 without delay) ............................102 2.5.5 Operation of Serial Interface Special Function (reception in slave mode with ......106 clock delay) ............................
Page 8 2.12.1 Overview ............................253 2.12.2 Operation of Watchdog Timer (Watchdog timer interrupt) ............256 2.13 Address Match Interrupt Usage ................258 2.13.1 Overview of the address match interrupt usage ................258 2.13.2 Operation of Address Match Interrupt .................... 260 2.14 Key-Input Interrupt Usage ..................262 2.14.1 Overview of the key-input interrupt usage ..................
Page 9 4.3.3 8-bit Memory to 8-bit Width Data Bus Connection Example ............337 4.3.4 Two 8-bit and 16-Bit Memory to 16-Bit Width Data Bus Connection Example ......338 4.3.5 Chip Selects and Address Bus ......................339 4.4 Connectable Memories ....................340 4.4.1 Operation Frequency and Access Time ....................
Page 10: Chapter 1. Hardware
www.DataSheet4U.com Chapter 1 Hardware...
Page 11 www.DataSheet4U.com See M30245 group datasheet.
Page 12: Chapter 2. Peripheral Functions Usage
www.DataSheet4U.com Chapter 2 Peripheral Functions Usage...
Page 13: Protect
M30245 Group 2. Protect 2.1 Protect 2.1.1 Overview 'Protect' is a function that causes a value held in a register to be unchanged even when a program runs away. The following is an overview of the protect function: (1) Registers affected by the protect function The registers affected by the protect function are: (a) System clock control registers 0, 1 (addresses 0006 and 0007...
Page 14: Protect Operation
M30245 Group 2. Protect 2.1.2 Protect Operation The following explains the protect operation. Figure 2.1.2 shows the set-up procedure. (1) Setting “1” in the write-enable bit of system clock control registers 0 and 1 and frequency Operation synthesizer-related registers causes system clock control register 0 and 1 and frequency synthesizer-related registers to be in write-enabled state.
Page 15: Timer A
M30245 Group 2. Timer A 2.2 Timer A 2.2.1 Overview The following is an overview for timer A, a 16-bit timer. (1) Mode Timer A operates in one of the four modes: (a) Timer mode In this mode, the internal count source is counted. Two functions can be selected: the pulse output www.DataSheet4U.com function that reverses output from a port every time an overflow occurs, or the gate function which controls the count start/stop according to the input signal from a port.
Page 16 M30245 Group 2. Timer A (3) Frequency division ratio In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency division ratio when a down count is performed, or [FFFF - the set value + 1] becomes the frequency division ratio when an up count is performed.
Page 17 M30245 Group 2. Timer A Timer A1 interrupt control register (TA1IC) 0045 0047 Timer A2 interrupt control register (TA2IC) 0054 Timer A0 interrupt control register (TA0IC) 0057 Timer A3 interrupt control register (TA3IC) 0059 Timer A4 interrupt control register (TA4IC) www.DataSheet4U.com 0380 Count start flag (TABSR)
Page 18 M30245 Group 2. Timer A Timer Ai register (i = 0 to 4) (Note 1) Symbol Address When reset 0387 , 0386 Indeterminate (b15 0389 , 0388 Indeterminate 038B , 038A Indeterminate 038D , 038C Indeterminate 038F , 038E Indeterminate Mode Values that can be set Function...
Page 19 M30245 Group 2. Timer A Up/down flag (Note) Symbol Address When reset 0384 Bit Symbol Bit Name Function TA0UD Timer A0 up/down flag 0 : Down count TA1UD Timer A1 up/down flag 1 : Up count TA2UD Timer A2 up/down flag This specification becomes valid when the up/down flag content is TA3UD...
Page 20 M30245 Group 2. Timer A Clock prescaler reset flag Symbol Address When reset CPSRF 0381 0XXXXXXX Bit Symbol Bit Name Function Nothing is assigned. Write "0" when writing to these bits. The contents are indeterminate if read. 0 : No effect Clock prescaler reset flag CPSR 1 : Reset...
Page 21: Operation Of Timer A (Timer Mode)
M30245 Group 2. Timer A 2.2.2 Operation of Timer A (timer mode) In timer mode, choose functions from those listed in Table 2.2.1. Operations of the circled items are described below. Figure 2.2.6 shows the operation timing, and Figure 2.2.7 shows the set-up procedure. Table 2.2.1.
Page 22 M30245 Group 2. Timer A Selecting timer mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TAi OUT pin is a normal port pin) Gate function select bit b4 b3 www.DataSheet4U.com...
Page 23: Operation Of Timer A (Timer Mode, Gate Function Selected)
M30245 Group 2. Timer A 2.2.3 Operation of Timer A (timer mode, gate function selected) In timer mode, choose functions from those listed in Table 2.2.2. Operations of the circled items are described below. Figure 2.2.8 shows the operation timing, and Figure 2.2.9 shows the set-up procedure. Table 2.2.2.
Page 24 M30245 Group 2. Timer A Selecting timer mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TAi OUT pin is a normal port pin) Gate function select bit b4 b3 www.DataSheet4U.com...
Page 25: Operation Of Timer A (Timer Mode, Pulse Output Function Selected)
M30245 Group 2. Timer A 2.2.4 Operation of Timer A (timer mode, pulse output function selected) In timer mode, choose functions from those listed in Table 2.2.3. Operations of the circled items are described below. Figure 2.2.10 shows the operation timing, and Figures 2.2.11 shows the set-up proce- dure.
Page 26 M30245 Group 2. Timer A Selecting timer mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of timer mode Pulse output function select bit 1 : Pulse is output (TAi OUT pin is a pulse output pin) (Note) Gate function select bit www.DataSheet4U.com b4 b3...
Page 27: Operation Of Timer A (Event Counter Mode, Reload Type Selected)
M30245 Group 2. Timer A 2.2.5 Operation of Timer A (event counter mode, reload type selected) In event counter mode, choose functions from those listed in Table 2.2.4. Operations of the circled items are described below. Figure 2.2.12 shows the operation timing, and Figure 2.2.13 shows the set-up procedure.
Page 28 M30245 Group 2. Timer A Selecting event counter mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TAi OUT pin is a normal port pin) Count polarity select bit 0 : Counts external signal's falling edge Up/down switching cause select bit...
Page 29: Operation Of Timer A (Event Counter Mode, Free Run Type Selected)
M30245 Group 2. Timer A 2.2.6 Operation of Timer A (event counter mode, free run type selected) In event counter mode, choose functions from those listed in Table 2.2.5. Operations of the circled items are described below. Figure 2.2.14 shows the operation timing, and Figure 2.2.15 shows the set-up procedure.
Page 30 M30245 Group 2. Timer A Selecting event counter mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A TAiMR (i=0 to 4) Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TAi OUT pin is a normal port pin) Count polarity select bit 0 : Counts external signal's falling edge Up/down switching cause select bit...
Page 31: Operation Of Timer A (Two-Phase Pulse Signal Process In Event Counter Mode, Normal Mode Selected)
M30245 Group 2. Timer A 2.2.7 Operation of timer A (two-phase pulse signal process in event counter mode, normal mode selected) In processing two-phase pulse signals in event counter mode, choose functions from those listed in Table 2.2.6. Operations of the circled items are described below. Figure 2.2.16 shows the operation timing, and Figure 2.2.17 shows the set-up procedure.
Page 32 M30245 Group 2. Timer A Selecting event counter mode and functions Timer Ai mode register (i=2, 3) [Address 0398 , 0399 TAiMR (i=2, 3) Selection of event counter mode 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0”...
Page 33: Operation Of Timer A (Two-Phase Pulse Signal Process In Event Counter Mode, Multiply-By-4 Mode Selected)
M30245 Group 2. Timer A 2.2.8 Operation of timer A (two-phase pulse signal process in event counter mode, multiply-by-4 mode selected) In processing two-phase pulse signals in event counter mode, choose functions from those listed in Table 2.2.7. Operations of the circled items are described below. Figure 2.2.18 shows the operation timing, and Figure 2.2.19 shows the set-up procedure.
Page 34 M30245 Group 2. Timer A Selecting event counter mode and functions Timer Ai mode register (i= 3, 4) [Address 0399 , 039A TAiMR (i= 3, 4) Selection of event counter mode 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0”...
Page 35: Operation Of Timer A (One-Shot Timer Mode)
M30245 Group 2. Timer A 2.2.9 Operation of Timer A (one-shot timer mode) In one-shot timer mode, choose functions from those listed in Table 2.2.9. Operations of the circled items are described below. Figure 2.2.20 shows the operation timing, and Figures 2.2.21 shows the set-up procedure.
Page 36 M30245 Group 2. Timer A Selecting one-shot timer mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A 1 1 0 TAiMR (i=0 to 4) Selection of one-shot timer mode Pulse output function select bit 1 : Pulse is output External trigger select bit When internal trigger is selected, this bit can be “1”...
Page 37: Operation Of Timer A (Pulse Width Modulation Mode, 16-Bit Pwm Mode Selected)
M30245 Group 2. Timer A 2.2.10 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected) In pulse width modulation mode, choose functions from those listed in Table 2.2.10. Operations of the circled items are described below. Figure 2.2.22 shows the operation timing, and Figures 2.2.23 and 2.2.24 show the set-up procedure.
Page 38 M30245 Group 2. Timer A Selecting PWM mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A 0 1 1 TAiMR (i=0 to 4) Selection of PWM mode 1 (Must always be “1” in PWM mode) External trigger select bit 1 : Rising edge of TAiIN pin's input signal (Note 1) Trigger select bit...
Page 39 M30245 Group 2. Timer A Continued from the previous page Setting clock prescaler reset flag (This function is effective when f is selected as the count source. Reset the prescaler for generating fc by dividing the X by 32.) Clock prescaler reset flag [Address 0381 CPSRF Clock prescaler reset flag 0 : No effect...
Page 40: Operation Of Timer A (Pulse Width Modulation Mode, 8-Bit Pwm Mode Selected)
M30245 Group 2. Timer A 2.2.11 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected) In pulse width modulation mode, choose functions from those listed in Table 2.2.11. Operations of the circled items are described below. Figure 2.2.25 shows the operation timing, and Figures 2.2.26 and 2.2.27 show the set-up procedure.
Page 41 M30245 Group 2. Timer A Selecting PWM mode and functions Timer Ai mode register (i=0 to 4) [Address 0396 to 039A 1 1 0 TAiMR (i=0 to 4) Selection of PWM mode 1 (Must always be “1” in PWM mode) External trigger select bit 0 : Falling edge of TAiIN pin's input signal (Note) Trigger select bit...
Page 42 M30245 Group 2. Timer A Continued from the previous page Setting clock prescaler reset flag (This function is effective when f is selected as the count source. Reset the prescaler for generating fc by dividing the X by 32.) Clock prescaler reset flag [Address 0381 CPSRF Clock prescaler reset flag 0 : No effect...
Page 43: Precautions For Timer A (Timer Mode)
M30245 Group 2. Timer A 2.2.12 Precautions for Timer A (timer mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter.
Page 44: Precautions For Timer A (Event Counter Mode)
M30245 Group 2. Timer A 2.2.13 Precautions for Timer A (event counter mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter.
Page 45 M30245 Group 2. Timer A (5) In the case of using as “Free-Run type”, the timer register contents may be unknown when counting begins. If the timer register is set before counting has started, then the starting value will be unknown. •...
Page 46: Precautions For Timer A (One-Shot Timer Mode)
M30245 Group 2. Timer A 2.2.14 Precautions for Timer A (one-shot timer mode) (1) At reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Setting the count start flag to “0” while a count is in progress causes as follows: •...
Page 47: Precautions For Timer A (Pulse Width Modulation Mode)
M30245 Group 2. Timer A 2.2.15 Precautions for Timer A (pulse width modulation mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) The timer Ai interrupt request bit becomes “1”...
Page 48: Clock-Synchronous Serial I/O
M30245 Group 2. Clock-Synchronous Serial I/O 2.3 Clock-Synchronous Serial I/O 2.3.1 Overview Clock-synchronous serial I/O carries out 8-bit data communications in synchronization with the clock. The following is an overview of the clock-synchronous serial I/O. (1) Transmission/reception format 8-bit data (2) Transfer rate If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit www.DataSheet4U.com...
Page 49 M30245 Group 2. Clock-Synchronous Serial I/O _______ _______ The clock-synchronous serial I/O has three types of CTS/RTS functions to choose from: _______ _______ _______ _______ • CTS/RTS functions disabled CTS/RTS pin is a programmable I/O port. _______ _______ _______ _______ •...
Page 50 M30245 Group 2. Clock-Synchronous Serial I/O cessive reception mode disabled (6) Input to the serial I/O and the direction register To input an external signal to the serial I/O, slect the function select register A to I/O port and set the direction register to input.
Page 51 M30245 Group 2. Clock-Synchronous Serial I/O UARTi transmit buffer register (i= 0 to 3) (Note) Symbol Address When reset (b7) (b0) U0TB 03AB , 03AA Indeterminate U1TB 036B , 036A Indeterminate U2TB 033B , 033A Indeterminate U3TB 032B , 032A Indeterminate Function Function...
Page 52 M30245 Group 2. Clock-Synchronous Serial I/O UARTi bit rate generator (o=0 to 3) (Note 1, 2) Symbol Address When reset U0BRG 03A9 Indeterminate U1BRG 0369 Indeterminate U2BRG 0339 Indeterminate U3BRG 0329 Indeterminate Function Values that can be set Assuming that set value = n, BRGi divides the count source by to FF n + 1 Note 1: Use MOV instruction to write to this register.
Page 53 M30245 Group 2. Clock-Synchronous Serial I/O U A R T i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 ( i = 0 t o 3 ) b7 b6 b5 b 4 b 3 b 2 b 1 b 0 S y m b o l A d d r e s s...
Page 54: Operation Of Serial I/O (Transmission In Clock-Synchronous Serial I/O Mode)
M30245 Group 2. Clock-Synchronous Serial I/O 2.3.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode) In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.3.1. Operations of the circled items are described below. Figure 2.3.5 shows the operation timing, and Figures 2.3.6 and 2.3.7 show the set-up procedures.
Page 55 M30245 Group 2. Clock-Synchronous Serial I/O Example of wiring (Note) Microcomputer Receiver side IC CLKi CTSi Port www.DataSheet4U.com Note : Since T pin is N-channel open drain, this pin needs pull-up resistance. Example of operation (1) Transmission enabled (4) Transmission is complete (5) Transmit next data (2) Confirming CTS (3) Start transmission Tc...
Page 56 M30245 Group 2. Clock-Synchronous Serial I/O Setting UARTi transmit/receive mode register (i=0 to 3) UARTi transmit/receive mode register UiMR [Address 03A8 , 368 , 0338 , 328 0 0 0 1 Must be fixed to “001” (Serial I/O mode) Internal/external clock select bit 0 : Internal clock Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode...
Page 57 M30245 Group 2. Clock-Synchronous Serial I/O Continued from the previous page Setting UARTi bit rate generator (i = 0 to 3) UARTi bit rate generator [Address 03A9 , 0369 , 0339 , 0329 UiBRG (i = 0 to 3) Can be set to 00 to FF (Note) Note: Use MOV instruction to write to this register.
Page 58: Operation Of Serial I/O (Reception In Clock-Synchronous Serial I/O Mode)
M30245 Group 2. Clock-Synchronous Serial I/O 2.3.3 Operation of Serial I/O (reception in clock-synchronous serial I/O mode) In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.3.2. Operations of the circled items are described below. Figure 2.3.8 shows the operation timing, and Figures 2.3.9 and 2.3.10 show the set-up procedures.
Page 59 M30245 Group 2. Clock-Synchronous Serial I/O Example of wiring Microcomputer Transmitter side IC CLKi RTSi Port www.DataSheet4U.com Example of operation “1” Receive enable bit (RE) “0” “1” Transmit enable bit (TE) “0” Dummy data is set in UARTi transmit buffer register “1”...
Page 60 M30245 Group 2. Clock-Synchronous Serial I/O Setting UARTi transmit/receive mode register (i=0 to 3) UARTi transmit/receive mode register UiMR [Address 03A8 , 368 , 0338 , 328 1 0 0 1 Must be fixed to “001” (Serial I/O mode) Set the RxDi pin's port direction register to “0” when receiving. Internal/external clock select bit 1 : External clock (Note) Invalid in clock synchronous I/O mode...
Page 61 M30245 Group 2. Clock-Synchronous Serial I/O Continued from the previous page Reception enabled UARTi transmit/receive control register 1 UiC1 [Address 03AD , 36D , 033D , 32D Transmit enable bit 1 : Transmission enabled Receive enable bit 1 : Reception enabled (Note) www.DataSheet4U.com Writing dummy data (Note) UART0 transmit buffer register [Address 03AB...
Page 62: Precautions For Serial I/O (In Clock-Synchronous Serial I/O Mode)
M30245 Group 2. Clock-Synchronous Serial I/O 2.3.4 Precautions for Serial I/O (in clock-synchronous serial I/O mode) Transmission/reception _______ ________ (1) With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmis- ________ sion side that the reception has become ready.
Page 63 M30245 Group 2. Clock-Synchronous Serial I/O Transmission (1) With an external clock selected, perform the following set-up procedure with the CLKi pin input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the CLK polarity select bit = “1”: 1.
Page 64: Clock-Asynchronous Serial I/O (Uart)
M30245 Group 2. UART 2.4 Clock-Asynchronous Serial I/O (UART) 2.4.1 Overview UART handles communications by means of character-by-character synchronization. The transmission side and the reception side are independent of each other, so full-duplex communication is possible. The following is an overview of the clock-asynchronous serial I/O. (1) Transmission/reception format Figure 2.4.1 shows the transmission/reception format, and Table 2.4.1 shows the names and func- tions of transmission data.
Page 65 M30245 Group 2. UART (2) Transfer rate The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans- fer rate. The count source for the transfer rate register can be selected from f , and the input from the CLK pin.
Page 66 M30245 Group 2. UART (4) How to deal with an error When receiving data, read an error flag and reception data simultaneously to determine which error has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer register, then receive the data again.
Page 67 M30245 Group 2. UART (e) Bus collision detection function This function is to sample the output level of the TxD pin and the input level of the RxD pin; if their values are different, then an interrupt request occurs. The following examples are described in section 2.4.2 and 2.4.3. _______ •...
Page 68 M30245 Group 2. UART (8) Registers related to the serial I/O Figure 2.4.2 shows the memory map of serial I/O-related registers, and Figures 2.4.3 to 2.4.6 show UARTi-related registers. 0042 UART2 receive/ACK interrupt control register (S2RIC) 0043 UART1/3 Bus collision interrupt control register (S13BCNIC) 035F Interrupt cause select register (IFSR) 0048...
Page 69 M30245 Group 2. UART UARTi transmit buffer register (i= 0 to 3) (Note) Symbol Address When reset (b7) (b0) U0TB 03AB , 03AA Indeterminate U1TB 036B , 036A Indeterminate U2TB 033B , 033A Indeterminate U3TB 032B , 032A Indeterminate Function Function Bit Symbol (UART mode)
Page 70 M30245 Group 2. UART UARTi bit rate generator (o=0 to 3) (Note 1, 2) Symbol Address When reset U0BRG 03A9 Indeterminate U1BRG 0369 Indeterminate U2BRG 0339 Indeterminate U3BRG 0329 Indeterminate Function Values that can be set Assuming that set value = n, BRGi divides the count source by to FF n + 1 Note 1: Use MOV instruction to write to this register.
Page 71 M30245 Group 2. UART U A R T i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 ( i = 0 t o 3 ) b 7 b 6 b 5 b4 b 3 b 2 b 1 b 0 S y m b o l A d d r e s s...
Page 72 M30245 Group 2. UART Interrupt request cause select register Symbol Address When reset IFSR 035F Bit Symbol Bit name Function INT0 interrupt polarity 0 : One edge IFSR0 swiching bit 1 : Two edges INT1 interrupt polarity 0 : One edge www.DataSheet4U.com IFSR1 swiching bit...
Page 73: Operation Of Serial I/O (Transmission In Uart Mode)
M30245 Group 2. UART 2.4.2 Operation of Serial I/O (transmission in UART mode) In transmitting data in UART mode, choose functions from those listed in Table 2.4.4. Operations of the circled items are described below. Figure 2.4.7 shows the operation timing, and Figures 2.4.8 and 2.4.9 show the set-up procedures.
Page 74 M30245 Group 2. UART Example of wiring (Note) Microcomputer Receiver side IC CTSi Port www.DataSheet4U.com Note: Since T pin is N-channel open drain, this pin needs pull-up resistance. Example of operation When confirming stop bit, stopped transfer clock once because CTS = “H” Started transfer clock again to start transmitting immediately after confirming CTS = “L”...
Page 75 M30245 Group 2. UART Setting UARTi transmit/receive mode register (i=0 to 3) UARTi transmit/receive mode register 0 1 0 0 0 1 0 1 UiMR [Address 03A8 , 368 , 0338 , 328 Serial I/O mode select bit b2 b1 b0 1 0 1 : Transfer data 8 bits long Internal/external clock select bit 0 : Internal clock...
Page 76 M30245 Group 2. UART Continued from the previous page Setting UARTi bit rate generator (i = 0 to 3) UARTi bit rate generator [Address 03A9 , 0369 , 0339 , 0329 UiBRG (i = 0 to 3) Can be set to 00 to FF (Note) Note: Use MOV instruction to write to this register.
Page 77: Operation Of Serial I/O (Reception In Uart Mode)
M30245 Group 2. UART 2.4.3 Operation of Serial I/O (reception in UART mode) In receiving data in UART mode, choose functions from those listed in Table 2.4.5. Operations of the circled items are described below. Figure 2.4.10 shows the operation timing, and Figures 2.4.11 and 2.4.12 show the set-up procedures.
Page 78 M30245 Group 2. UART Example of wiring Microcomputer Transmitter side IC RTSi Port www.DataSheet4U.com Example of operation (4) Data is read (1) Reception enabled (3) Receiving is (2) Start reception completed BRGi's count source Receive enable “1” “0” Start bit Stop bit Sampled “L”...
Page 79 M30245 Group 2. UART Setting UARTi transmit/receive mode register (i=0 to 3) UARTi transmit/receive mode register UiMR [Address 03A8 , 368 , 0338 , 328 0 0 1 0 1 Serial I/O mode select bit (Note) b2 b1 b0 1 0 1 : Transfer data 8 bits long Internal/external clock select bit 0 : Internal clock Stop bit length select bit...
Page 80 M30245 Group 2. UART Continued from the previous page Setting UARTi bit rate generator (i = 0 to 3) UARTi bit rate generator [Address 03A9 , 0369 , 0339 , 0329 UiBRG (i = 0 to 3) Can be set to 00 to FF (Note) Note: Use MOV instruction to write to this register.
Page 81: Serial I/O Precautions (Uart Mode)
M30245 Group 2. UART 2.4.4 Serial I/O Precautions (UART Mode) Description When the level of the CLKi and CTSi pins goes to “H” (Note 1), if the UiMR register is set to any of the following, the UiERE bit in the UiC1 register is set to “1” (parity error signal output enabled).
Page 82: Operation Of Serial I/O (Transmission Used For Sim Interface)
M30245 Group 2. SIM interface 2.4.5 Operation of Serial I/O (transmission used for SIM interface) In transmitting data in UARTi (i=0 to 3) mode (used for SIM interface), choose functions from those listed in Table 2.4.6. Operations of the circled items are described below. Figure 2.4.13 shows the operation timing, and Figures 2.4.14 and 2.4.15 show the set-up procedures.
Page 83 M30245 Group 2. SIM interface Example of wiring (Note1) Microcomputer SIM card www.DataSheet4U.com Note1: TxDi pin is N-channel open drain and needs a pull-up resistance. Note2: i=0 to 3 Example of operation (when direct format) ( 1 ) T r a n s m i s s i o n e n a b l e d ( 3 ) C o n f i r m s t o p b i t (5) Dispose parity error...
Page 84 M30245 Group 2. SIM interface Setting UARTi transmit/receive mode register (i=0 to 3) UARTi transmit/receive mode register 0 1 1 0 0 1 0 1 UiMR [Address 03A8 , 368 , 0338 , 328 Serial I/O mode select bit b2 b1 b0 1 0 1 : Transfer data 8 bits long Internal/external clock select bit 0 : Internal clock...
Page 85 M30245 Group 2. SIM interface Continued from the previous page Setting UARTi bit rate generator (i = 0 to 3) UARTi bit rate generator [Address 03A9 , 0369 , 0339 , 0329 UiBRG (i = 0 to 3) Can be set to 00 to FF (Note) Note: Use MOV instruction to write to this register.
Page 86: Operation Of Serial I/O (Reception Used For Sim Interface)
M30245 Group 2. SIM interface 2.4.6 Operation of Serial I/O (reception used for SIM interface) In receiving data in UARTi (i=0 to 3) mode (used for SIM interface), choose functions from those listed in Table 2.4.7. Operations of the circled items are described below. Figure 2.4.16 shows the operation timing, and Figures 2.4.17 to 2.4.18 show the set-up procedures.
Page 87 M30245 Group 2. SIM interface Example of wiring (Note) Microcomputer SIM card www.DataSheet4U.com External clock Note1: TxDi pin is N-channel open drain and needs a pull-up resistance. Note2: i=0 to 3 Example of operation (when inversed format) ( 1 ) R e c e p t i o n e n a b l e d (3) Receiving is completed ( 5 ) P a r i t y e r r o r o c c u r r e d ( 2 ) S t a r t r e c e p t i o n...
Page 88 M30245 Group 2. SIM interface Setting UARTi transmit/receive mode register (i=0 to 3) UARTi transmit/receive mode register 0 1 0 0 1 1 0 1 UiMR [Address 03A8 , 368 , 0338 , 328 Serial I/O mode select bit (Note 1) b2 b1 b0 1 0 1 : Transfer data 8 bits long Internal/external clock select bit...
Page 89 M30245 Group 2. SIM interface Continued from the previous page Setting UARTi bit rate generator (i = 0 to 3) UARTi bit rate generator [Address 03A9 , 0369 , 0339 , 0329 UiBRG (i = 0 to 3) Can be set to 00 to FF (Note) Note: Use MOV instruction to write to this register.
Page 90: Clock Signals In Used For The Sim Interface
M30245 Group 2. SIM interface 2.4.7 Clock Signals in used for the SIM Interface In conforming to the SIM interface, the UART clock signal within the SIM card needs to conform to the UARTi (i=0 to 3) clock signal within the microprocessor. Two examples are given here as means of generating a UARTi clock signal within the microprocessor.
Page 91 M30245 Group 2. SIM interface Clock generator M30245 CARD jOUT Timer Aj counter flip-flop kOUT SIM card Timer Ak counter flip-flop internal clock www.DataSheet4U.com frequency division ratio External clock CLKi UART clock Bit rate generator UART 1/16 UARTi clock RxDi UART TxDi Note : i=0 to 3...
Page 92 M30245 Group 2. SIM interface Table 2.4.8. UARTi bit rate adjustment factor (i=0 to 3) UARTi bit UARTi bit SIM card SIM card rate rate Bit rate Bit rate internal clock internal clock generator generator F(Hz) F(Hz) set value set value 1116 1116 www.DataSheet4U.com...
Page 93 M30245 Group 2. SIM interface Table 2.4.9. TimerAi register adjustment factor SIM card SIM card Bit rate Timer Ai Timer Aj Bit rate internal clock internal clock value value F(Hz) F(Hz) 1116 1116 www.DataSheet4U.com 2232 1488 4464 1115 2976 8928 2231 1/16 5952...
Page 94: Serial Interface Special Function
M30245 Group 2. Serial Interface Special Function 2.5 Serial Interface Special Function 2.5.1 Overview _____ Serial interface special function can control communications on the serial bus using SSi input pins. The following is an overview of the serial interface special function. (1) Transmission/reception format 8-bit data www.DataSheet4U.com...
Page 95 M30245 Group 2. Serial Interface Special Function Following are some examples in which various functions (a) through (c) are selected: • Transmission Operation WITH: outputting transmission data at falling edge of transfer clock, no clock delay, master mode • Reception Operation WITH: inputting reception data at rising edge of transfer clock, clock delay, master mode •...
Page 96 M30245 Group 2. Serial Interface Special Function 0042 UART2 receive/ACK interrupt control register (S2RIC) 0043 UART1/3 Bus collision interrupt control register (S13BCNIC) 035F Interrupt cause select register (IFSR) 0048 UART1 receive/ACK/SSI1 interrupt control register (S1RIC) 0364 UART1 special mode register 4 (U1SMR4) 0049 UART0/2 Bus collision interrupt control register (S02BCNIC) 0365...
Page 97 M30245 Group 2. Serial Interface Special Function UARTi transmit buffer register (i= 0 to 3) (Note) Symbol Address When reset (b7) (b0) U0TB 03AB , 03AA Indeterminate U1TB 036B , 036A Indeterminate U2TB 033B , 033A Indeterminate U3TB 032B , 032A Indeterminate Function Function...
Page 98 M30245 Group 2. Serial Interface Special Function UARTi bit rate generator (o=0 to 3) (Note 1, 2) Symbol Address When reset U0BRG 03A9 Indeterminate U1BRG 0369 Indeterminate U2BRG 0339 Indeterminate U3BRG 0329 Indeterminate Function Values that can be set Assuming that set value = n, BRGi divides the count source by to FF n + 1 Note 1: Use MOV instruction to write to this register.
Page 99 M30245 Group 2. Serial Interface Special Function U A R T i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 ( i = 0 t o 3 ) b 7 b 6 b 5 b4 b 3 b 2 b 1 b0 S y m b o l A d d r e s s...
Page 100 M30245 Group 2. Serial Interface Special Function UARTi special mode register 1 (i= 0 to 3) Symbol Address When reset UiSMR (i=0 to 3) 03A7 , 0367 , 0337 , 0327 Function Function Bit Symbol Bit Name (clock synchronous (UART mode) serial I/O mode) 0 : Normal mode C mode...
Page 101 M30245 Group 2. Serial Interface Special Function UARTi special mode register 3 (i= 0 to 3) Symbol Address When reset UiSMR3 (i=0 to 3) 03A5 , 0365 , 0335 , 0325 Bit Symbol Bit Name Function 0 : SS function disabled SS port function 1 : SS function enabled enable bit (Note 1)
Page 102 M30245 Group 2. Serial Interface Special Function UARTi special mode register 4 (i= 0 to 3) Symbol Address When reset UiSMR4 (i=0 to 3) 03A4 , 0364 , 0334 , 0324 Bit Symbol Bit Name Function Start condition 0 : Clear STAREQ generate bit (Note 1) 1 : Start...
Page 103: Operation Of Serial Interface Special Function (Transmission In Master Mode Without Delay)
M30245 Group 2. Serial Interface Special Function 2.5.2 Operation of Serial Interface Special Function (transmission in master mode without delay) In transmitting data in serial interface special function master mode, choose functions from those listed in Table 2.5.1. Operations of the circled items are described below. Figure 2.5.8 shows the operation timing, and Figures 2.5.9 and 2.5.10 show the set-up procedures.
Page 104 M30245 Group 2. Serial Interface Special Function Example of wiring Microcomputer Receiver side IC Port www.DataSheet4U.com CLKi Example of operation (1) Output "L" at the receiver side IC (4) Transmission is complete (2) Transmission enabled (5) Transmit next data (3) Start transmission Tc Transfer clock “H”...
Page 105 M30245 Group 2. Serial Interface Special Function Setting UARTi transmit/receive mode register (i=0 to 3) UARTi transmit/receive mode register 0 0 0 1 UiMR [Address 03A8 , 368 , 0338 , 328 Must be fixed to “001” Internal/external clock select bit 0 : Internal clock Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode...
Page 106 M30245 Group 2. Serial Interface Special Function Continued from the previous page Setting UARTi transmit/receive control register 1 (i=0 to 3) UARTi transmit/receive control register 1 UiC1 [Address 03AD , 36D , 033D , 32D UARTi transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) Data logic select bit 0 : No reverse...
Page 107: Operation Of Serial Interface Special Function (Reception In Master Mode With Clock Delay)
M30245 Group 2. Serial Interface Special Function 2.5.3 Operation of Serial Interface Special Function (reception in master mode with clock delay) In receiving data in serial interface special function master mode, choose functions from those listed in Table 2.5.2. Operations of the circled items are described below. Figure 2.5.11 shows the operation timing, and Figures 2.5.12 and 2.5.13 show the set-up procedures.
Page 108 M30245 Group 2. Serial Interface Special Function Example of wiring Microcomputer Transmitter side IC Port www.DataSheet4U.com CLKi Example of operation (1) Output "L" on the transmitter side IC (2) Reception enabled (4) Reception is complete (3) Start reception (5) Read of reception data Transfer clock “H”...
Page 109 M30245 Group 2. Serial Interface Special Function Setting UARTi transmit/receive mode register (i=0 to 3) UARTi transmit/receive mode register 0 0 0 1 UiMR [Address 03A8 , 368 , 0338 , 328 Must be fixed to “001” (Note) Internal/external clock select bit 0 : Internal clock Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode...
Page 110 M30245 Group 2. Serial Interface Special Function Continued from the previous page Setting UARTi transmit/receive control register 1 (i=0 to 3) UARTi transmit/receive control register 1 0 0 0 0 UiC1 [Address 03AD , 36D , 033D , 32D UARTi transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) UARTi continuous receive mode enable bit 0 : Continuous receive mode disabled...
Page 111: Operation Of Serial Interface Special Function
M30245 Group 2. Serial Interface Special Function 2.5.4 Operation of Serial Interface Special Function (transmission in slave mode without delay) In transmitting data in serial interface special function slave mode, choose functions from those listed in Table 2.5.3. Operations of the circled items are described below. Figure 2.5.14 shows the operation timing, and Figures 2.5.15 and 2.5.16 show the set-up procedures.
Page 112 M30245 Group 2. Serial Interface Special Function Example of wiring Microcomputer Receiver side IC Port www.DataSheet4U.com CLKi Example of operation (1) Set SSi port to "L" with the output from the receiver side IC port (4) Transmission is complete (2) Transmission enabled (5) Transmit next data (3) Start transmission “1”...
Page 113 M30245 Group 2. Serial Interface Special Function Setting UARTi transmit/receive mode register (i=0 to 3) UARTi transmit/receive mode register 1 0 0 1 UiMR [Address 03A8 , 368 , 0338 , 328 Must be fixed to “001” Internal/external clock select bit 1 : External clock (Note) Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode...
Page 114 M30245 Group 2. Serial Interface Special Function Continued from the previous page Setting UARTi transmit/receive control register 1 (i=0 to 3) UARTi transmit/receive control register 1 UiC1 [Address 03AD , 36D , 033D , 32D UARTi transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) Data logic select bit www.DataSheet4U.com...
Page 115: Operation Of Serial Interface Special Function
M30245 Group 2. Serial Interface Special Function 2.5.5 Operation of Serial Interface Special Function (reception in slave mode with clock delay) In receiving data in serial interface special function slave mode, choose functions from those listed in Table 2.5.4. Operations of the circled items are described below. Figure 2.5.17 shows the operation timing, and Figures 2.5.18 and 2.5.19 show the set-up procedures.
Page 116 M30245 Group 2. Serial Interface Special Function Example of wiring Microcomputer Transmistter side IC Port www.DataSheet4U.com CLKi Example of operation (1) Set SSi port to "L" by the output from the transmitter side IC port (4) Reception is complete (2) Reception enabled (5) Read of reception data (3) Start reception “1”...
Page 117 M30245 Group 2. Serial Interface Special Function Setting UARTi transmit/receive mode register (i=0 to 3) UARTi transmit/receive mode register 1 0 0 1 UiMR [Address 03A8 , 368 , 0338 , 328 Must be fixed to “001” (Note 1) Internal/external clock select bit 1 : External clock (Note 2) Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode...
Page 118 M30245 Group 2. Serial Interface Special Function Continued from the previous page Setting UARTi transmit/receive control register 1 (i=0 to 3) UARTi transmit/receive control register 1 0 0 0 UiC1 [Address 03AD , 36D , 033D , 32D UARTi continuous receive mode enable bit 0 : Continuous receive mode disabled Data logic select bit www.DataSheet4U.com...
Page 119: Serial Sound Interface
M30245 Group 2. Serial sound interface 2.6 Serial sound interface 2.6.1 Overview The Serial Sound Interface (SSI) is a synchronous serial data interface used primary for transferring digital audio data. The bus of the 30245 Serial Sound Interface has four lines: •...
Page 120 M30245 Group 2. Serial sound interface (3) LSB/MSB first select function This function is to choose whether to transmit/receive data from bit 1 or bit 7. This is valid when the transfer data length is 8 bits long. Choose either of the following: •...
Page 121 M30245 Group 2. Serial sound interface Serial Sound Interface 0 mode register 0 (SS0MR0) 0310 0311 Serial Sound Interface 0 mode register 1 (SS0MR1) 0312 Reserved 0313 Reserved 0314 Serial Sound Interface 0 transmit buffer register (SS0TXB) www.DataSheet4U.com 0315 0316 Serial Sound Interface 0 receive buffer register (SS0RXB) 0317 0318...
Page 122 M30245 Group 2. Serial sound interface Serial Sound Interface x transmit buffer register Symbol Address When reset (b15) (b8) SSIxTXB (x = 0,1) 0000 b0 b7 Function Transmit data (Note 1) www.DataSheet4U.com Note 1: For byte access, write data to addresses 0314 and 0374 only.
Page 123 M30245 Group 2. Serial sound interface Serial Sound Interface x mode register 0 Symbol Address When reset SSIxMR0 (x = 0,1) b5 b4 b3 b2 Bit name Function Bit symbol 0 : Disable SSIEN Serial Sound Interface enable bit 1 : Enable 0 : Disable Transmitter enable bit XMTEN...
Page 124 M30245 Group 2. Serial sound interface In the case of the USB audio class, the following stream is output. Audio stream (PCM) from the PC to the M30245 USB FIFO For 16-bit data Fifth byte Fourth byte First byte Third byte Second byte f1 f0 e1 e0...
Page 125: Example Of Serial Sound Interface Operation
M30245 Group 2. Serial sound interface 2.6.2 Example of Serial Sound Interface operation When using Serial Sound Interface (SSI), the DMA is recommended for reading and writing data quickly from the receive buffer to the transmit buffer. A programming example using DMA is shown below Figure 2.6.5 shows an example of Serial Sound Interface transmit timing, and Figure 2.6.6 shows an example of Serial Sound Interface receive timing.
Page 126 M30245 Group 2. Serial sound interface (Continued from the previous page.) /***** Serial Sound Interface activation routine for 16 bits *******************************************/ #ifdef OUT_Q_BIT_NO_16 ssi1mr0 = 0x01; /* SSIEN = 1 */ ssi1mr0 = 0xf1; /* 16bit / MSB justified */ ssi1mr1 = 0x21;...
Page 127 M30245 Group 2. Serial sound interface Serial Sound Interface timing (1) Fs = 48 kHz or 44.1kHz XMTEN WSDLY = 1 SCK = Min 64 × Fs (2.8MHz)/ Max192 × Fs(9.2MHz) www.DataSheet4U.com SCKP = 1, WSP = 0 SCKP = 0, WSP = 0 SCKP = 1, WSP = 1 SCKP = 0, WSP = 1 XMTFMT = 0:MSB first, XMTFMT = 1:LSB first...
Page 128 M30245 Group 2. Serial sound interface Serial Sound Interface timing (3) Fs = 48 kHz or 44.1kHz RXEN SCK = Min 64 × Fs (2.8MHz)/ Max192 × Fs(9.2MHz) www.DataSheet4U.com SCKP = 1, WSP = 0 SCKP = 0, WSP = 0 SCKP = 1, WSP = 1 SCKP = 0, WSP = 1 RFMT1 = 0:MSB first, RFMT1 = 1:LSB first...
Page 129: Precautions For Serial Sound Interface
M30245 Group 2. Serial sound interface 2.6.3 Precautions for Serial Sound Interface Description For flash memory version SSI transmission data must be latched as the following timing by a receiver. • SCKP=0 (falling edge) : within 3 BCLK cycles from the rising edge of SCK •...
Page 130: Frequency Synthesizer (Pll)
M30245 Group 2. Frequency synthesizer (PLL) 2.7 Frequency synthesizer (PLL) This paragraph explains the registers setting method and the notes related to the frequency synthesizer (PLL circuit). 2.7.1 Overview The frequency synthesizer generates the 48MHz clock that is necessary for the USB block and the f clock.
Page 131 M30245 Group 2. Frequency synthesizer (PLL) Frequency Synthesizer Control register Symbol Address When reset 03DC 01100000 Bit Symbol Bit Name Function 0 : Disabled Frequency synthesizer enable bit 1 : Enabled b2 b1 VCO0 0 0 : Lowest gain www.DataSheet4U.com 0 1 : Low gain VCO gain control bit 1 0 : High gain (Note 1)
Page 132 M30245 Group 2. Frequency synthesizer (PLL) Frequency Synthesizer Prescaler Register Symbol Address When reset 03DE 11111111 Bit Symbol Bit Name Function Frequency synthesizer Generates f prescaler value =f(X )/2(n + 1) n: FSP value www.DataSheet4U.com Frequency Synthesizer Multiply Register Symbol Address When reset 03DD...
Page 133: Operation Of Frequency Synthesizer
M30245 Group 2. Frequency synthesizer (PLL) 2.7.2 Operation of frequency synthesizer The following explains how to setup after hardware reset. Table 2.7.1 to 2.7.3 show frequency synthe- sizer related registers setting examples. Operation (1) Cancel the protect register. (2) Set the frequency synthesizer related registers to generate the 48MHz clock that is necessary for the f (3) Enable the frequency synthesizer by setting frequency synthesizer control register.
Page 134 M30245 Group 2. Frequency synthesizer (PLL) Frequency Multiplier is generated via the Frequency Synthesizer Mul-tiply register (FSM: address 03DD ). When the Frequency Multiply register is set to 255, multiplication is disabled and f . The value of n should be set so that f becomes 48MHz.
Page 135: Precautions For Frequency Synthesizer
M30245 Group 2. Frequency synthesizer (PLL) 2.7.3 Precautions for Frequency synthesizer (1) Bits 6 and 5 of frequency synthesizer control register are set to (bit6, bit5)=(1, 1) at reset. When using the frequency synthesizer, we recommended to set to (bit6, bit5)=(1, 0). (2) Set f to 12 MHz or lower.
Page 136: Usb Function
M30245 Group 2. USB function 2.8 USB function 2.8.1 Overview The USB function control unit of the M30245 group is compliant with USB2.0 specification and supports Full-Speed transfer. USB2.0 specification defines the following four kinds of transfer types: Control Transfer Isochronous Transfer Interrupt Transfer Bulk Transfer...
Page 137 M30245 Group 2. USB function Interrupt Transfer This transfer is used to notify the host of aperiodic and low-frequency data from the device. For example, they include the notification of out of paper in printer and data concerning devices such as the mouse and the keyboard.
Page 138 M30245 Group 2. USB function SOF Packet: Packet to start the frame to be issued from the host for every 1ms. 8 bits 8 bits 5 bits PID Frame number CRC5 PID: SOF(0xA5) Token Packet: Packet to be issued from the host at the time of transaction start. 8 bits 7 bits 4 bits...
Page 139 M30245 Group 2. USB function Transaction A transaction is the unit in which the host CPU schedules one frame. Each transaction is config- ured with packet, and the transaction types are determined according to the configuration pat- tern. The transaction types and formats are shown below: IN transaction OUT transaction SETUP transaction...
Page 140 M30245 Group 2. USB function Communication Sequence The control transfer is used common to all devices at the time of setup, which consists of three kinds of stages being combined for one processing. The control transfer starts with setup stage. According to the content, data stage (control read transfer or control write transfer) is executed, followed by status stage being executed to finally complete one processing.
Page 141 M30245 Group 2. USB function Control Read Transfer In setup stage, host notifies the device that it is control read transfer. Then, in data stage, data are transmitted from the device to host through repetition of IN transaction. Finally, in status stage, OUT transaction is executed (that the host transmits an empty packet of data length (0) to the device) to complete the control read transfer.
Page 142 M30245 Group 2. USB function (3) Bulk Transfer Bulk IN Transfer In bulk IN transfer which data are transmitted from the device to the host CPU, IN transactions are repeated. When transmit data are available in IN FIFO, the M30245 group issues a data packet to the IN token.
Page 143 M30245 Group 2. USB function (4) Isochronous Transfer Isochronous IN Transfer In isochronous IN transfer which data are transferred from the device to the host CPU, isochronous (IN) transactions are repeated. Isochronous transaction does not have the handshake phase. The data packet consists only of DATA0.
Page 144 M30245 Group 2. USB function (6) Device State The device has states and, transits between the states. The M30245 group does not execute state transition on the hardware. Control it by the software based on requests of the related USB interrupt request.
Page 145 M30245 Group 2. USB function Attached state Configured Deconfigured www.DataSheet4U.com Suspend detected (USB suspend interrupt) Powered Suspend state state Resume detected (USB resume interrupt) USB bus reset detected (USB reset interrupt) USB bus reset detected (USB reset interrupt) Suspend detected (USB suspend interrupt) Default Suspend state...
Page 146 M30245 Group 2. USB function 02B6 USB EP1 OUT control/status register (EP1OCS) 02B7 USB control register (USBC) 000C 02B8 USB EP1 OUT max packet size register (EP1OMP) 02B9 USB Attach/Detach register (USBAD) 001F 02BA USB EP1 OUT write count register (EP1WC) 02BB USB Endpoint 0 interrupt control register (EP0IC) 0046...
Page 147 M30245 Group 2. USB function Table 2.8.2. List of USB Related Registers Items Register name Section name 2.8.2 USB function control USB control register, USB Attach/Detach register, USB endpoint enable register, USB endpoint x(x=0-4) IN FIFO data register, USB endpoint x(x=0-4) OUT FIFO data register USB function interrupt status register, 2.8.3 USB Interrupt USB function interrupt clear register,...
Page 148: Usb Function Control
M30245 Group 2. USB function 2.8.2 USB function control The USB function control unit needs to be enabled for using the USB function. The initialization procedure of the USB function control unit is explained below: (1) Related Registers USB control register This register is used to control each operation of the USB function control unit.
Page 149 M30245 Group 2. USB function USB attach/detach register This register is used to control attach/detach from the USB host without physically attaching/detaching the USB cable. •Port 9 -Second bit The port P9 operates as standard port when this bit is set to “0”. Connect a 1.5kΩ resistance between the USB D+ pin and the Uvcc pin.
Page 150 M30245 Group 2. USB function USB endpoint enable register Endpoints 1 to 4 are used to enable endpoint IN/OUT FIFOs for use. The endpoint 0 is always enabled and cannot be disabled by software. All Endpoints 1 to 4 are disabled after reset. The configuration of USB endpoint enable register is shown in Figure 2.8.11.
Page 151 M30245 Group 2. USB function USB endpoint x(x=0 to 4) OUT FIFO data register Endpoints 0 to 4 respectively have their OUT FIFOs. When data are received from the host PC, read the receive data from these registers. Access these registers in word cycle or byte cycle to the lower byte.
Page 152 M30245 Group 2. USB function (2) Enable of USB Function Control Unit The initialization procedure of the USB function control unit of the M30245 group after hardware reset is explained below. Further, for power supply being supplied from the USB, the total driving current has to be controlled to keep equal to or below 100mA.
Page 153 M30245 Group 2. USB function Invalid 12MHz (255 48MHz FSP: Frequency synthesizer prescaler FSM: Frequency synthesizer multiplier FSD: Frequency synthesizer divider www.DataSheet4U.com Figure 2.8.15. Setting example of frequency synthesizer division RESET Enable frequency synthesizer Wait for 3ms Enable USB clock USBC5 USBC7 Enable USB function control unit...
Page 154 M30245 Group 2. USB function Initialization of USB FCU Clearing the protect Protect register [Address 000A PRCR Enable bit for writing to system clock control registers 0 and 1 and frequency synthesizer related registers 1 : Write-enabled Enable bit for writing to processor mode registers 0 and 1 0 : Write-inhibited Reserved bit www.DataSheet4U.com...
Page 155 M30245 Group 2. USB function Continued from the previous page When using f as a main clock Frequency synthesizer clock control register [Address 03DB FSCCR Clock source selection bit 1 : f Divide-by-3 option 0 : Normal Note: When this bit is “1”, set FSD to “02 ”.
Page 156 M30245 Group 2. USB function Initialization of Endpoint Initialization of endpoint 0 (Control transfer) (b15) (b8) USB endpoint 0 MAXP register [Address 029A EP0MP Maximum packet size of endpoint 0 IN/OUT Setting the size and start location of IN/OUT FIFO www.DataSheet4U.com (b15) (b8)
Page 157 M30245 Group 2. USB function Continued from the previous page Initialization of endpoint x (x=1 to 4) (Bulk tranfer/Interrupt transfer/Isochronous transfer) (b15) (b8) USB endpoint x IN MAXP register EPxIMP (x=1 to 4) [Address 02A0 , 02A6 , 02AC , 02B2 Set the maximum packet size (b15) (b8)
Page 158 M30245 Group 2. USB function (3) Disable of USB Function Control Unit After the USB function control unit being enabled, if the system design requires to disable the USB function, follow the procedure below: 1: Disable the USB clock by clearing USB enable bit (USBC7) to “0”. 2: Disable the USB clock by clearing USB clock enable bit (USBC5) to “0”.
Page 159: Usb Interrupt
M30245 Group 2. USB function 2.8.3 USB Interrupt The USB related interrupts include USB suspend interrupt, USB resume interrupt, USB reset interrupt, USB endpoint 0 interrupt, USB function interrupt, and USB SOF interrupt. (1) Related Registers USB function interrupt status register This register is used to judge the USB function interrupt factor.
Page 160 M30245 Group 2. USB function USB Interrupt Status register (Note) (b8) (b15) Symbol Address When reset USBIS 0284 0000 Bit Symbol Bit Name Function INTST0 EP1 IN interrupt status flag 0 : No interrupt request EP1 OUT interrupt status flag INTST1 1 : Interrupt request issued EP2 IN interrupt status flag...
Page 161 M30245 Group 2. USB function USB Function Interrupt Clear register (b8) (b15) Symbol Address When reset USBIC 0286 0000 Bit Symbol Bit Name Function INTCL0 Clear EP1 IN interrupt status flag 0 : No action Clear EP1 OUT interrupt status flag INTCL1 1 : Clear interrupt status flag Clear EP2 IN interrupt status flag...
Page 162 M30245 Group 2. USB function USB frame number register This register is used to contain 11-bit frame number of SOF token received from the host CPU. This is the read-only register. The configuration of USB frame number register is shown in Figure 2.8.24. USB Frame Number register (Note) (b8) (b15)
Page 163 M30245 Group 2. USB function (2) USB Endpoint 0 Interrupt In the endpoint 0 interrupt, the interrupt request occurs when the data transmit/receive of endpoint 0 are completed. Set the interrupt priority level by using USB endpoint 0 interrupt control register (EP0IC: address 0046 ).
Page 164 M30245 Group 2. USB function (3) USB Function Interrupt The USB function interrupts include the endpoint x(x=1~4) IN interrupt, endpoint x(x=1~4) OUT inter- rupt, and error interrupt. An interrupt request occurs on completion of data transmit/receive or on occurrence of an error such as overrun/underrun, setting the status flag which is the factor of the interrupt request inside USB function interrupt status register to “1”.
Page 165 M30245 Group 2. USB function (4) USB Reset Interrupt This interrupt is used for detection of the USB reset. This occurs when the USB function control unit has received reset signal from the host CPU (or detected SE0 on the D+/D- line for at least 2.5µs). At this time, all the USB internal registers are made into reset state.
Page 166 M30245 Group 2. USB function (7) USB SOF (Start of Frame) Interrupt This interrupt is valid to control the isochronous transfer. When a valid SOF PID is detected, receive of an SOF packet is recognized and an interrupt request occurs. The frame number (11 bits) of the SOF packet received from the host is automatically stored in USB frame number register.
Page 167 M30245 Group 2. USB function (8) USB Function Interrupt Routine This interrupt is used to control data flow. This occurs on completion of data transmit/receive or on occurrence of an error such as overrun/underrun. When using the USB function interrupt, set the interrupt priority level at USB function interrupt control register (address 005D ) and the correspond- ing bit of USB function interrupt enable register to “1”.
Page 168 M30245 Group 2. USB function USB function interrupt control register [Address 005D USBFIC Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested USB function interrupt enable register [Address 0288 (b15) (b8) www.DataSheet4U.com USBIE EP1 IN interrupt enable bit EP1 OUT interrupt enable bit EP2 IN interrupt enable bit EP2 OUT interrupt enable bit...
Page 169 M30245 Group 2. USB function USB function interrupt request detected •Enables each interrupt by the USBIE (address 0288 ~0289 at initial routine USBIS → Read one word and store it to RAM •Clears USB interrupt status register 1, 2 by writing “1” RAM →...
Page 170: Usb Operation (Suspend/Resume Function)
M30245 Group 2. USB function 2.8.4 USB Operation (Suspend/Resume Function) The USB device has received the suspend signal from the host CPU following the power input state, and then controls power supply and shifts the state into the suspend state. And, by receiving the resume signal from the host CPU (or transmitting the resume signal to the host CPU in the case of remote wakeup), it returns to the state before shifting into the suspend state and resumes the USB communication.
Page 171 M30245 Group 2. USB function USB Power Management register (b8) (b15) Symbol Address When reset 0 0 0 USBPM 0282 0000 Bit Symbol Bit Name Function 0 : Not in suspend state SUSPEND Suspend state flag 1 : In suspend state (Note 1) (Note 2) 0 : End remote wakeup signal WAKEUP...
Page 172 M30245 Group 2. USB function (2) USB Suspend Function In the M30245 group, the USB suspend status flag (SUSPEND) of USB power management register (address 0282 ) is set to “1” when the suspend signal has been received from the host CPU (or not detected any bus activity on the D+/D- line for at least 3ms).
Page 173 M30245 Group 2. USB function (3) USB Resume Function Returning Routine from USB Suspend State To return from the USB suspend state, the M30245 group uses the USB resume interrupt occurred by receiving the resume signal from the host or the interrupt for remote wakeup for transmitting the resume signal to the host.
Page 174 M30245 Group 2. USB function - Returning Routine of USB Function Control Unit To return from the USB suspend state to the previous state, perform return control of the USB function control unit as follows. Further, clearing the bit of protect register (address 000A ) is required for changes in frequency synthesizer control register (address 03DC 1: Set frequency synthesizer enable bit of frequency synthesizer control register to “1”.
Page 175 M30245 Group 2. USB function (4) USB Suspend Interrupt Request Processing Routine When using the USB suspend interrupt, set USB suspend interrupt control register (address 0056 In the USB suspend interrupt, when the USB suspend status flag (SUSPEND) of USB power manage- ment register is set to “1”, the interrupt request occurs.
Page 176 M30245 Group 2. USB function Continued from the previous page Interrupt enable flag (I) ← “1” Stop all clocks System clock control register 1 [Address 0007 www.DataSheet4U.com All clock stop control bit 1: All clocks off (stop mode) “1” Insert at least four NOPs following JMP.B instruction after the instruction that sets the all clock stop control bit to •...
Page 177 M30245 Group 2. USB function Detection of USB resume interrupt request Clearing the protect Protect register [Address 000A PRCR Enable bit for writing to system clock control registers 0 and 1 and frequency synthesizer related registers 1 : Write-enabled www.DataSheet4U.com Setting frequency synthesizer control register Frequency synthesizer control register [Address 03DC Frequency Synthesizer enable bit...
Page 178: Usb Operation (Endpoint 0)
M30245 Group 2. USB function 2.8.5 USB Operation (Endpoint 0) Endpoint 0 is used only for control transfer. Endpoint 0 FIFO consists of total 256 bytes including IN (transmit) FIFO and OUT (receive) FIFO each respectively of 128 bytes. The starting position is allocated from the 3072nd byte to the 3327th byte of the endpoint FIFO.
Page 179 M30245 Group 2. USB function USB Function Address register (b8) (b15) Symbol Address When reset 0 0 0 0 0 0 0 0 0 USBA 0280 0000 Bit Symbol Bit Name Function 7-bit programmable Function address FUNAD6-0 function address Reserved Must always be “0”...
Page 180 M30245 Group 2. USB function - Data exceeding the one specified in the SETUP stage are required. (An OUT token is received after the DATA_END flag is set.) - Data exceeding the one specified are received in USB endpoint 0 MAXP register. Except for when an incorrect data toggle is received in the SETUP stage, on occurrence of the above condition, STALL is transmitted to the IN/OUT token with a problem.
Page 181 M30245 Group 2. USB function • SET_DATA_END bit This bit controls setting of the DATA_END flag to “1”. When the last data has been written in IN FIFO in the IN data phase or when the last data has been read from OUT FIFO in the OUT data phase, set this bit to “1”.
Page 182 M30245 Group 2. USB function USB Endpoint 0 Control and Status register (b8) (b15) Address When reset Symbol 0298 2000 EP0CS Bit Symbol Bit Name Function 0 : No setup packet or data set ready for unload 1 : Setup packet or data set ready for unload OUT_BUF_RDY flag EP0CSR0 0 : No data set ready for transmit...
Page 183 M30245 Group 2. USB function USB endpoint 0 MAXP register This register indicates the IN/OUT maximum packet size of endpoint 0. When a GET_DESCRIPTION request is received from the host CPU, write to this register to change the IN/OUT maximum packet size value of endpoint 0. Set the packet size value (8, 16 or 32 bytes) specified by control transfer.
Page 184 M30245 Group 2. USB function (2) Control Transfer: Endpoint 0 Receive The endpoint 0 receives the packet data from the host CPU in the setup stage or the data stage by the control write transfer. When the receive of a valid SETUP packet or a data packet completes, the SETUP flag and the OUT_BUF_RDY flag are automatically set to “1”, and the number of bytes of receive data are set in USB endpoint 0 OUT write count register (address 029C ).
Page 185 M30245 Group 2. USB function (3) Control Transfer: Endpoint 0 Transmit The endpoint 0 transmits the packet data to the host CPU in the data stage by the control read after completion of receive request analysis process in the setup stage. Write one packet data to be transmitted in IN FIFO.
Page 186 M30245 Group 2. USB function (4) Control Transfer: Example of Standard Device Request Receive The control transfer includes the setup stage, data stage and status stage. Which one of write transfer, read transfer and no data transfer is executed in the data stage is deter- mined by the content of the setup data acquired in the setup stage.
Page 187 M30245 Group 2. USB function Receiving of endpoint 0 setup packet Confirming of receive data (b15) (b8) USB endpoint 0 control and status register EP0CS [Address 0298 OUT_BUF_RDY flag (Note 1) 0 : Reading data packet is complete 1 : Data packet reception is compete SETUP flag 0 : Data packet reception 1 : SETUP packet reception...
Page 188 M30245 Group 2. USB function (continued from previous page) Getting of new address (address state) Setting of USB endpoint 0 control and status register (b15) (b8) USB endpoint 0 control and status register EP0CS [Address 0298 CLR_OUT_BUF_RDY bit 1 : Clear OUT_BUF_RDY flag www.DataSheet4U.com CLR_SETUP flag 1 : Clear SETUP flag...
Page 189 M30245 Group 2. USB function Receiving of endpoint 0 setup packet Confirming of receive data (b15) (b8) USB endpoint 0 control and status register EP0CS [Address 0298 OUT_BUF_RDY flag (Note 1) 0 : Reading data packet is complete 1 : Data packet reception is compete SETUP flag www.DataSheet4U.com 0 : Data packet reception...
Page 190 M30245 Group 2. USB function Continued from previous page Setting of USB endpoint 0 control and status reister (Note 1) (b15) (b8) USB endpoint 0 control and status register EP0CS [Address 0298 SET_IN_BUF_RDY bit 1 : Set IN_BUF_RDY flag to “1” SET_DATA_END bit www.DataSheet4U.com 1 : Set DATA_END flag to “1”...
Page 191: Usb Operation (Endpoints 1 To 4 Receive)
M30245 Group 2. USB function 2.8.6 USB Operation (Endpoints 1 to 4 Receive) Endpoints 1 to 4 can apply to the isochronous transfer, bulk transfer and interrupt transfer. The endpoints 1 to 4 respectively have their IN (transmit) FIFOs and OUT (receive) FIFOs. For using the endpoints 1 to 4 OUT, enable each endpoint OUT FIFO by USB endpoint enable register (address 028E ).
Page 192 M30245 Group 2. USB function (1) Related Registers USB endpoint x(x=1 to 4) OUT control and status register •OUT_BUF_STS1, OUT_BUF_STS0 flags These flags indicate OUT FIFO state. At the time of reading the receive data from the host PC, read these flags to confirm the OUT FIFO state.
Page 193 M30245 Group 2. USB function •TOGGLE_INIT bit This bit initializes data toggle sequence bit in bulk/interrupt transfer. With this bit being set to “1”, the PID of the next packet to be received from the host CPU becomes DATA0. When initialization of the data toggle sequence is requested from the host CPU at the time of configuration, etc., set TOGGLE_INIT bit and initialize PID to DATA0 before starting the OUT end- point communication.
Page 194 M30245 Group 2. USB function USB Endpoint x OUT Control and Status register (b8) (b15) Address When reset Symbol 02B6 , 02BE 0000 EPxOCS (x = 1 - 4) 02C6 , 02CE Bit Symbol Bit Name Function These two bits indicate the EPx OUT buffer status: OUT_BUF_STS0 flag OUTxCSR0 Bit1...
Page 195 M30245 Group 2. USB function USB endpoint x(x=1 to 4) OUT MAXP register This register indicates endpoint x(x=1~4) OUT maximum packet size. The default value is 0 byte. When the endpoint is initialized due to any reason such as that the request for setting the endpoint (SET_DESCRIPTOR, SET_CONFIGURATION, SET_INTERFACE, etc.) is received from the host CPU, change the endpoint x OUT maximum packet size value by writing in this register.
Page 196 M30245 Group 2. USB function USB endpoint x(x=1 to 4) OUT FIFO configuration register This register sets endpoint x(x=1~4) OUT FIFO. •BUF_NUM This bit sets the starting location of the endpoint x(x= 1~4) OUT FIFO per 64 bytes. For example, when OUT FIFO is allocated, starting at the 320th byte, the set value is “000101 ”.
Page 197 M30245 Group 2. USB function (2) Bulk Transfer: Endpoints 1 to 4 Receive Setting of Transfer Type When endpoints 1 to 4 OUT are used for bulk transfer, ISO bit of USB endpoint x(x=1 to 4) OUT control and status register is set to “0” for bulk transfer setting. Also, for initialization of toggle sequence bit in bulk transfer, set TOGGLE_INIT bit to “1”...
Page 198 M30245 Group 2. USB function When an error is detected in bulk OUT transfer, a response is not returned without ACK and NAK responses (Error checks such as CRC check and bit-justification, conforming to USB2.0 specifica- tion, are automatically performed. So the error does not have to be controlled by software). Fetch of Receive Data On receiving one packet data (Note 2), the received packet data (Note 2) from OUT FIFO is read.
Page 199 M30245 Group 2. USB function (3) Isochronous Transfer: Endpoints 1 to 4 Receive Setting of Transfer Type When endpoints 1 to 4 OUT are used for isochronous transfer, ISO bit of USB endpoint x(x=1 to 4) OUT control and status register is set to “1” for isochronous transfer setting. Receive Operation When there is a packet space in OUT FIFO, on receiving the OUT token from the host CPU, the data are received.
Page 200 M30245 Group 2. USB function (4) Interrupt Transfer: Endpoints 1 to 4 Receive Setting of Transfer Type When endpoints 1 to 4 OUT are used for interrupt transfer, ISO bit of USB endpoint x(x=1 to 4) OUT control and status register is set to “0” for interrupt transfer setting. Also, for initialization of toggle sequence bit in interrupt transfer, set TOGGLE_INIT bit to “1”...
Page 201 M30245 Group 2. USB function (6) USB Receive (Endpoints 1 to 4 OUT): Example The endpoints 1 to 4 OUT packet fetching routine (in continuous transfer disable) is shown in Figure 2.8.44. In addition to packet fetch process, error flag (OVER_RUN, FORCE_STALL, DATA_ERR) process is required for every transfer type.
Page 202: Usb Operation (Endpoints 1 To 4 Transmit)
M30245 Group 2. USB function 2.8.7 USB Operation (Endpoints 1 to 4 Transmit) Endpoints 1 to 4 can apply to the isochronous transfer, bulk transfer and interrupt transfer. The endpoints 1 to 4 respectively have their IN (transmit) FIFOs and OUT (receive) FIFOs. For using the endpoints 1 to 4 IN, enable each endpoint IN FIFO by USB endpoint enable register (ad- dress 028E ).
Page 203 M30245 Group 2. USB function (1) Related Registers USB ISO control register This register controls isochronous transfer of endpoints 1 to 4. This register setting is valid for all the isochronous transfer IN endpoints that are used simultaneously. •AUTO_FLUSH bit This bit controls transmit packet data destruction in isochronous transfer.
Page 204 M30245 Group 2. USB function •Artificial SOF enable bit This bit enables the artificial SOF function. With this bit being set to “1”, when a SOF packet from the host PC has been destroyed due to any cause and no valid SOF packet has been received even after 1ms from the preceding start of the frame, the artificial SOF receive is operated.
Page 205 M30245 Group 2. USB function USB endpoint x(x=1 to 4) IN control and status register •IN_BUF_STS1, IN_BUF_STS0 flags These flags indicate IN FIFO state. At the time of writing the data to be transmitted to the host PC in IN FIFO, read these flags to confirm the IN FIFO state.
Page 206 M30245 Group 2. USB function •CLR_UNDER_RUN bit The UNDER_RUN flag is cleared to “0” by setting “1” to this bit. •TOGGLE_INIT bit This bit initializes data toggle bit required in bulk and interrupt transfer. When initialization of the data toggle sequence is requested from the host CPU at the time of configu- ration, etc., set this bit to “1”...
Page 207 M30245 Group 2. USB function -AUTO_SET bit This bit controls setting of SET_IN_BUF_RDY bit. With this bit being set to “1”, when one data packet whose is equal to the maximum packet size (EPxIMP set value) has been written to IN FIFO in continuous transmit disable, or, when data equal to the buffer size (byte count set in the BUF_SIZ of the EPxIFC) have been written to IN FIFO in continuous transmit enable, the IN_BUF_STS1 and IN_BUF_STS0 flags are updated without SET_IN_BUF_RDY bit being set to “1”.
Page 208 M30245 Group 2. USB function USB endpoint x(x=1 to 4) IN MAXP register This register indicates endpoint x(x=1 to 4) IN maximum packet size. The default value is 0 byte. When the endpoint is initialized due to any reason such as that the request for setting the endpoint (SET_DESCRIPTOR, SET_CONFIGURATION, SET_INTERFACE, etc.) is received from the host CPU, change the endpoint x IN maximum packet size value by writing in this register.
Page 209 M30245 Group 2. USB function USB endpoint x(x=1 to 4) IN FIFO configuration register This register sets endpoint x(x=1 to 4) IN FIFO. •BUF_NUM This bit sets the starting location of the endpoint x(x= 1 to 4) IN FIFO per 64 bytes. For example, when IN FIFO is allocated, starting at the 320th byte, the set value is “000101 ”.
Page 210 M30245 Group 2. USB function (2) Bulk Transfer: Endpoints 1 to 4 Transmit Setting of Transfer Type When endpoints 1 to 4 IN are used for bulk transfer, both ISO bit and INTPT bit of USB endpoint x IN control and status register are set to “0” for bulk transfer setting. Also, for initialization of toggle sequence bit in bulk transfer, set TOGGLE_INIT bit to “1”...
Page 211 M30245 Group 2. USB function While the AUTO_SET is enabled (AUTO_SET bit is “1”), when one data packet whose is equal to the maximum packet size (EPxIMP set value) has been written to IN FIFO in continuous transmit dis- able, or, when data equal to the buffer size (byte count set in the BUF_SIZ of the EPxIFC) has been written to IN FIFO in continuous transmit enable, the IN_BUF_STS1 and IN_BUF_STS0 flags are updated without SET_IN_BUF_RDY bit being set to “1”.
Page 212 M30245 Group 2. USB function (3) Isochronous Transfer: Endpoints 1 to 4 Transmit Type of Transmit Transfer When endpoints 1 to 4 IN are used for isochronous transfer, ISO bit and INTPT bit of USB endpoint x IN control and status register are respectively set to “1” and to “0”, for isochronous transfer setting. Transmit Data Preparation The endpoint x IN packet data preparation procedure in the isochronous transfer is same as the bulk transfer.
Page 213 M30245 Group 2. USB function (4) Interrupt Transfer: Endpoints 1 to 4 Transmit Setting of Transfer Type Interrupt transfer setting has two kinds including the normal interrupt transfer and the rate feedback interrupt transfer. When endpoints 1 to 4 IN are used for the normal interrupt transfer, ISO bit and INTPT bit of USB endpoint x IN control and status register are respectively to “0”.
Page 214 M30245 Group 2. USB function Rate Feedback Interrupt Transfer: In real application, rate feedback interrupt transfer always has data to be transmitted to the host. Therefore, the device does not repond with NAK to the IN token from the host in this transfer. On receiving IN token from the host CPU, the IN FIFO data are always transmitted in the current data sequence bit regardless of the IN_BUF_STS0 and IN_BUF_STS1 values.
Page 215 M30245 Group 2. USB function (6) USB Transmit (Endpoints 1 to 4 IN): Example The endpoints 1 to 4 IN transmit packet prepare routine (continuous transfer disable) is shown in Figure 2.8.49. In addition to packet prepare process, error process by the UNDER_RUN flag is re- quired in isochronous transfer.
Page 216: Usb Operation (Interface With Dmac Transfer)
M30245 Group 2. USB function 2.8.8 USB Operation (Interface with DMAC Transfer) The M30245 group can select a USB (USB0/USB1/USB2/USB3) as the DMA request factor. The USB0 corresponds to DMA0, USB1 to DMA1, USB2 to DMA2, and USB3 to DMA3. The DMA request factor origin of USB0/USB1/USB2/USB3 is also set by setting any one of endpoints 1 to 4 IN/OUT factors to USB DMAx(x=0 to 3) request register .
Page 217 M30245 Group 2. USB function (2) DMA Request by Endpoint x OUT DMA Request Factors When endpoint 1 to 4 OUT FIFO write request select bit is set to the DMA request factor origin of USB0/USB1/USB2/USB3, the DMA request factor includes the following three kinds. On occurrence of an event when all the specified conditions have been satisfied for each factor, the DMA request of DMA0/DMA1/DMA2/DMA3 occurs.
Page 218 M30245 Group 2. USB function (3) DMA Request by Endpoint x IN DMA Request Factor When endpoint x(x=1 to 4) IN FIFO write request select bit is set to the DMA request factor origin of USB0/USB1/USB2/USB3, the DMA request factor includes the following three kinds. On occurrence of an event when all the specified conditions have been satisfied for each factor, the DMA request of DMA0/DMA1/DMA2/DMA3 occurs.
Page 219: Precautions For Usb
M30245 Group 2. USB function 2.8.9 Precautions for USB (1) USB Communication "In applications requiring high-reliability, we recommend providing the system with protective mea- sures such as USB function initialization by software or USB reset by the host to prevent USB com- munication from being terminated unexpectedly, for example due to external causes such as noise."...
Page 220 M30245 Group 2. USB function USBC5 Frequency synthesizer enable lock enable control ATTACH enable Connect to ATTACH or UV USB Clock PORT90_ ATTACH/ (48MHz) SECOND DETACH www.DataSheet4U.com USB FCU Transceiver enable USBC7 enable USBC7 : The value of resistance and capacitor, and the configuration will depened on the layout of printed circuit board.
Page 221 M30245 Group 2. USB function (3) Register, Bit •When the USB reset interrupt request occurs, all the USB internal registers become reset state. To resume communication, each endpoint needs to be initialized. •All the USB related registers (16-bit registers) except USB endpoint x(x=0 to 4) IN FIFO data register (EPxI), USB endpoint x(x=0 to 4) OUT FIFO data register (EPxO), USB control register (USBC), and USB attach/detach register (USBAD) are available for word access and byte access.
Page 222: A/D Converter
M30245 Group 2. A/D Converter 2.9 A/D Converter 2.9.1 Overview The A/D converter used in the M30245 group operates on a successive conversion basis. The following is an overview of the A/D converter. (1) Mode The A/D converter operates in one of five modes: (a) One-shot mode www.DataSheet4U.com Carries out A/D conversion on input level of one specified pin only once.
Page 223 M30245 Group 2. A/D Converter (4) Functions selection (a) Sample & Hold function Sample & Hold function samples input voltage when A/D conversion starts and carries out A/D con- version on the voltage sampled. When A/D conversion starts, input voltage is sampled for 3 cycles of the operation clock.
Page 224 M30245 Group 2. A/D Converter 004B AD conversion interrupt control register (ADIC) 03C0 AD register 0 (AD0) 03C1 03C2 AD register 1 (AD1) 03C3 03C4 AD register 2 (AD2) 03C5 www.DataSheet4U.com 03C6 AD register 3 (AD3) 03C7 03C8 AD register 4 (AD4) 03C9 03CA AD register 5 (AD5)
Page 225 M30245 Group 2. A/D Converter AD control register 0 (Note 1) b5 b4 b3 b2 Symbol Address When reset ADCON0 03D6 Bit Name Function Bit Symbol b2 b1 b0 0 0 0 : AN0 0 0 1 : AN1 0 1 0 : AN2 Analog input pin select bit 0 1 1 : AN3 1 0 0 : AN4...
Page 226 M30245 Group 2. A/D Converter AD control register 2 (Note) b5 b4 b3 b2 Symbol Address When reset ADCON2 03D4 X00X0XX0 Bit Name Function Bit Symbol 0 : Without sample and hold A/D conversion method 1 : With sample and hold select bit Nothing is assigned.
Page 227: Operation Of A/D Converter (One-Shot Mode)
M30245 Group 2. A/D Converter 2.9.2 Operation of A/D converter (one-shot mode) In one-shot mode, choose functions from those listed in Table 2.9.2. Operations of the circled items are described below. Figure 2.9.4 shows the operation timing, and Figure 2.9.5 shows the set-up procedure. Table 2.9.2.
Page 228 M30245 Group 2. A/D Converter S e l e c t i n g S a m p l e a n d h o l d AD control register 2 [Address 03D4 ADCON2 A / D c o n v e r s i o n m e t h o d s e l e c t b i t 1 : W i t h s a m p l e a n d h o l d M u s t a l w a y s b e s e t t o “...
Page 229: Operation Of A/D Converter (In One-Shot Mode, An External Trigger Selected)
M30245 Group 2. A/D Converter 2.9.3 Operation of A/D Converter (in one-shot mode, an external trigger selected) In one-shot mode, choose functions from those listed in Table 2.9.3. Operations of the circled items are described below. Figure 2.9.6 shows timing chart, and Figure 2.9.7 shows the set-up procedure. Table 2.9.3.
Page 230 M30245 Group 2. A/D Converter S e l e c t i n g S a m p l e a n d h o l d A D c o n t r o l r e g i s t e r 2 [ A d d r e s s 0 3 D 4 A D C O N 2 A / D c o n v e r s i o n m e t h o d s e l e c t b i t 1 : W i t h s a m p l e a n d h o l d...
Page 231: Operation Of A/D Converter (In Repeat Mode)
M30245 Group 2. A/D Converter 2.9.4 Operation of A/D Converter (in repeat mode) In repeat mode, choose functions from those listed in Table 2.9.4. Operations of the circled items are described below. Figure 2.9.8 shows timing chart, and Figure 2.9.9 shows the set-up procedure. Table 2.9.4.
Page 232 M30245 Group 2. A/D Converter S e l e c t i n g S a m p l e a n d h o l d A D c o n t r o l r e g i s t e r 2 [ A d d r e s s 0 3 D 4 A D C O N 2 A / D c o n v e r s i o n m e t h o d s e l e c t b i t 1 : W i t h s a m p l e a n d h o l d...
Page 233: Operation Of A/D Converter (In Single Sweep Mode)
M30245 Group 2. A/D Converter 2.9.5 Operation of A/D Converter (in single sweep mode) In single sweep mode, choose functions from those listed in Table 2.9.5. Operations of the circled items are described below. Figure 2.9.10 shows timing chart, and Figure 2.9.11 shows the set-up procedure. Table 2.9.5.
Page 234 M30245 Group 2. A/D Converter S e l e c t i n g S a m p l e a n d h o l d A D c o n t r o l r e g i s t e r 2 [ A d d r e s s 0 3 D 4 A D C O N 2 A / D c o n v e r s i o n m e t h o d s e l e c t b i t 1 : W i t h s a m p l e a n d h o l d...
Page 235: Operation Of A/D Converter (In Repeat Sweep Mode 0)
M30245 Group 2. A/D Converter 2.9.6 Operation of A/D Converter (in repeat sweep mode 0) In repeat sweep 0 mode, choose functions from those listed in Table 2.9.6. Operations of the circled items are described below. Figure 2.9.12 shows timing chart, and Figure 2.9.13 shows the set-up procedure. Table 2.9.6.
Page 236 M30245 Group 2. A/D Converter S e l e c t i n g S a m p l e a n d h o l d A D c o n t r o l r e g i s t e r 2 [ A d d r e s s 0 3 D 4 A D C O N 2 A / D c o n v e r s i o n m e t h o d s e l e c t b i t 1 : W i t h s a m p l e a n d h o l d...
Page 237: Operation Of A/D Converter (In Repeat Sweep Mode 1)
M30245 Group 2. A/D Converter 2.9.7 Operation of A/D Converter (in repeat sweep mode 1) In repeat sweep 1 mode, choose functions from those listed in Table 2.9.7. Operations of the circled items are described below. Figure 2.9.14 shows ANi pin's sweep sequence, Figure 2.9.15 shows timing chart, and Figure 2.9.16 shows the set-up procedure.
Page 238 M30245 Group 2. A/D Converter S e l e c t i n g S a m p l e a n d h o l d A D c o n t r o l r e g i s t e r 2 [ A d d r e s s 0 3 D 4 A D C O N 2 A / D c o n v e r s i o n m e t h o d s e l e c t b i t 1 : W i t h s a m p l e a n d h o l d...
Page 239: Precautions For A/D Converter
M30245 Group 2. A/D Converter 2.9.8 Precautions for A/D Converter (1) Write to each bit (except bit 6) of AD control register 0, to each bit of AD control register 1, and to bit 0 of AD control register 2 when A/D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from 0 to 1, start A/D conversion after an elapse of 1 µs or longer.
Page 240: Method Of A/D Conversion (10-Bit Mode)
M30245 Group 2. A/D Converter 2.9.9 Method of A/D Conversion (10-bit mode) (1) The A/D converter compares the reference voltage (Vref) generated internally based on the contents of the successive comparison register with the analog input voltage (V ) input from the analog input pin.
Page 241 M30245 Group 2. A/D Converter Table 2.9.9. Variation of the successive comparison register and Vref while A/D conversion is in progress (10-bit mode) Successive approximation register change 0 0 0 0 0 0 0 0 0 A/D converter stopped 0 0 0 0 0 0 0 0 0 1st comparison –...
Page 242: Method Of A/D Conversion (8-Bit Mode)
M30245 Group 2. A/D Converter 2.9.10 Method of A/D Conversion (8-bit mode) (1) In 8-bit mode, 8 higher-order bits of the 10-bit successive comparison register becomes A/D conversion result. Hence, if compared to a result obtained by using an 8-bit A/D converter, the voltage compared is different by 3 V /2048 (see what are underscored in Table 2.9.10), and differences in stepping points of output codes occur as shown in Figure 2.9.19.
Page 243 M30245 Group 2. A/D Converter Table 2.9.11. Variation of the successive comparison register and Vref while A/D conversion is in progress (8-bit mode) change Successive approximation register 0 0 0 0 0 0 0 0 0 A/D converter stopped 0 0 0 0 0 0 0 0 0 1st comparison –...
Page 244: Absolute Accuracy And Differential Non-Linearity Error
M30245 Group 2. A/D Converter 2.9.11 Absolute Accuracy and Differential Non-Linearity Error • Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and actual A/D conversion result. When measuring absolute accuracy, the voltage at the middle point of the width of analog input voltage (1-LSB width), that can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as an ana- log input voltage.
Page 245 M30245 Group 2. A/D Converter • Differential non-linearity error Differential non-linearity error refers to the difference between 1-LSB width based on the theoretical A/ D conversion characteristics (an analog input width that can meet the expectation of outputting an equal code) and an actually measured 1-LSB width (analog input voltage width that outputs an equal code).
Page 246: Internal Equivalent Circuit Of Analog Input
M30245 Group 2. A/D Converter 2.9.12 Internal Equivalent Circuit of Analog Input Figure 2.9.23 shows the internal equivalent circuit of analog input. V c c V c c V s s www.DataSheet4U.com AVcc P a r a s i t i c O N r e s i s t o r Ω...
Page 247: Sensor's Output Impedance Under A/D Conversion (Reference Value)
M30245 Group 2. A/D Converter 2.9.13 Sensor’s Output Impedance under A/D Conversion (reference value) To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 2.9.23 has to be completed within a specified period of time. With T as the specified time, time T is the time that switches SW2 and SW3 are connected to O in Figure 2.9.23.
Page 248 M30245 Group 2. A/D Converter Table 2.9.12. Relation between output impedance and precision (error) of A/D converter (10-bit mode) Reference value f(Xin) Cycle Sampling time Resolution (MHz) (pF) (LSB) (µs) (µs) (k ) (k ) (3 x cycle, Sample & hold bit is enabled) www.DataSheet4U.com...
Page 249: Dmac Usage
M30245 Group 2. DMAC 2.10 DMAC Usage 2.10.1 Overview of the DMAC usage DMAC transfers one data item held in the source address to the destination address every time a transfer request is generated. The following is an overview of the DMAC usage. (1) Source address and destination address Both the register which indicates a source and the register which indicates a destination comprise of 24 bits, so that each can cover a 1M bytes space.
Page 250 M30245 Group 2. DMAC (6) Reading to a register The reload register can be read to, as in normal conditions. (7) Switching function (a) Switching between one-shot transfer and repeated transfer 'One-shot transfer' refers to a mode in which DMA is disabled after the transfer counter underflows. 'Repeated transfer' refers to a mode in which a reload is carried out after the transfer counter under- flows.
Page 251 M30245 Group 2. DMAC DMA0 request cause select register (Note 1) Symbol Address When reset DM0SL 03B8 Bit Symbol Bit Name Function (Note 2) b4 b3 b2 b1 b0 0 0 0 0 0 : DMA Disabled DSEL0 DMA request 0 0 0 0 1 : INT0 (falling edge) 0 0 0 1 0 : INT0 (two edges) cause select bits...
Page 252 M30245 Group 2. DMAC DMA2 request cause select register (Note 1) Symbol Address When reset DM2SL 03B0 Bit Name Function (Note 2) Bit Symbol b4 b3 b2 b1 b0 0 0 0 0 0 : DMA Disabled DSEL0 DMA request 0 0 0 0 1 : INT2 (falling edge) cause select bits 0 0 0 1 0 : INT2 (two edges)
Page 253 M30245 Group 2. DMAC DMAi control register Address Symbol When reset 002C , 003C DMiCON (i=0-3) 00000X00 018C , 019C Bit Symbol Bit Name Function 0 : 16 bits Transfer unit select bit DMBIT 1 : 8 bits 0 : Single transfer Repeat transfer mode select bit DMASL 1 : Repeat transfer...
Page 254: Operation Of Dmac (One-Shot Transfer Mode)
M30245 Group 2. DMAC 2.10.2 Operation of DMAC (one-shot transfer mode) In one-shot transfer mode, choose functions from the items shown in Table 2.10.1. Operations of the circled items are described below. Figure 2.10.5 shows an example of operation and Figure 2.10.6 shows the set-up procedure.
Page 255 M30245 Group 2. DMAC Setting DMAi request cause select register DMAi request cause select register [Address 03B8 , 03BA , 03B0 , 03B2 DMiSL(i = 0 to 3) DMA request cause select bit Software trigger is always enabled Software DMA request bit Set to “0”...
Page 256: Operation Of Dmac (Repeated Transfer Mode)
M30245 Group 2. DMAC 2.10.3 Operation of DMAC (repeated transfer mode) In repeat transfer mode, choose functions from the items shown in Table 2.10.2. Operations of the circled items are described below. Figure 2.10.7 shows an example of operation and Figure 2.10.8 shows the set-up procedure.
Page 257 M30245 Group 2. DMAC Setting DMAi request cause select register DMAi request cause select register [Address 03B8 , 03BA , 03B0 , 03B2 DMiSL(i = 0 to 3) DMA request cause select bit Software trigger is always enabled Software DMA request bit Set to “0”...
Page 258: Crc Calculation Circuit
M30245 Group 2. CRC Calculation Circuit 2.11 CRC Calculation Circuit 2.11.1 Overview Cyclic Redundancy Check (CRC) is a method that compares CRC code formed from transmission data by use of a polynomial generation with CRC check data so as to detect errors in transmission data. Using the CRC calculation circuit allows generation of CRC code.
Page 259 M30245 Group 2. CRC Calculation Circuit CRC data register (b15) (b8) Symbol Address When reset CRCD 03BC to 03BD Indeterminate Function Values that can be set CRC calculation result output 0000 to FFFF www.DataSheet4U.com CRC input register Symbol Address When reset CRCIN 03BE Indeterminate...
Page 260: Operation Of Crc Calculation Circuit
M30245 Group 2. CRC Calculation Circuit 2.11.2 Operation of CRC Calculation Circuit The following describes the operation of the CRC calculation. Figure 2.11.3 shows an example of calcu- lation using the CRC-CCITT. Operation (1) Select CRC-CCITT or CRC-16, and LSB first or MSB first by bit 0 and bit 5 of CRC mode register.
Page 261: Sfr Access Snoop Function
M30245 Group 2. CRC Calculation Circuit 2.11.3 SFR Access Snoop Function The CRC calculation circuit includes the ability to snoop write/read to/from the SFR addresses and to execute CRC automatic calculation (SFR access snoop function). In order to execute CRC calculation for data which have been written/read to/from the SFR, setting data to CRC input register again is not re- quired.
Page 262: Watchdog Timer
M30245 Group 2. Watchdog Timer 2.12 Watchdog Timer 2.12.1 Overview The watchdog timer can detect a runaway program using its 15-bit timer prescaler. The following is an overview of the watchdog timer. (1) Watchdog timer start procedure When reset, the watchdog timer is in stopped state. Writing to the watchdog timer start register initializes the watchdog timer to 7FFF and causes it to start performing a down count.
Page 263 M30245 Group 2. Watchdog Timer (5) Watchdog timer cycle The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the prescaler selected. Table 2.12.1 shows the watchdog timer cycle. Table 2.12.1. The watchdog timer cycle (f(X ) = 16MH CM07 CM06...
Page 264 M30245 Group 2. Watchdog Timer (6) Registers related to the watchdog timer Figure 2.12.1 shows the memory map of watchdog timer-related registers, and Figure 2.12.2 shows watchdog timer-related registers. 000E Watchdog timer start register (WDTS) 000F Watchdog timer control register (WDC) 0010 www.DataSheet4U.com Figure 2.12.1.
Page 265: Operation Of Watchdog Timer (Watchdog Timer Interrupt)
M30245 Group 2. Watchdog Timer 2.12.2 Operation of Watchdog Timer (Watchdog timer interrupt) The following is an operation of the watchdog timer using watchdog timer interrupt. Figure 2.12.3 shows the operation timing, and Figure 2.12.4 shows the set-up procedure. Operation (1) Writing to the watchdog timer start register initializes the watchdog timer to 7FFF causes it to start a down count.
Page 266 M30245 Group 2. Watchdog Timer Setting watchdog timer control register Watchdog timer control register [Address 000F Reserved bit Must always be “0” Prescaler select bit 0 : Divided by 16 1 : Divided by 128 www.DataSheet4U.com Setting watchdog timer start register Watchdog timer start register [Address 000E WDTS The watchdog timer is initialized and starts counting with a write instruction to...
Page 267: Address Match Interrupt Usage
M30245 Group 2. Address Match Interrupt 2.13 Address Match Interrupt Usage 2.13.1 Overview of the address match interrupt usage The address match interrupt is used for correcting a ROM or for a simplified debugging-purpose monitor. When the external bus is used for 8 bits, the address match interrupt is not used to the external areas. The following is an overview of the address match interrupt usage.
Page 268 M30245 Group 2. Address Match Interrupt (5) Registers related to the address match interrupt Figure 2.13.2 shows the memory map of address match interrupt-related registers, and Figure 2.13.3 shows address match interrupt-related registers. 0009 Address match interrupt enable register (AIER) 0010 0011 Address match interrupt register 0 (RMAD0)
Page 269: Operation Of Address Match Interrupt
M30245 Group 2. Address Match Interrupt 2.13.2 Operation of Address Match Interrupt The following is an operation of address match interrupt. Figure 2.13.4 shows the set-up procedure of address match interrupt, and Figure 2.13.5 shows the overview of the address match interrupt handling routine.
Page 270 M30245 Group 2. Address Match Interrupt Address match interrupt routine [1] Storing registers [2] Determining the interrupt address Address match 0? Address match 1? Address match 0 program www.DataSheet4U.com Address match 1 program [3] Rewriting the stack Restoring registers REIT Handling an error Explanation: [1] Storing the contents of the registers holding the main program status to be kept.
Page 271: Key-Input Interrupt Usage
M30245 Group 2. Key-Input Interrupt 2.14 Key-Input Interrupt Usage 2.14.1 Overview of the key-input interrupt usage Key-input interrupt can be generated by a falling edge, rising edge or both edges input to any Port 10 pin. It can also be used as a Key-on wake up function for canceling the wait mode or stop mode. It is possible to select the edge of the Key input interrupt for P10 with bits 0 and 1 of key input mode register.
Page 272 M30245 Group 2. Key-Input Interrupt Key input interrupt control register (Note 1) Symbol Address When reset KUPIC 0041 XXXXX000 Bit symbol Bit name Function Interrupt priority level ILVL0 b2 b1 b0 select bit 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 ILVL1...
Page 273 M30245 Group 2. Key-Input Interrupt Key-input mode register Symbol Address When reset KUPM 03F9 Bit Symbol Bit Name Function b1 b0 KIS0 P10 Key-input edge select 0 0 0 : Falling edge 0 1 : Rising edges 1 0 : Two edge www.DataSheet4U.com KIS1 P10 Key-input edge select 1...
Page 274: Operation Of Key-Input Interrupt
M30245 Group 2. Key-Input Interrupt 2.14.2 Operation of Key-Input Interrupt The following is an operation of key-input interrupt. Figure 2.14.4 shows an example of a circuit that uses the key-input interrupt, Figure 2.14.5 shows an example of operation of key-input interrupt, and Figure 2.14.6 shows the setting procedure of key-input interrupt.
Page 275 M30245 Group 2. Key-Input Interrupt Setting key input mode register Key input mode register [Address 03F9 KUPM P10 Key-input edge select bit 0 P10 Key-input edge select bit 1 b1 b0 0 0 : Falling edge and P10 Key-input enable bit 1 : Enabled w w w .
Page 276: Multiple Interrupts Usage
M30245 Group 2. Multiple Interrupts 2.15 Multiple interrupts Usage 2.15.1 Overview of the Multiple interrupts usage The following is an overview of the multiple interrupts usage. (1) Interrupt control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted.
Page 277 M30245 Group 2. Multiple Interrupts Interrupt control register (Note 1) Symbol Address When reset Symbol Address When reset KUPIC 0041 XXXXX000 S1TIC 0051 XXXXX000 S2RIC 0042 XXXXX000 DM3IC 0052 XXXXX000 S13BCNIC 0043 XXXXX000 S0TIC 0053 XXXXX000 TA1IC 0045 XXXXX000 TA0IC 0054 XXXXX000 EP0IC...
Page 278 M30245 Group 2. Multiple Interrupts (2) Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0”...
Page 279 M30245 Group 2. Multiple Interrupts The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 2.15.1. Settings of interrupt priority levels Table 2.15.2.
Page 280 M30245 Group 2. Multiple Interrupts (6) Interrupt resolution circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure 2.15.5 shows the circuit that judges the interrupt priority level. Priority level of each interrupt Level 0 (initial value) High INT2...
Page 281: Multiple Interrupts Operation
M30245 Group 2. Multiple Interrupts 2.15.2 Multiple Interrupts Operation The state when control branched to an interrupt routine is described below: · The interrupt enable flag (I flag) is set to “0” (the interrupt is disabled). · The interrupt request bit of the accepted interrupt is set to “0”. ·...
Page 282 M30245 Group 2. Multiple Interrupts Interrupt request Nesting generated Main routine Reset Time I = 0 IPL = 0 Interrupt 1 I = 1 Interrupt priority level = 3 Interrupt 1 www.DataSheet4U.com I = 0 IPL = 3 Multiple interrupts Interrupt 2 I = 1 Interrupt priority level = 5...
Page 283: Www.datasheet4U.com 2.16 Power Control Usage
M30245 Group 2. Power Control 2.16 Power Control Usage 2.16.1 Overview of the power control usage ‘Power Control’ refers to the reduction of CPU power consumption by stopping the CPU and oscillators, or decreasing the operation clock. The following is a description of the three available power control modes: (1) Modes Power control is available in three modes.
Page 284 M30245 Group 2. Power Control Transition of stop mode, wait mode Reset All oscillators stopped CPU operation stopped WAIT CM10 = “1” instruction Medium-speed mode Stop mode Wait mode (divided-by-8 mode) Interrupt Interrupt Interrupt All oscillators stopped CPU operation stopped WAIT instruction High-speed/medium-...
Page 285 M30245 Group 2. Power Control (3) Returning from stop mode The stop mode can be canceled by hardware reset, or by generating an interrupt request. If an inter- rupt is to be used to cancel stop mode, that interrupt must first have been enabled and the priority level of the interrupt not to be used for clearing must be set to level 0 before changing to stop mode.
Page 286 M30245 Group 2. Power Control Table 2.16.1. Interrupts available for clearing stop mode and wait mode W a i t m o d e I n t e r r u p t f o r c l e a r i n g S t o p m o d e C M 0 2 = 1 ( N o t e 6 ) , C M 0 2 = 0...
Page 287 M30245 Group 2. Power Control (5) Sequence of returning from stop mode Sequence of returning from stop mode is oscillation start-up time and interrupt sequence. When interrupt is generated in stop mode, CM10 becomes “0” and clearing stop mode. Starting oscillation and supplying BCLK execute the interrupt sequence as follow: In the interrupt sequence, the processor carries out the following in sequence given: (a) CPU gets the interrupt information (the interrupt number and interrupt request level) by read- ing address 00000...
Page 288 M30245 Group 2. Power Control System clock control register 0 (Note 1) Symbol Address When reset 0006 Bit Symbol Bit Name Function Always set to “0” Reserved bit WAIT peripheral function 0 : Do not stop in wait mode CM02 clock stop bit w w w .
Page 289: Stop Mode Set-Up
M30245 Group 2. Power Control 2.16.2 Stop Mode Set-Up Settings and operation for entering stop mode are described here. Operation (1) Enables the interrupt used for returning from stop mode. (2) Sets the interrupt enable flag (I flag) to “1”. (3) Clearing the protection and setting all clock stop control bit to “1”...
Page 290: Wait Mode Set-Up
M30245 Group 2. Power Control 2.16.3 Wait Mode Set-Up Settings and operation for entering wait mode are described here. Operation (1) Enables the interrupt used for returning from wait mode. (2) Sets the interrupt enable flag (I flag) to “1”. (3) Clears the protection and changes the content of the system clock control register.
Page 291: Precautions In Power Control
M30245 Group 2. Power Control 2.16.4 Precautions in Power Control ______ (1) The processor does not switch to stop mode when the NMI pin is at “L” level. ____________ (2) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized.
Page 292 M30245 Group 2. Power Control (5) Before the count source for BCLK can be changed from X to X or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscilla- tion to stabilize before switching over the clock.
Page 293: Programmable I/O Ports Usage
M30245 Group 2. Programmable I/O Ports 2.17 Programmable I/O Ports Usage 2.17.1 Overview of the programmable I/O ports usage Eighty-one programmable I/O ports and one input-only port are available. I/O pins also serve as I/O pins for built-in peripheral functions. Each port has a direction register that defines the I/O direction and also has a port register for I/O data.
Page 294 M30245 Group 2. Programmable I/O Ports (6) I/O functions of built-in peripheral devices Table 2.17.1 shows relation between ports and I/O functions of built-in peripheral devices. Table 2.17.1. Relation between ports and I/O functions of built-in peripheral devices Port Internal peripheral device I/O pins I/O pins/Serial sound interface, I C and SPI communication pins for UART0 and UART1 Timer A0 to A3 I/O pins / I/O pins or I...
Page 295 M30245 Group 2. Programmable I/O Ports (b) Memory expansion mode, microprocessor mode Table 2.17.3. Examples of working on unused pins in memory expansion mode or microprocessor mode P i n n a m e C o n n e c t i o n P o r t s P 6 t o P 1 0 ( e x c l u d i n g P 8 ) A f t e r s e t t i n g f o r i n p u t m o d e , c o n n e c t e v e r y p i n t o V o r V...
Page 296 M30245 Group 2. Programmable I/O Ports (8) Registers related to the programmable I/O ports Figure 2.17.1 shows the memory map of programmable I/O ports-related registers, and Figures 2.17.2 to 2.17.5 show programmable I/O ports-related registers. Port P0 (P0) 03E0 Port P1 (P1) 03E1 Port P0 direction register (PD0) www.DataSheet4U.com...
Page 297 M30245 Group 2. Programmable I/O Ports Port 7 drive capacity register Symbol Address When reset P7DR 03FA Bit symbol Bit name Function P7DR0 LED drive capacity The N-channel high drive capacity is activated for the corresponding P7DR1 LED drive capacity bit.
Page 298 M30245 Group 2. Programmable I/O Ports Port Pi direction register (Note 1) Symbol Address When reset PDi (i = 0 to 7, 10) 03E2 , 03E3 , 03E6 , 03E7 , 03EA 03EB , 03EE , 03EF , 03F6 Bit symbol Bit name Function PDi_0...
Page 299 M30245 Group 2. Programmable I/O Ports Port Pi register (Note 2) Symbol Address When reset Pi (i = 0 to 7, 10) 03E0 , 03E1 , 03E4 , 03E5 , 03E8 Indeterminate 03E9 , 03EC , 03ED , 03F4 Indeterminate Bit symbol Bit name Function...
Page 300 M30245 Group 2. Programmable I/O Ports P u l l - u p c o n t r o l r e g i s t e r 0 ( N o t e ) S y m b o l A d d r e s s W h e n r e s e t P U R 0...
Page 301 www.DataSheet4U.com THIS PAGE IS BLANK FOR REASONS OF LAYOUT.
Page 302: Applications
www.DataSheet4U.com Chapter 3 Examples of Peripheral Functions Applications...
Page 303 M30245 Group 3. Applications This chapter presents applications in which peripheral functions built in the M30245 are used. They are shown here as examples. In practical use, make suitable changes and perform sufficient evaluation. For basic use, see Chapter 2 Peripheral Functions Usage. www.DataSheet4U.com Rev.2.00 Oct 16, 2006 page 294 of 354...
Page 304: Long-Period Timers
M30245 Group 3. Timer A Applications 3.1 Long-Period Timers Overview In this process, Timer A0 and Timer A1 are connected to make a 16-bit timer with a 16-bit prescaler. Figure 3.1.1 shows the operation timing, Figure 3.1.2 shows the connection dia- gram, and Figures 3.1.3 and 3.1.4 show the set-up procedure.
Page 305 M30245 Group 3. Timer A Applications Used for timer mode Timer A0 Timer A0 interrupt request bit Timer A1 Timer A1 interrupt request bit Used for event counter mode Figure 3.1.2. Connection diagram of long-period timers www.DataSheet4U.com Rev.2.00 Oct 16, 2006 page 296 of 354 REJ09B0340-0200...
Page 306 M30245 Group 3. Timer A Applications Setting timer A0 Selecting timer mode and functions Timer A0 mode register [Address 0396 TA0MR Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA0 pin is a normal port pin) www.DataSheet4U.com Gate function select bit b4 b3...
Page 307 M30245 Group 3. Timer A Applications Continued from the previous page Setting trigger select register Trigger select register [Address 0383 TRGSR www.DataSheet4U.com Timer A1 event/trigger select bit b1 b0 1 0 : TA0 overflow is selected Setting counter value (b15) (b8) Timer A1 register [Address 0389 , 0388...
Page 308: Variable-Period Variable-Duty Pwm Output
M30245 Group 3. Timer A Applications 3.2 Variable-Period Variable-Duty PWM Output Overview In this process, Timer A0 and A1 are used to generate variable-period, variable-duty PWM out- put. Figure 3.2.1 shows the operation timing, Figure 3.2.2 shows the connection diagram, and Figures 3.2.3 and 3.2.4 show the set-up procedure.
Page 309 M30245 Group 3. Timer A Applications l = reload register content (1) Timer A0 start count FFFF (2) Timer A0 underflow 0000 www.DataSheet4U.com Time n = reload register content (3) Timer A1 start count FFFF (4) Timer A1 stop count 0001 Set to “1”...
Page 310 M30245 Group 3. Timer A Applications Setting timer A0 Selecting timer mode and functions Timer A0 mode register [Address 0396 TA0MR Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA0 pin is a normal port pin) Gate function select bit www.DataSheet4U.com b4 b3...
Page 311 M30245 Group 3. Timer A Applications Continued from the previous page Setting trigger select register Trigger select register [Address 0383 TRGSR Timer A1 event/trigger select bit www.DataSheet4U.com b1 b0 1 0 : TA0 overflow is selected Setting one-shot timer's time (b15) (b8) Timer A1 register [Address 0389...
Page 312: Buzzer Output
M30245 Group 3. Timer A Applications 3.3 Buzzer Output Overview The timer mode is used to make the buzzer ring. Figure 3.3.1 shows the operation timing, and Figure 3.3.2 shows the set-up procedure. Use the following peripheral function: • The pulse-outputting function in timer mode of timer A. Specifications (1) Sound a 2-kHz buzz beep by use of timer A0.
Page 313 M30245 Group 3. Timer A Applications Initialization of timer A0 Timer A0 mode register TA0MR [Address 0396 Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA0out pin is a normal port pin) Gate function select bit b4 b3 www.DataSheet4U.com 0 0 : Gate function not available (TA0in pin is a normal port pin)
Page 314: Solution For External Interrupt Pins Shortage
M30245 Group 3. Timer A Applications 3.4 Solution for External Interrupt Pins Shortage Overview The following are solution for external interrupt pins shortage. Figure 3.4.1 shows the set-up procedure. Use the following peripheral function: • Event counter mode of timer A Specifications (1) Inputting a falling edge to the TA0 pin generates a timer A0 interrupt.
Page 315 M30245 Group 3. Timer A Applications Initialization of timer A0 Timer A0 mode register TA0MR [Address 0396 Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TA0out pin is a normal port pin) Count polarity select bit 0 : Counts external signal's falling edge www.DataSheet4U.com...
Page 316: Memory To Memory Dma Transfer
M30245 Group 3. DMAC Applications 3.5 Memory to Memory DMA Transfer Overview The following are steps for changing both source address and destination address to transfer data from memory to another. The DMA transfer utilizes the workings that assign a higher priority to the DMA0 transfer if transfer requests simultaneously occur in two DMA channels.
Page 317 M30245 Group 3. DMAC Applications Source area Destination area F6000 F6000 content 00400 F6001 content F6002 content www.DataSheet4U.com Temporary RAM 0047F F607F F607F content Data transfer by DMA0 Data transfer by DMA1 Figure 3.5.2. Block diagram of memory to memory DMA transfer Rev.2.00 Oct 16, 2006 page 308 of 354 REJ09B0340-0200...
Page 318 M30245 Group 3. DMAC Applications Initialization of DMA0 DMA0 control register DMA0 request cause select register DM0SL [Address 03B8 DM0CON [Address 002C Transfer unit bit select bit DMA request cause select bit 1 : 8 bits b4 b3 b2 b1 b0 0 0 1 0 0 : Timer A0 Repeat transfer mode select bit 1 : Repeat transfer...
Page 319 M30245 Group 3. DMAC Applications Continued from the previous page Initialization of timer A0 Timer A0 mode register TA0MR [Address 0396 Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA0 pin is a normal port pin) www.DataSheet4U.com Gate function select bit b4 b3...
Page 320: Buzzer Output
M30245 Group 3. CRC Snoop Function Applications 3.6 CRC Calculation SFR Access Snoop Function in Clock Synchronous Serial Data Transmit The M30245 group, by use of DMAC, transfers data from the internal RAM to the UART1 and the Overview result is transferred to the UART1 by use of SFR access snoop function. The block diagram is shown in Figure 3.6.1 and the setting routine is shown in Figure 3.6.2 to Figure 3.6.4.
Page 321 M30245 Group 3. CRC Snoop Function Applications M30245 Source area Contents of 1st byte 00400 transmission data CRC input register Contents of 2nd byte transmission data Contents of 3rd byte transmission data www.DataSheet4U.com Snoop the address of UART1 transmit buffer register UART1 transmit Transmission Contents of 512th byte...
Page 322 M30245 Group 3. CRC Snoop Function Applications Initialization of UART1 (See “2.3.2 Operation of Serial I/O (transmission in clock synchronous serial I/O mode” for detail.) Enable UART1 transmit UART1 transmit / receive control register 1 U1C1 [Address 036D Transmit enable bit 1 : Transmit enable www.DataSheet4U.com Disable DMA0...
Page 323 M30245 Group 3. CRC Snoop Function Applications Continued from the previous page Enable DMA0 DMA0 control register DM0CON [Address 002C DMA request bit 0 : DMA not requested DMA enable bit 1 : Enabled www.DataSheet4U.com Clear CRC data register b8 b7 CRC data register CRCD [Address 03BD , 03BC...
Page 324 M30245 Group 3. CRC Snoop Function Applications Continued from the previous page The DMA transfer request from the 2nd byte on is occurred when DMA enable bit = “1” and the UART1 is transmit request state. Transfer of the data to www.DataSheet4U.com CRC input register by the SFR snoop function.
Page 325: Transfer From Usb Fifo To Serial Sound Interface
M30245 Group 3. USB Applications 3.7 Transfer from USB FIFO to Serial Sound Interface Overview The M30245 group, by use of DMAC, transfers data from the USB endpoint 1 OUT FIFO to SS interface 1 transmit buffer register and fetches one packet data. The block diagram is shown in Figure 3.7.1 and the setting routine is shown in Figure 3.7.2 to Figure 3.7.4.
Page 326 M30245 Group 3. USB Applications M30245 DMA0 transfer USB endpoint 1 USB transfer Serial Sound Interface 1 Host CPU OUT FIFO transmit buffer register www.DataSheet4U.com Figure 3.7.1. Block diagram of DMA transfer from USB FIFO to serial sound interface Rev.2.00 Oct 16, 2006 page 317 of 354 REJ09B0340-0200...
Page 327 M30245 Group 3. USB Applications Initialization USB function unit (See “2.8 USB function” for detail) Setting USB-related registers Enable USB endpoint 1 OUT (b15) (b8) USB endpoint enable register 0 0 0 0 0 0 0 0 USBEPEN [Address 028E EP1 OUT enable bit www.DataSheet4U.com 1 : Enabled...
Page 328 M30245 Group 3. USB Applications Continued from the previous page Setting DMA0 control register DMA0 control register DM0CON [Address 002C Transfer unit select bit 0 : 16 bits Repeat transfer mode select bit 0 : Single transfer DMA request bit www.DataSheet4U.com 0 : DMA not requested DMA enable bit...
Page 329 M30245 Group 3. USB Applications Continued from the previous page The DMA request of the serial sound interface 1 transmit is occurred when DMA enable bit = “1” and the OUT_BUF_STS1 flag of endpoint 1 = “1”. DMA0 transfer of the 1st word www.DataSheet4U.com DMA request from the 2nd byte on is occurred when DMA enable bit = “1”...
Page 330: Controlling Power Using Stop Mode
M30245 Group 3. Controlling Power Applications 3.8 Controlling Power Using Stop Mode Overview The following are steps for controlling power using stop mode. Figure 3.8.1 shows the operation timing, Figure 3.8.2 shows an example of circuit, and Figures 3.8.3 and 3.8.4 show the set-up procedure.
Page 331 M30245 Group 3. Controlling Power Applications (1) Shift to stop mode (2) Cancel a stop mode (3) Key scan Key matrix scan (4) Shift to stop mode output output www.DataSheet4U.com output output to P10 input Key ON Key ON Key input Key OFF Key OFF Key input...
Page 332 M30245 Group 3. Controlling Power Applications M a i n I n i t i a l c o n d i t i o n P u l l - u p c o n t r o l r e g i s t e r 2 Port P0 direction register [ A d d r e s s 0 3 F E [Address 03E2...
Page 333 M30245 Group 3. Controlling Power Applications C o n t i n u e d f r o m t h e p r e v i o u s p a g e I n t e r r u p t e n a b l e f l a g ( I f l a g ) “...
Page 334: Controlling Power Using Wait Mode
M30245 Group 3. Controlling Power Applications 3.9 Controlling Power Using Wait Mode Overview The following are steps for controling power using wait mode. Figure 3.9.1 shows the operation timing, and Figures 3.9.2 to 3.9.4 show the set-up procedure. Use the following peripheral functions: •...
Page 335 M30245 Group 3. Controlling Power Applications Main Initial condition System clock control register 0 [Address 0006 Reserved bit Must always be set to “0” WAIT peripheral function clock stop bit 0 : Do not stop peripheral function clock in wait mode drive capacity select bit COUT www.DataSheet4U.com...
Page 336 M30245 Group 3. Controlling Power Applications Continued from the previous page Canceling protect Protect register [Address 000A PRCR Enables writing to system clock control registers 0 and 1 (address 0006 and 0007 1 : write-enabled Switching system clock System clock control register 0 [Address 0006 www.DataSheet4U.com Reserved bit Must always be set to “0”...
Page 337 M30245 Group 3. Controlling Power Applications INT0 interrupt Store the registers [F_WIT] = 0 www.DataSheet4U.com Restore the registers REIT instruction Timer A2 interrupt Store the registers Counting clock Restore the registers REIT instruction Figure 3.9.4. Set-up procedure of controlling power using wait mode (3) Rev.2.00 Oct 16, 2006 page 328 of 354 REJ09B0340-0200...
Page 338: Chapter 4. External Buses
www.DataSheet4U.com Chapter 4 External Buses...
Page 339: Overview Of External Buses
M30245 Group 4. External Buses 4.1 Overview of External Buses Memory and I/O external expansion can be connected to microcomputer easily by using external buses. When memory expansion mode or microprocessor mode is selected for processor mode, some of the pins function as the address bus, the data bus, and as control signals and this makes the external buses be able to operate.
Page 340: Data Access
M30245 Group 4. External Buses 4.2 Data Access 4.2.1 Data Bus Width If the voltage level input to the BYTE pin is “H”, the external data bus width becomes 8 bits, and P1 through P1 ) can be used as I/O ports (Figure 4.2.1). If the voltage level input to the BYTE pin is “L”, the external data bus width becomes 16 bits, and P0 through P0 ), and P1...
Page 341: Chip Selects And Address Bus
M30245 Group 4. External Buses 4.2.2 Chip Selects and Address Bus ______ ______ Chip selects (P4 /CS0 through P4 /CS3) are output in areas resulting from dividing a 1-M byte memory space into four. To use the chip select, the chip select output must be enabled by setting the chip select control register.
Page 342: R/W Modes
M30245 Group 4. External Buses C h i p s e l e c t c o n t r o l r e g i s t e r S y m b o l A d d r e s s W h e n r e s e t C S R 0 0 0 8...
Page 343: Connection Examples
M30245 Group 4. External Buses 4.3 Connection Examples 4.3.1 16-bit Memory to 16-bit Width Data Bus Connection Example Figure 4.3.1 shows an example of connecting M5M51016BTP (SRAM). In this diagram, when reset the microcomputer starts operating in single-chip mode. Change this mode to memory expansion mode in a program.
Page 344: 8-Bit Memory To 16-Bit Width Data Bus Connection Example
M30245 Group 4. External Buses 4.3.2 8-bit Memory to 16-bit Width Data Bus Connection Example Figure 4.3.2 shows an example of connecting two M5M5278's (SRAM) to a 16-bit data bus.In this dia- gram, when reset the microcomputer starts operating in single-chip mode. Change this mode to memory expansion mode in a program.
Page 345 M30245 Group 4. External Buses _______ ________ Figure 4.3.3 shows how to connect two Am29LV008B (flash memory). In 16-bit bus mode,the BHE/WRH _______ pin functions as BHE. When connecting 8-bit flash memory chips to the 16-bit bus, make sure the ________ _____ microcomputer’s WRL pin is connected to the WR pins on both flash memory chips, and that data is...
Page 346: 8-Bit Memory To 8-Bit Width Data Bus Connection Example
M30245 Group 4. External Buses 4.3.3 8-bit Memory to 8-bit Width Data Bus Connection Example Figure 4.3.4 shows an example of connecting two M5M5278's (SRAM) to an 8-bit data bus.In this dia- gram, when reset the microcomputer starts operating in single-chip mode. Change this mode to memory expansion mode in a program.
Page 347: Two 8-Bit And 16-Bit Memory To 16-Bit Width Data Bus Connection Example
M30245 Group 4. External Buses 4.3.4 Two 8-bit and 16-Bit Memory to 16-Bit Width Data Bus Connection Example Figure 4.3.5 shows an example of connecting M5M28F102 (16-bit flash memory) and two M5M5278's (8- bit SRAM) to a 16-bit data bus. M i c r o c o m p u t e r C N V W R H...
Page 348: Chip Selects And Address Bus
M30245 Group 4. External Buses 4.3.5 Chip Selects and Address Bus When there are insufficient chip select signals, it is necessary to generate chip selects externally. Figure _______ 4.3.6 shows an example of a connection in which the CS2 (128K bytes) area is divided into four 32K byte areas.
Page 349: Connectable Memories
M30245 Group 4. External Buses 4.4 Connectable Memories 4.4.1 Operation Frequency and Access Time Connectable memories depend upon the BCLK frequency f(BCLK). The frequency of f(BCLK) is equal to that of the BCLK, and is contingent on the oscillator's frequency and on the settings in the system clock select bits (bit 6 of address 0006 , and bits 6 and 7 of address 0007 The following are the conditional equations for the connections.
Page 350 M30245 Group 4. External Buses (4) Output enable time [ta(OE)] Output enable time [ta(OE)] must satisfy the following conditional expressions: (a) Vcc = 3.0 to 3.6 V • With the Wait option cleared /(f(BCLK) × 2) – 60(ns) = tac1(RD-DB) ta(OE) <...
Page 351 M30245 Group 4. External Buses OE access time 4000 Without wait 1 wait 3500 3440 2 waits 3 waits 3000 www.DataSheet4U.com 2500 2440 2000 1690 1500 1440 1190 1107 1000 Data set up time 4000 3960 Without wait 3500 1 wait 2 waits 3 waits 3000...
Page 352: Connecting Low-Speed Memory
M30245 Group 4. External Buses 4.4.2 Connecting Low-Speed Memory To connect memory with long access time [ta(A)], either decrease the frequency of BCLK or set a soft- ________ ware wait. Using the RDY feature allows you to connect memory having the timing that precludes con- nection though you set software wait.
Page 353 M30245 Group 4. External Buses S i n g l e - c h i p m o d e 0 0 0 0 0 BCLK × 2 S F R a r e a 0 0 4 0 0 BCLK ×...
Page 354 M30245 Group 4. External Buses ________ (2) RDY function usage _______ To use the RDY function, set a software wait. _______ _______ The RDY function operates when the BCLK signal falls with the RDY pin at “L”; the bus does not vary for 1 BCLK, and the state at that moment is held.
Page 355: Connectable Memories
M30245 Group 4. External Buses 4.4.3 Connectable Memories Connectable memories and their maximum frequencies are given here; M30245 group maximum frequency is 16MHz (without the wait) for Vcc=3V, (1) Flash memories (Read only mode) ( a ) 3 V w i t h o u t w a i t Maximum M o d e l N o .
Page 356 M30245 Group 4. External Buses __________ __________ 4.5 Releasing an External Bus (HOLD input and HLDA output) The Hold feature is to relinquish the address bus, the data bus, and the control bus on M30245 side in line with the Hold request from the bus master other than M30245 when the two or more bus masters share the address bus, the data bus, and the control bus.
Page 357 M30245 Group 4. External Buses Timing chart BCLK HOLD HLDA Indeterminate www.DataSheet4U.com RD/WR Bus released (1) (2) (3) (4) (5) (6) (7) (1) An “L” level is input to the HOLD pin. (2) HOLD is detected. (3) The CPU releases the bus. (4) An “L”...
Page 358: Precautions For External Bus
M30245 Group 4. External Buses 4.6 Precautions for External Bus Description When the MCU enters wait mode while operating in memory expansion mode or micropro- cessor mode, a pin functioning as part of the address or data bus retains it's state on the bus before wait mode is entered.
Page 359 www.DataSheet4U.com THIS PAGE IS BLANK FOR REASONS OF LAYOUT.
Page 360: Chapter 5. Standard Characteristics
www.DataSheet4U.com Chapter 5 Standard Characteristics...
Page 361: Dc Standard Characteristics
M30245 Group 5. Standard Characteristics 5.1 DC Standard Characteristics Standard characteristics described in this chapter are just examples and not guaranteed. For rated values, refer to "Electrical Characteristics" of Datasheet. 5.1.1 Port Standard Characteristics Figures 5.1.1 to 5.1.4 show port standard characteristics. Vcc=3.3V www.DataSheet4U.com Topr = -20°C...
Page 362 M30245 Group 5. Standard Characteristics Vcc=3.3V Topr = -20°C Topr = 25°C Topr = 85°C www.DataSheet4U.com Note 1 : These characteristics are just examples and not guaranteed. For rated values, refer to “Electrical Characteristics” of Datasheet. Figure 5.1.3. V standard characteristics of ports P6 to P6 Vcc=3.3V Topr = -20°C...
Page 363: Vcc-Icc Characteristics
M30245 Group 5. Standard Characteristics 5.1.2 V Characteristics Figure 5.1.5 and Figure 5.1.6 show V characteristics. Measuring condition Topr = 25°C ) : Square wave 16MH Single-chip mode www.DataSheet4U.com Without wait No division mode Figure 5.1.5. Vcc-Icc characteristics (Mask version) Measuring condition Topr = 25°C ) : Square wave 16MH...
Page 364 M30245 Group User’s Manual REVISION HISTORY Rev. Date Description Page Summary – First edition issued Jan 24, 2003 2.2.1 (c) “3 types” → “2 types”, “an external input signal” deleted 2.00 Oct 16, 2006 ” → “–” Figure 2.2.4 UDF: bit 5-7; R “ www.DataSheet4U.com Figure 2.2.5 ONSF Note 3 added 2.2.10 deleted...
Page 365 M30245 Group User’s Manual REVISION HISTORY Rev. Date Description Page Summary 2.00 Oct 16, 2006 Figure 2.7.3 FSC: bit 2, 1 revised Table 2.7.1 revised Table 2.7.3 revised 2.8.2 •USB control register; “the minimum 250ns of delay” → “a minimum 187.5 www.DataSheet4U.com ns of delay (three cycles of BCLK)”...
Page 366 RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER USER’S MANUAL M30245 Group Publication Data : Rev.A Jan 24, 2003 Rev.2.00 Oct 16, 2006 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 367 M30245 Group www.DataSheet4U.com User's Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

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Renesas M16C Series User Manual

Chapter 1. Hardware

Chapter 2. Peripheral Functions Usage

Chapter 4. External Buses

Chapter 5. Standard Characteristics

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