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M16C/5L Group, M16C/56 Group
17.3.1.8
Three-Phase Output Forced Cutoff Function
While the INV02 bit in the INVC0 register is 1 (three-phase motor control timer function) and the
INV03 bit is 1 (three-phase motor control timer output enabled), when a low-level signal is applied to
the SD pin, the INV03 bit in the INVC0 register becomes 0 (three-phase motor control timer output
disabled), and pins corresponding to U, U , V, V , W and W outputs change concurrently as follows:
•
When the IVPCR1 bit in the TB2SC register is 1 (three-phase output forced cutoff enabled)
High-impedance
•
When the IVPCR1 bit in the TB2SC register is 0 (three-phase output forced cutoff disabled)
I/O ports or other peripheral function I/O ports
However, applying a low-level signal to the SD pin while the IVPCR1 bit is 1 places the pins in a high-
impedance state even when the pins are used as functions other than U, U , V, V , W and W outputs.
Table 17.7 lists State of Pins U, U , V, V , W, and W .
State of Pins U, U, V, V, W, and W
Table 17.7
IVPCR1 bit in the TB2SC
register
1
0
Note:
1.
The above assumes bits INVC02, INVC03, and PFCi are all 1.
The digital debounce filter is available for the SD pin. When the SD pin level remains at a level longer
than the width of the digital debounce filter, the level is transferred to the internal circuit. The NDDR
register can be set the digital debounce filter width. Refer to 13.4.3 " NMI / SD Digital Filter" for details.
To return the pin function to three-phase PWM output after a forced cutoff, follow these steps:
(1) Apply a high-level signal to the SD pin.
(2) Wait for more than width of the digital debounce filter (digital debounce filter enabled).
(3) Set the INV03 bit in the INVC0 register to 1 (three-phase motor control timer output enabled).
(4) Confirm that the INV03 bit is 1. If the bit is 0, return to step (3).
(5) Set the IVPCR1 bit to 0 (three-phase output forced cutoff disabled).
(6) Set the IVPCR1 bit to 1 (when enabling three-phase output forced cutoff again).
When not using the three-phase output forced cutoff function, set a port direction bit which shares the
pin with SD input to 0 (input port), and apply a high-level signal to the SD pin.
The same pin is used for both SD input and NMI input. To disable the NMI interrupt, set the PM24 bit
in the PM2 register to 0 ( NMI interrupt disabled).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
State of Bit and Pin
SD pin input
High
Low
High
Low
17. Three-Phase Motor Control Timer Function
(1)
Function or State of Pins U, U , V, V , W and W
Three-phase PWM output
High-impedance
Three-phase PWM output
I/O port or other peripheral functions
Page 323 of 803
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