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M16C/5L Group, M16C/56 Group
f1TIMS
f1
f2TIMS
1/2
Two-phase
TSUDA
pulse input
TSUDB
processor
f1TIMS
or
f2TIMS
Time measurement function and wave
generation function for channels 0 and 1
IFE0
FSC0
INPC1_0
IFE1
FSC1
INPC1_1
Time measurement function and waveform generation function for channels 2 and 3
INPC1_2
(The logic circuit for these channels is equivalent to the one for channels 0 and 1.
INPC1_3
Names of registers, bits and signals for channels 0 and 1 are also applied to names
of those for channels 2 and 3.)
f1TIMS or f2TIMS
Continued on the next page
j = 0 to 3
INV, RLD, IVL, MOD1 to MOD0: Bits in the G1POCRj register
DF1 to DF0, CTS1 to CTS0: Bits in the G1TMCRj register
IT, RST4, BCK1 to BCK0: Bits in the G1BCR0 register
UD1 to UD0, BTS, RST2, RST1: Bits in the G1BCR1 register
IFEj: Bit in the G1FE register
Figure 18.1
IC/OC Block Diagram (1/2)
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Clock stopped
PCLK0
BCK1 to BCK0
f1TIMS
00b
1
or f2TIMS
11b
0
10b
Two-phase pulse clock
fBT1
(n+1) divider
G1DV
11b
10b
DF1 to DF0
Sampling clock
CTS1 to CTS0
Digital
10b,11b
Edge
filter
00b
select
DF1 to DF0
11b
10b
DF1 to DF0
Sampling clock
CTS1 to CTS0
Digital
10b,11b
Edge
filter
00b
select
DF1 to DF0
fBT1
fBT1
G1BT
UD1 to UD0
Base timer reset
IT
Base timer overflow
Base timer
Comparator
G1BTRR
RLD
Comparator
G1PO0
G1TM0
Time measurement trigger
IO01 to IO00
MOD1 to MOD0
IVL
Waveform generator
IO11 to IO10
MOD1 to MOD0
IVL
RLD
Comparator
G1PO1
G1TM1
Time measurement trigger
FSCj: Bit in the G1FS register
EOCj: Bit in the G1OER register
IOj1 to IOj0: Bits in registers G1IOR0 and G1IOR1
PCLK0: Bit in the PCLKR register
BTS
INT1
RST2
IC/OC base timer interrupt
(IR bit in the BTIC register)
Match
RST4
RST1
Match
IFE0
FSC0
INV EOC0
0
1
INV EOC1
0
1
IFE1
FSC1
Match
Page 345 of 803
18. Timer S
Channel 0
interrupt
request
OUTC1_0
OUTC1_1
Channel 1
interrupt
request
Channel 2
interrupt
request
OUTC1_2
OUTC1_3
Channel 3
interrupt
request
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