Renesas M16C/50 Series User Manual page 524

M16C/5L Group, M16C/56 Group
(1) The ABSCS Bit in the U2SMR Register (Bus collision detect sampling clock select)
Transmit/
receive clock
TXD2
RXD2
Timer A0
(2) The ACSE Bit in the U2SMR Register (Auto clear of transmit enable bit)
Transmit/
receive clock
TXD2
RXD2
IR bit in BCNIC register
TE bit in U2C1
register
(3) The SSS Bit in the U2SMR Register (Transmit start condition select)
If the SSS bit is 0, the serial interface starts sending data one transmit/receive
clock cycle after the transmission enable condition is met.
Transmit/
receive clock
TXD2
If the SSS bit is 1, the serial interface starts sending data at the rising edge of RXD2
CLK2
TXD2
RXD2
Notes:
1. The falling edge of RXD2 when the IOPOL bit is 0; the rising edge of RXD2 when the IOPOL bit is1.
2. The transmit condition must be met before the falling edge of RXD2
The above assumes the IOPOL bit is 1 (inverted).
Figure 21.29 Bus Collision Detect Function-Related Bits
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
If the ABSCS bit is 0, bus collision is determined at the rising edge of the transmit/receive clock
ST D0 D1
Trigger signal is applied to the TA0IN pin
If the ABSCS bit is 1, bus collision is determined when timer A0 (one-shot timer mode) underflows.
ST D0 D1
ST D0
Transmit enable conditions are met
ST D0
(2)
D2 D3 D4 D5
D2 D3 D4 D5
D1 D2 D3 D4 D5
D1 D2 D3 D4 D5
(1)
.
21. Serial Interface UARTi (i = 0 to 4)
D6 D7 D8 SP
D6 D7 D8 SP
If ACSE bit is 1 (automatically
clear when bus collision occurs),
the TE bit is cleared to 0
(transmission disabled) when the
IR bit in the BCNIC register is 1
(unmatching detected).
D6 D7 D8 SP
(1)
D6 D7 D8 SP
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