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M16C/5L Group, M16C/56 Group
f1TIMS or f2TIMS
Two-phase
TSUDA
pulse input
TSUDB
processor
BTS bit in the G1BCR1 register
Match with the G1BTRR register
Match with the G1PO0 register
Apply low to the INT1 pin
Figure 18.3
Base Timer Block Diagram
Table 18.6
Base Timer Associated Register Settings
Register
Bit
BCK1 and BCK0 Select a count source.
RST4
G1BCR0
IT
RST1
RST2
G1BCR1
BTS
UD1 and UD0
G1BT
—
G1DV
—
G1BTRR
—
G1POCR0 MOD1 and MOD0 — (Do not use for the base timer)
G1PO0
—
G1FS
FSC0
G1FE
IFE0
G1IOR0
IO01 and IO00 — (Do not use for the base timer)
Note:
1.
This table does not describe a procedure.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
BCK1 and BCK0
11b
10b
Two-phase pulse clock
RST4
RST1
RST2
Base timer reset not used
Set to 0.
Select a timing of IC/OC
base timer interrupt request.
Set to 0.
Select whether the INT1 pin
is used for base timer reset.
Set to 1 to start the base
timer count.
Set to 0 to reset the base
timer count.
Select a count operation.
Base timer value can be
read.
Set a divide ratio of the
count source.
— (Do not use)
— (Do not use for the base timer)
— (Do not use for the base timer)
— (Do not use for the base timer)
G1DV register
fBT1
(n+1) divider
b15
Base timer reset
IT, RST4, BCK1 and BCK0: Bits in the G1BCR0 register
RST2, RST1: Bits in the G1BCR1 register
(1)
Function and Setting Value
Base timer reset by
matching with the G1BTRR
register
Select a count source.
Set to 1.
Select a timing of IC/OC
base timer interrupt request.
Set to 0.
Select whether the INT1 pin
is used for base timer reset.
Set to 1 to start the base
timer count.
Set to 0 to reset the base
timer count.
Select a count operation.
Base timer value can be
read.
Set a divide ratio of the
count source.
Set a base timer reset timing — (Do not use)
G1BT register
0
1
IT
Base timer
b14
Base timer reset by
matching with the G1PO0
register
Select a count source.
Set to 0.
Select a timing of IC/OC
base timer interrupt request.
Set to 1.
Select whether the INT1 pin
is used for base timer reset.
Set to 1 to start the base
timer count.
Set to 0 to reset the base
timer count.
Select a count operation.
Base timer value can be
read.
Set a divide ratio of the
count source.
Set to 00b
Set a base timer reset timing
Set to 0.
Set to 1.
Set to 00b.
Page 369 of 803
18. Timer S
Base timer
overflow
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