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M16C/5L Group, M16C/56 Group
10.3
Software Wait
The PM17 bit in the PM1 register, PM20 bit in the PM2 register, and FMR17 bit in the FMR1 register
select software wait and the bus cycles will be determined accordingly. Table 10.3 lists the relation
between software wait related bits and bus cycle.
Table 10.3
Software Wait Related Bits and Bus Cycles
Area
SFR
Internal RAM
Program ROM 1
Program ROM 2
Data flash
—
: 0 or 1 has no effect
Note:
1.
Status after reset.
10.4
Bus Hold
The internal bus is in a hold state under the following condition:
•
Rewriting the flash memory in EW1 mode while auto-programming or auto-erasing
When the bus is in hold state, the following occur:
•
CPU stops.
•
DMAC stops.
•
The watchdog timer stops when the CSPRO bit in the CSPR register is 0 (count source protection
mode disabled).
•
The I/O port state is maintained.
Bus use priority is given to bus hold, DMAC, and CPU in descending order. However, if the CPU is
accessing an odd address in word units, DMAC cannot gain control of the bus between two separate
accesses. Figure 10.1 "Bus Use Priority" shows the bus use priority.
Figure 10.1
Bus Use Priority
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Software Wait Related Bits and Settings
FMR17 bit in the
PM17 bit in the
FMR1 register
PM1 register
—
—
—
0
1
Bus Hold > DMAC > CPU
Software
Wait
—
1 wait
0
no wait
1
1 wait
0
no wait
1
1 wait
—
1 wait
0
no wait
1
1 wait
10. Processor Mode
Bus Cycle
(1)
2 BCLK cycles
(1)
1 BCLK cycle
2 BCLK cycles
(1)
1 BCLK cycles
2 BCLK cycles
(1)
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
Page 143 of 803
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