Renesas M16C/50 Series User Manual page 306

M16C/5L Group, M16C/56 Group
m
Counter
operations of
0000h
lower bits
255-n
n
Counter
operations of
upper bits
0000h
TAiS bit in the
TABSR register
TAiOUT output
POFSi = 0
POFSi = 1
Low-level output
immediately after
count started
IR bit in the
TAiIC register
i = 0 to 4
POFSi: Bits in the TAPOFS register
fj: Count source frequency
The above timing diagram assumes the following:
- The MR0 bit in the TAiMR register = 1 (pulse output)
- The MR2 bit in the TAiMR register = 0 (the TAiS bit in the TABSR is the trigger)
- The MR3 bit in the TAiMR register = 1 (8-bit PWM mode)
b15
TAi register
Operates as an 8-bit
pulse width modulator
Figure 15.12 Operation Example in 8-Bit Pulse Width Modulation Mode
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Count started
m+1
Count started
n+1 n
(n+1)(m+1) n(m+1)
fj fj
b8 b7
n m
Operates as a prescaler
255-n
255
n(m+1)
255(m+1)
fj
Set to 0 by accepting an interrupt request, or
by a program.
b0
n = 03h m = 02h
15. Timer A
fj
255(m+1)
fj
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