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REVISION HISTORY
Rev.
Date
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1.10 Sep. 01, 2011
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457, 466 21.3.1.5 CTS / RTS Function, 21.3.2.5 CTS / RTS Function: Deleted the CRD and CRS bit
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M16C/5L, M16C/56 Group User's Manual: Hardware
21.2.5 UARTi Transmit Buffer Register (UiTB) (i = 0 to 4):
2
Added "or I
C mode" after "When character length is 9 bits long...".
21.2.6 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 4):
• Deleted the CRS bit explanation.
• Changed the first and second paragraphs in the NCH bit explanation.
21.2.9 UART2 Special Mode Register 4 (U2SMR4):
• Changed the Function column of bits STSPSEL, ACKC, SCLHI, and SWC9.
• Changed the bit names of bits SCLHI and SWC9.
• Added an explanation regarding I
RSTAREQ, and STPREQ.
• Added bit explanations for the other bits.
21.2.11 UART2 Special Mode Register 2 (U2SMR2):
• Changed the bit names of bits SWC, ALS, and STAC.
• Changed the functions of bits other than b7.
21.3 Operations: Inserted the title.
Table 21.5 Clock Synchronous Serial I/O Mode Specifications: Changed note 1 and note 2.
Table 21.6 Pin Functions in Clock Synchronous Serial I/O Mode:
• Added the I/O column.
• Changed "the port direction bit corresponding to xxx pin" to "the port direction bit sharing pin" in
the Method of Selection column.
• Added the Input, Input port row to the RXDi pin.
Table 21.7 Registers Used and Settings in Clock Synchronous Serial I/O Mode:
• Added UCLKSEL0 and PCLKR rows to the Register column.
• Added b8 to UiTB.
• Added b8, b11, and b13 to b15 to UiRB.
• Added b4 to b6 to UiMR.
• Deleted note 1.
21.3.1.3 Continuous Receive Mode:
• Added an explanation for when using an external clock.
• Added Figure 21.6 Operation Example in Continuous Receive Mode.
explanation and added a reference to a table that includes similar information.
21.3.1.6 Processing When Terminating Communication or When an Error Occurs: Moved the
contents of "21.2.1 Transmit/Receive Register Initialization" here and rewrote the explanation.
Table 21.8 UART Mode Specifications: Deleted note 2.
Table 21.9 I/O Pin Functions in UART Mode:
• Added the I/O column.
• Changed "the port direction bit corresponding to xxx pin" to "the port direction bit sharing pin" in
the Method of Selection column.
• Modified " RTS input" to " RTS output".
Table 21.10 Registers Used and Settings in UART Mode:
• Added the UCLDSEL0 and PCLKR rows.
• Added b11 to UiRB.
• Changed the order of notes, and changed note 4.
Figure 21.9 Receive Timing in UART Mode:
Changed "UiBRG count source" to "Clock divided by UiBRG".
21.3.2.6 Processing When Terminating Communication or When an Error Occurs: Moved the
contents of "21.3.2 Transmit/Receive Circuit Initialization" here and rewrote the explanation.
2
Table 21.12 I
C Mode Specifications:
• Changed the setting value of U2BRG register n from "00h to FFh" in the Transfer clock row.
• Changed note 1 and note 2.
Figure 21.14 Internal Clock Configuration: Added.
Table 21.13 I/O Pin Functions in I
C- 10
Description
Summary
2
C master mode to the existing bit explanations of STAREQ,
2
C Mode: Added note 1, and the previous note 1 became note 2.
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