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M16C/5L Group, M16C/56 Group
8.3.2
PLL Clock
PLL clock is generated by the PLL frequency synthesizer. This clock is used as the clock source for the
CPU and peripheral function clocks.
After reset, the PLL frequency synthesizer is stopped.
PLL clock is a clock which divides the main clock by the selected values of bits PLC05 to PLC04 in the
PLC0 register, and then multiplied by the selected values of bits PLC02 to PLC00. Set bits PLC05 and
PLC04 to fit divided frequency between 2 MHz and 5 MHz. Figure 8.3 shows Relation between Main
Clock and PLL Clock.
Main clock
Figure 8.3
Relation between Main Clock and PLL Clock
Table 8.5
Example Settings for PLL Clock Frequencies
Main Clock
10 MHz
5 MHz
12 MHz
6 MHz
16 MHz
8 MHz
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Divided by n
n: 1, 2, 4 (selected by setting bits PLC05 and PLC04 in the PLC0 register)
m: 2, 4, 6, 8 (selected by setting bits PLC02 to PLC00 in the PLC0 register)
Notes:
1. Set the frequency divided by n to between 2 MHz and 5 MHz.
2. Set the PLL clock frequency to be within the f(PLL) range.
Setting Value
Bits PLC05 to PLC04
01b (divide-by-2)
00b (not divided)
10b (divide-by-4)
01b (divide-by-2)
10b (divide-by-4)
01b (divide-by-2)
Multiplied by m
(See Note 1)
Bits PLC02 to PLC00
010b (multiply-by-4)
010b (multiply-by-4)
100b (multiply-by-8)
100b (multiply-by-8)
100b (multiply-by-8)
100b (multiply-by-8)
8. Clock Generator
PLL clock
(See Note 2)
PLL Clock
20 MHz
24 MHz
32 MHz
Page 105 of 803
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