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M16C/5L Group, M16C/56 Group
22.2.3
I2C0 Control Register 0 (S1D0)
I2C0 Control Register 0
b7 b6 b5 b4
b3
b2
b1
0
BC2 to BC0 (Bit counter) (b2-b0)
Bits BC2 to BC0 become 000b (8 bits) when a start condition is detected.
When the ACKCLK bit in the S20 register is 0 (no ACK clock), and data for the number of bits selected
by bits BC2 to BC0 is transmitted or received, bits BC2 to BC0 become 000b again.
When the ACKCLK bit in the S20 register is 1 (ACK clock), and data for the number of bits selected and
an ACK is transmitted or received, bits BC2 to BC0 become 000b again.
2
ES0 (I
C-bus interface enable bit) (b3)
The ES0 bit enables the I
When the ES0 bit is set to 0, the I
•
Pins SDAMM and SCLMM: I/O ports or other peripheral pins
•
The S00 register is write disabled.
2
•
The I
C-bus system clock (hereinafter called fVIIC) stops.
•
S10 register
ADR0 bit: 0 (general call not detected)
AAS bit: 0 (slave address not matched)
AL bit: 0 (arbitration lost not detected)
PIN bit: 1 (no I
BB bit: 0 (bus free)
TRX bit: 0 (receive mode)
MST bit: 0 (slave mode)
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b0
S1D0
Bit Symbol
Bit Name
BC0
Bit counter (number of
BC1
transmitted/received bits)
BC2
2
ES0
I
C-bus interface enable bit
ALS
Data format select bit
—
Reserved bit
(b5)
2
IHR
I
C-bus interface reset bit
2
I
C-bus interface pin input
TISS
level select bit
2
C interface.
2
C interface becomes as follows:
2
C-bus interrupt request)
22. Multi-master I
Address
02B3h
Function
b2 b1 b0
0 0 0: 8
0 0 1: 7
0 1 0: 6
0 1 1: 5
1 0 0: 4
1 0 1: 3
1 1 0: 2
1 1 1: 1
0: Disabled
1: Enabled
0: Addressing format
1: Free data format
Set to 0.
0: Reset is deasserted (automatically)
1: Reset
2
0: I
C-bus input
1: SMBus input
2
C-bus Interface
Reset Value
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
Page 505 of 803
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