Renesas M16C/50 Series User Manual page 427

M16C/5L Group, M16C/56 Group
Table 18.17 Registers and Settings in SR Waveform Output Mode
Register
G1POj
G1FS
G1FE
MOD1 and MOD0 Set to 01b.
G1POCRj
G1OER
G1IOR0
IOj1 and IOj0
G1IOR1
G1BCR1 UD1 and UD0
j = 0, 2, 4, 6; k = j + 1, however, when the RST1 bit in the G1BCR1 register is 1 (the base timer is reset
when the base timer and G1PO0 register values match), then j = 2, 4, 6.
Notes:
1. This table does not describe a procedure.
2. When the INV bit in the G1POCRj register is 0 (output level not inverted).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Bit
Even channel (channel j)
Set the timing for an output level to
—
become high.
Set to 0 (waveform generation
FSCj
function selected).
Set to 1 (channel j function
IFEj
enabled).
Select a default value of an output
IVL
level.
Select the reload timing for the
RLD
G1POj register value.
Select whether an output level is
INV
inverted.
Set to 1 when the OUTC1_j is
EOCj
disabled.
Set to 00b.
Set to 00b.
Function
Set the timing for an output level to
(2)
become low.
Set to 0 (waveform generation
function selected).
Set to 1 (channel k function
enabled).
Set to 01b.
— (invalid)
Select the reload timing for the
G1POk register value.
— (invalid)
Set to 1.
Set to 00b.
(1)
Odd channel (channel k)
(2)
Page 390 of 803
18. Timer S