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M16C/5L Group, M16C/56 Group
RLD (G1POj register value reload timing select bit) (b5)
For SR waveform output mode, set both even channels (channel j (j = 0, 2, 4, or 6)) and odd channels
(channel j+1).
When writing a value to the G1POj register (j = 0 to 7) while the BTS bit is 0 (base timer reset) and the
RLD bit is 1 (reload the G1POj register when the base timer is reset), the written value will not be
reloaded to a buffer.
Therefore, when the BTS bit is 0, set the RLD bit to 0 (reload on a write access), write a value to the
G1POj register, and then set the RLD bit to 1 after one or more fBT1 cycles.
When the RLD bit is set to 1, the value will not be reloaded at the following timings:
•
When the base timer counter changes from FFFFh to 0000h immediately after writing FFFFh to the
base timer while incrementing in increment mode or increment/decrement mode.
•
When the base timer counter changes from 0000h to FFFFh immediately after writing 0000h to the
base timer while decrementing in increment/decrement mode.
INV (Output level inversion select bit) (b7)
The output level inversion function is located at the final step of waveform generation circuit. When the
INV bit is set to 1 (output level inverted), the default output value becomes high if the IVL bit is set to 0,
and the default output value becomes low if the IVL bit is set to 1.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
18. Timer S
Page 353 of 803
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