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M16C/5L Group, M16C/56 Group
18.5
Notes on Timer S
18.5.1
Register Access
The explanation for some bits and registers states, "the value written to this register or this bit is
reflected to the internal circuit when the clock is synchronized with the base timer count source (fBT1)".
When writing these bits or registers, the written value is not reflected to the internal circuits immediately.
After writing the value, prewrite operations are performed for up to one fBT1 cycle. When reading these
bits or registers immediately after writing the value, the value before writing may be read.
18.5.2
Changing the G1IR Register
Set the G1IRj bit in the G1IR register (j = 0 to 7) to 0 by a program since it does not become 0
automatically with an interrupt request reception.
However, the G1IRj bit cannot be set to 0 for one fBT1 cycle after this bit becomes 1. Wait for one or
more fBT1 cycles after the G1IRj bit becomes 1, then set this bit to 0.
To write 0 to the G1IRj bit, use the AND and BCLR instructions to avoid deleting requests for other
channels.
Figure 18.20 shows "IC/OC Interrupt 0 Operation Example". As shown in the operation example,
disable interrupt requests for all channels once at the last part of an interrupt process, then enable them
again.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
18. Timer S
Page 395 of 803
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