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M16C/5L Group, M16C/56 Group
13.2.2
Count Source Protection Mode Register (CSPR)
Count Source Protection Mode Register
b7 b6 b5 b4
b3
b2
b1
b0
CSPRO (Count Source Protection Mode Select Bit) (b7)
To set the CSPRO bit to 1, write 1 immediately after writing 0. The CSPRO bit cannot be set to 0 by a
program.
When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled), the
following are automatically set:
•
Dedicated 125 kHz on-chip oscillator for the watchdog timer starts oscillating.
•
The PM12 bit in the PM1 register is set to 1 (watchdog timer reset is initiated when the watchdog
timer underflows.).
•
The initial value of the watchdog timer is a value set by setting bits WDTUFS1 and WDTUFS0 in
the OFS2 address.
When the CSPROINI bit in the OFS1 address is 0, the CSPRO bit becomes 1. The CSPROINI bit
cannot be changed by a program. In order to set the CSPROINI bit, write 0 to bit 7 of address 0FFFFFh
by using a flash programmer.
Do not change the CSPRO bit setting while the watchdog timer is operating.
13.2.3
Watchdog Timer Refresh Register (WDTR)
Watchdog Timer Refresh Register
b7
After the watchdog timer interrupt is generated, refresh the watchdog timer by writing to the WDTR
register.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
CSPR
Bit Symbol
Bit Name
—
No register bits. If necessary, set to 0. The read value is 0.
(b6-b0)
Count source protection mode
CSPRO
select bit
b0
Symbol
WDTR
The watchdog timer counter is refreshed by writing 00h and then FFh to this register.
The default value is indicated by setting bits WDTUFS1 and WDTUFS0 in the OFS2 address.
Address
037Ch
0000 0000b
(when the CSPROINI bit in the OFS1 address is 1)
1000 0000b
(when the CSPROINI bit in the OFS1 address is 0)
0 : Count source protection mode
disabled
1 : Count source protection mode enabled
Address
037Dh
Function
13. Watchdog Timer
Reset Value
Function
RW
RW
Reset Value
XXh
Page 203 of 803
—
RW
WO
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