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M16C/5L Group, M16C/56 Group
23.5
Acceptance Filtering and Masking Function
Acceptance filtering allows the user to receive messages with a specified range of multiple IDs for
mailboxes.
Registers C0MKR0 to C0MKR7 can perform masking of the standard ID and the extended ID of 29 bits.
• The C0MKR0 register corresponds to mailboxes [0] to [3].
• The C0MKR1 register corresponds to mailboxes [4] to [7].
• The C0MKR2 register corresponds to mailboxes [8] to [11].
• The C0MKR3 register corresponds to mailboxes [12] to [15].
• The C0MKR4 register corresponds to mailboxes [16] to [19].
• The C0MKR5 register corresponds to mailboxes [20] to [23].
• The C0MKR6 register corresponds to mailboxes [24] to [27] in normal mailbox mode, and receive
FIFO mailboxes [28] to [31] in FIFO mailbox mode.
• The C0MKR7 register corresponds to mailboxes [28] to [31] in normal mailbox mode, and receive
FIFO mailboxes [28] to [31] in FIFO mailbox mode.
The C0MKIVLR register disables acceptance filtering individually for each mailbox.
The IDE bit in the C0MBj register (j = 0 to 31) is enabled when the IDFM bit in the C0CTLR register is 10b
(mixed ID mode).
The RTR bit in the C0MBj register selects a data frame or a remote frame.
In FIFO mailbox mode, normal mailboxes (mailboxes [0] to [23]) use the single corresponding register
among registers C0MKR0 to C0MKR5 for acceptance filtering. Receive FIFO mailboxes (mailboxes [28]
to [31]) use two registers C0MKR6 and C0MKR7 for the acceptance filtering.
Also, the receive FIFO uses two registers C0FIDCR0 and C0FIDCR1 for ID comparison. Bits EID, SID,
RTR, and IDE in registers C0MB28 to C0MB31 for the receive FIFO are disabled. As acceptance filtering
depends on the result of two ID-mask sets, two ranges of IDs can be received into the receive FIFO.
The C0MKIVLR register is disabled for the receive FIFO.
If both setting of standard ID and extended ID are set in the IDE bits in registers C0FIDCR0 and
C0FIDCR1 individually, both ID formats are received.
If both setting of data frame and remote frame are set in the RTR bits in registers C0FIDCR0 and
C0FIDCR1 individually, both data and remote frames are received.
When combination with two ranges of IDs is not necessary, set the same mask value and the same ID
into both of the FIFO ID/mask register sets.
Figure 23.41 shows the correspondence of mask registers to mailboxes, and Figure 23.42 shows
acceptance filtering.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
23. CAN Module
Page 608 of 803
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