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M16C/5L Group, M16C/56 Group
24. A/D Converter
Note
The 64-pin package has no AN0_4 to AN0_7 (P0_4 to P0_7), AN2_0 to AN2_3 (P1_0 to P1_3),
AN2_5 to AN2_7 (P9_5 to P9_7).
24.1
Introduction
The A/D converter consists of one 10-bit successive approximation A/D converter.
Table 24.1 lists the A/D Converter Specifications and Figure 24.1 shows an A/D Converter Block Diagram.
Table 24.1
A/D Converter Specifications
Item
A/D conversion
method
Analog input voltage
Operating clock φ AD
Resolution
Integral nonlinearity
error
Operation modes
Analog input pins
A/D conversion start
conditions
Conversion rate per
pin
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Successive approximation
0 V to AVCC (VCC)
f1, f1 divided by 2, f1 divided by 3, f1 divided by 4, f1 divided by 6, f1 divided by 12,
fOCO40M divided by 2, fOCO40M divided by 3, fOCO40M divided by 4, fOCO40M
divided by 6, or fOCO40M divided by 12
10 bits
AVCC = VREF = 5 V
±3 LSB
AVCC = VREF = 3.3 V
±5 LSB
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0
8 pins (AN0 to AN7) + 8 pins (AN0_0 to AN0_7) + 8 pins (AN2_0 to AN2_7) + 3
pins (AN3_0 to AN3_2) (80-pin package)
8 pins (AN0 to AN7) + 4 pins (AN0_0 to AN0_3) + 1 pin (AN2_4) + 3 pins (AN3_0
to AN3_2) (64-pin package)
•
Software trigger
The ADST bit in the ADCON0 register is set to 1 (A/D conversion start).
•
External trigger (retrigger is enabled)
Input to the ADTRG pin changes from high to low after the ADST bit is set to 1
(A/D conversion start).
Minimum 43 φ AD cycles
Specification
24. A/D Converter
Page 616 of 803
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