Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 4 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 5 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 6 The following documents apply to the M16C/26A Group (M16C/26A, M16C/26B, and M16C/26T). Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Document Type...
Page 7 Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,”...
Page 8 Register Notation The symbols and terms used in register diagrams are described below. XXX Register Symbol Address After Reset Bit Symbol Bit Name Function b1 b0 XXX bits XXX0 1 0: XXX 0 1: XXX 1 0: Do not set. XXX1 1 1: XXX Nothing is assigned.
Page 9 List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment bus Input/Output IrDA Infrared Data Association Least Significant Bit...
Page 10 Table of Contents Quick Reference by Address _______________________ B-1 1. Overview ______________________________________ 1 1.1 Applications ........................1 1.2 Performance Outline ..................... 2 1.3 Block Diagram ....................... 4 1.4 Product List ........................6 1.5 Pin Assignments ......................11 1.6 Pin Description ......................15 2.
Page 11: Table Of Contents
5. Reset ________________________________________ 26 5.1 Hardware Reset ......................26 5.1.1 Hardware Reset 1 ....................26 5.1.2 Hardware Reset 2 ....................26 5.2 Software Reset ......................27 5.3 Watchdog Timer Reset ....................27 5.4 Oscillation Stop Detection Reset ................. 27 5.5 Voltage Detection Circuit ..................... 29 5.5.1 Voltage Down Detection Interrupt ...............
Page 12 9.2 Interrupts and Interrupt Vector ..................64 9.2.1 Fixed Vector Tables ....................64 9.2.2 Relocatable Vector Tables ................... 65 9.3 Interrupt Control ......................66 9.3.1 I Flag ........................69 9.3.2 IR Bit ........................69 9.3.3 ILVL2 to ILVL0 Bits and IPL ................. 69 9.4 Interrupt Sequence ......................
Page 13 12.3 Three-phase Motor Control Timer Function ............117 12.3.1 Position-data-retain Function ................128 12.3.2 Three-phase/Port Output Switch Function ............130 13. Serial I/O ___________________________________ 132 13.1. UARTi (i=0 to 2)...................... 132 13.1.1. Clock Synchronous serial I/O Mode ..............142 13.1.2. Clock Asynchronous Serial I/O (UART) Mode ..........150 13.1.3 Special Mode 1 (I C bus mode)(UART2) ............
Page 14 17.2 Memory Map ......................232 17.3 Functions To Prevent Flash Memory from Rewriting..........235 17.3.1 ROM Code Protect Function ................235 17.3.2 ID Code Check Function .................. 235 17.4 CPU Rewrite Mode ....................237 17.4.1 EW0 Mode ....................... 238 17.4.2 EW1 Mode ....................... 238 17.5 Register Description ....................
Page 15 18. Electrical Characteristics _______________________ 261 18.1. M16C/26A, M16C/26B (Normal version) ..............261 18.2. M16C/26T (T version) .................... 280 19. Usage Notes ________________________________ 299 19.1 SFR ......................... 299 19.1.1 Precaution for 48-pin package ................. 299 19.1.2 Precaution for 42-pin package ................. 299 19.1.3 Register Setting ....................
Page 16 19.13 Flash Memory Version ..................320 19.13.1 Functions to Inhibit Rewriting Flash Memory ..........320 19.13.2 Stop mode ...................... 320 19.13.3 Wait mode ...................... 320 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode... 320 19.13.5 Writing command and data ................320 19.13.6 Program Command ..................
Page 17 Quick Reference by Address Register Symbol Page Register Symbol Page Address Address 0000 0040 0001 0041 0002 0042 0003 0043 INT3 interrupt control register INT3IC Processor mode register 0 0004 0044 Processor mode register 1 0005 0045 System clock control register 0 0006 0046 System clock control register 1...
Page 18 Quick Reference by Address Register Symbol Page Register Symbol Page Address Address 0080 0340 0081 0341 0082 0342 Timer A1-1 register TA11 0083 0343 0084 0344 Timer A2-1 register TA21 0085 0345 0086 0346 Timer A4-1 register TA41 0347 Three-phase PWM control register 0 INVC0 0348 Three-phase PWM control register 1...
Page 19 Quick Reference by Address Register Symbol Page Register Symbol Page Address Address 95, 110, Count start flag TABSR 0380 03C0 A/D register 0 03C1 r 0) Clock prescaler reset flag CPSRF 0381 03C2 A/D register 1 One-shot start flag ONSF 0382 03C3 96, 124...
Page 20 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. Overview The M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) is a single-chip control MCU, fabricated using high-performance silicon gate CMOS technology, embedding the M16C/60 Series CPU core. The M16C/ 26A Group (M16C/26A, M16C/26B, M16C/26T) is housed in 42-pin and 48-pin plastic molded packages. This MCU combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed.
Page 21 1. Overview 1.2 Performance Outline Table 1.1 and 1.2 outline performance overview of the M16C/26A Group (M16C/26A, M16C/26B, M16C/ 26T). Table 1.1. M16C/26A Group(M16C/26A, M16C/26B, M16C/26T) Performance (48-Pin Package) Item Specification Basic instructions 91 instructions Z (3) Minimun instruction 41.7 ns (f(BCLK) = 24MH = 4.2 to 5.5 V) (M16C/26B) execution time...
Page 22 1. Overview Table 1.2. Performance outline of M16C/26A group (M16C/26A, M16C/26B) (42-pin package) Item Performance Basic instructions 91 instructions Minimun instruction 41.7 ns (f(BCLK) = 24 MHz , VCC = 4.2 to 5.5 V (M16C/26B) execution time 50 ns (f(BCLK) = 20 MH = 3.0 to 5.5 V) (M16C/26A, M16C/26B) 100 ns (f(BCLK) = 10 MH...
Page 23 1. Overview 1.3 Block Diagram Figure 1.1 and 1.2 show block diagrams of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 48- pin package and 42-pin package. Port P9 Port P8 Port P6 Port P7 Port P10 Port P1 Peripheral functions Clock generation circuit Timer (16-bit) Output (timer A): 5channels UART or...
Page 24 1. Overview Port P9 Port P8 Port P6 Port P7 Port P10 Port P1 Peripheral functions Clock generation circuit Timer (16-bit) Output (timer A): 5channels UART or XIN-XOUT Input (timer B): 3 channels clock synchronous serial I/O XCIN-XCOUT (8 bits X 2 channels) On-Chip Oscillator Three-phase motor PLL frequency synthesizer...
Page 25 1. Overview 1.4 Product List Tables 1.3 to 1.6 lists product information, Figure 1.3 shows a product numbering system, Table 1.7 lists the product code, and Figure 1.4 shows the marking. Table 1.3 M16C/26A Current as of Feb., 2007 y t i y t i Table 1.4 M16C/26B Current as of Feb., 2007...
Page 26 1. Overview Type No. M 3 0 2 6 0 M 8 A - XXX G P - U3 Product code: See Tables 1.7 to 1.10 Package type: GP: PLQP0048KB-A (48P6Q) (M16C/26A, M16C/26B, M16C/26T) FP: PRSP0042GA-B (42P2R) (M16C/26A, M16C/26B) ROM number: ROM number is omitted in flash memory version Version: : M16C/26A...
Page 27 1. Overview Table 1.7 Product Code (Flash Memory Version) - M16C/26A, M16C/26B C º C º C º C º C º C º C º C º Table 1.8 Product Code (Mask ROM Version - M16C/26A) C º C º C º...
Page 28 1. Overview (1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26A, M16C/26B Product Name : indicates M30260F8AGP 0260F8A Chip Version and Product Code: A U3 A : Indicates chip version XXXXX The first edition is shown to be blank and continues with A and B. U3 : Indicates Product code (see Table 1.7 Product Code) Date Code (5 digits) ﬁ...
Page 29 1. Overview (1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26T T-ver. 0260F8T Product Name : indicates M30260F8TGP A U3 Chip Version and Product Code: A : Indicates chip version XXXXX The first edition is shown to be blank and continues with A and B. U3 : Indicates product code (see Table 1.9 Product Code) Date Code (5 digits) ﬁ...
Page 30 1. Overview 1.5 Pin Assignments Figures 1.6 and 1.7 show the Pin Assignments (top view). /RxD /TA0 /SCL /CLK /CLK /TA1 /V/RxD /CTS /RTS /TA1 /V/TxD /TA2 /TA2 /TA3 /TA3 /TA4 /TA4 /INT /INT /INT NOTE: 1. Set PACR2 to PACR0 bit in the PACR register to "100 "...
Page 31 1. Overview Table 1.11 Pin Characteristics for 48-Pin Package page 12...
Page 32 1. Overview /TB1 /TB0 /CLK /INT /IDV /INT /IDW COUT /INT /IDU RESET /CTS /RTS /CTS /CLKS /CLK /RxD /TxD /TxD /SDA /TA0 /CTS /RTS /CTS /CLKS /NMI/SD /INT /RxD /SCL /TA0 /CLK /INT /CLK /TA1 /V/RxD /INT /CTS /RTS /TA1 /V/TxD /TA4...
Page 33 1. Overview Table 1.12 Pin Characteristics for 42-Pin Package page 14...
Page 34 1. Overview 1.6 Pin Description Table 1.13 Pin Description (48-Pin and 42-Pin Packages) Classification Pin Name I/O Type Description Power Supply Apply 0V to the Vss pin. Apply following voltage to the Vcc pin. 2.7 to 5.5 V (M16C/26A, M16C/26B), 3.0 to 5.5 V (M16C/26T T-ver.), 4.2 to 5.5 V (M16C/26T V-ver.) Analog Power Supplies power to the A/D converter.
Page 35 1. Overview Table 1.13 Pin Description ( 48-pin packages only) (Continued) Classification Pin Name I/O Type Description _________ Serial I/O CTS0 Inputs pin to control data transmission _________ RTS0 Output pin to control data reception CLK0 Inputs and outputs the transfer clock RxD0 Inputs serial data TxD0...
Page 36 2. CPU 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised of seven registers (R0, R1, R2, R3, A0, A1 and FB) out of 13 registers. There are two sets of register bank. b8 b7 R0H(R0's high bits) R0L(R0's low bits)
Page 37 2. CPU 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed.
Page 38 All blank spaces within SFR location are reserved and cannot be accessed by users. The special page vectors are allocated addresses FFE00 to FFFDB . They are used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication M16C/60 and M16C/20 Series Soft- ware Manual for details. 00000 FFE00...
Page 39 4. SFRs 4. Special Function Registers (SFRs) Table 4.1 SFR Information(1) Register Symbol After reset Address 0000 0001 0002 0003 Processor mode register 0 0004 Processor mode register 1 00001000 0005 System clock control register 0 01001000 0006 01101000 2(M16C/26T) System clock control register 1 00100000 0007...
Page 40 4. SFRs Table 4.2 SFR Information(2) Address Register Symbol After reset 0040 0041 0042 0043 INT3 interrupt control register INT3IC XX00X000 0044 0045 0046 0047 INT5 interrupt control register INT5IC XX00X000 0048 INT4 interrupt control register INT4IC XX00X000 0049 UART2 Bus collision detection interrupt control register BCNIC XXXXX000 004A...
Page 41 4. SFRs Table 4.3 SFR Information(3) Address Register Symbol After reset 0080 0081 0082 0083 0084 0085 0086 01B0 01B1 01B2 Flash memory control register 4 FMR4 01000000 01B3 01B4 01B5 Flash memory control register 1 FMR1 000XXX0X 01B6 01B7 Flash memory control register 0 FMR0 01B8...
Page 42 4. SFRs Table 4.4 SFR Information(4) Address Register Symbol After reset 0340 0341 Timer A1-1 register TA11 0342 0343 0344 Timer A2-1 register TA21 0345 Timer A4-1 register TA41 0346 0347 Three phase PWM control register 0 INVC0 0348 Three phase PWM control register 1 INVC1 0349 034A...
Page 43 4. SFRs Table 4.5 SFR Information(5) Address Register Symbol After reset Count start flag TABSR 0380 0381 Clock prescaler reset flag CPSRF 0XXXXXXX One-shot start flag ONSF 0382 0383 Trigger select register TRGSR Up-dowm flag 0384 0385 Timer A0 register 0386 0387 Timer A1 register...
Page 44 4. SFRs Table 4.6 SFR Information(6) Address Register Symbol After Reset A/D register 0 XXXXXXXX 03C0 XXXXXXXX 03C1 A/D register 1 XXXXXXXX2 03C2 XXXXXXXX 03C3 A/D register 2 XXXXXXXX 03C4 XXXXXXXX 03C5 A/D register 3 XXXXXXXX 03C6 XXXXXXXX 03C7 A/D register 4 XXXXXXXX 03C8 XXXXXXXX...
Page 45: Reset
5. Reset 5. Reset There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla- tion stop detection reset. 5.1 Hardware Reset There are two types of hardware resets: a hardware reset 1 and a hardware reset 2. 5.1.1 Hardware Reset 1 ____________ ____________...
Page 46: Software Reset
5. Reset Recommended operating voltage RESET RESET Equal to or less Equal to or less than 0.2V than 0.2V More than td(ROC) + td(P-R) Figure 5.1.1.1. Example Reset Circuit 5.2 Software Reset When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized.
Page 47 5. Reset td(P-R) More than td(ROC) RESET CPU clock 28 cycles CPU clock FFFFC Content of reset vector Address FFFFE Figure 5.1.1.2. Reset Sequence ____________ Table 5.1.1.1. Pin Status When RESET Pin Level is “L” Status Pin name P1, P6 to P10 Input port (high impedance) 0000 Data register(R0)
Page 48: Voltage Detection Circuit
5. Reset 5.5 Voltage Detection Circuit Note =5 V is assumed. Voltage Detection Circuit is not available in M16C/26T. The voltage detection circuit has circuits to monitor the input voltage at the V pin, each checking the input voltage with respect to Vdet3, and Vdet4, respectively. Use the VC26 to VC27 bits in the VCR2 register to select whether or not to enable these circuits.
Page 49 5. Reset V o l t a g e d e t e c t i o n r e g i s t e r 1 S y m b o l A d d r e s s A f t e r r e s e t ( 2) 0 0 0 0 0 0 0...
Page 50 5. Reset 5.0V 5.0V Vdet4 Vdet3r Vdet3 Vdet3s RESET Internal Reset Signal VC13 bit in Indefinite VCR1 register Set to “1” by program (reset level detect circuit enable) VC26 bit in Indefinite VCR2 register Set to “1” by program (voltage down detect circuit enable) VC27 bit in Indefinite VCR2 register...
Page 51: Voltage Down Detection Interrupt
5. Reset 5.5.1 Voltage Down Detection Interrupt If the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled), the voltage down detection interrupt request is generated when the voltage applied to the VCC pin crosses the Vdet4 voltage level.
Page 52 5. Reset Voltage down detection interrupt generation circuit DF1, DF0 The D42 bit is set to “0” (not detected) by program. the VC27 bit is set to “0” Voltage Down Detection Circuit (voltage down detect circuit disabled), the D42 bit is set to “0”. D4INT clock(the clock with which it VC27...
Page 53: Limitations On Exiting Stop Mode
5. Reset 5.5.2 Limitations on Exiting Stop Mode The voltage down detection interrupt is immediately generated and the microcomputer exits stop mode if the CM10 bit in the CM1 register is set to “1” under the conditions below. • the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled), •...
Page 54: Processor Mode
6. Processor Mode 6. Processor Mode The microcomputer supports single-chip mode only. Figures 6.1 and 6.2 show the associated registers. Processor Mode Register 0 Symbol Address After Reset 0004 Bit Symbol Bit Name Function Reserved bit Set to "0" (b2-b0) The microcomputer is reset when PM03 Software reset bit...
Page 55 6. Processor Mode Processeor Mode Register 2 Symbol Address After Reset 001E XXX00000 Bit Symbol Bit Name Function Specifying wait when 0: 2 wait PM20 accessing SFR during PLL 1: 1 wait operation 0: Clock is protected by PRCR PM21 (3,4) register System clock protective bit...
Page 56 6. Processor Mode The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and periph- eral bus. Figure 6.3 shows the block diagram of the internal bus. CPU address bus Memory address bus CPU data bus...
Page 57: Clock Generation Circuit
7. Clock Generation Circuit 7. Clock Generation Circuit The clock generation circuit contains four oscillator circuits as follows: (1) Main clock oscillation circuit (2) Sub clock oscillation circuit (3) On-chip oscillator (available at reset, oscillation stop detect function) (4) PLL frequency synthesizer Table 7.1 lists the clock generation circuit specifications.
Page 58 7. Clock Generation Circuit PCLK5=0,CM01-CM00=00 I/O ports PCLK5=0,CM01-CM00=01 Sub-clock generating circuit PCLK5=1, PCLK5=0, CM01-CM00=00 COUT PCLK5=0, CM01-CM00=10 CM01-CM00=11 1/32 CM04 PCLK0=1 Sub-clock PCLK0=0 On-chip CM21 oscillator clock Oscillation 1SIO stop, re- PCLK1=1 oscillation 2SIO detection PCLK1=0 circuit 8SIO CM10=1(stop mode) frequency 32SIO synthesizer...
Page 59 7. Clock Generation Circuit System clock control register 0 Symbol Address After reset 0006 01001000 (M16C/26A, M16C/26B) 01101000 (M16C/26T) Bit symbol Bit name Function CM00 Clock output function Refer to Table 7.5.3.1 Function of the CLKout pin select bit CM01 WAIT peripheral function 0 : Do not stop peripheral function clock in wait mode CM02...
Page 60 7. Clock Generation Circuit System clock control register 1 (1) Symbol Address After reset 0007 00100000 Bit symbol Bit name Function All clock stop control bit 0 : Clock on CM10 (4, 6) 1 : All clocks off (stop mode) System clock select bit 1 0 : Main clock CM11...
Page 61 7. Clock Generation Circuit Oscillation stop detection register (1) Symbol Address After reset 000C 0X000010 (11) Bit symbol Bit name Function 0: Oscillation stop, re-oscillation Oscillation stop, re- CM20 oscillation detection bit detection function disabled 1: Oscillation stop, re-oscillation (7, 9, 10, 11) detection function enabled System clock select bit 2 0: Main clock or PLL clock...
Page 62 7. Clock Generation Circuit Peripheral Clock Select Register Symbol Address After Reset PCLKR 025E 00000011 0 0 0 Bit Symbol Bit Name Function Timers A, B clock select bit (Clock source for the timers A, 0: f PCLK0 B, the timer S, the dead timer, 1: f SI/O3, SI/O4 and multi-master C bus)
Page 63 7. Clock Generation Circuit PLL control register 0 (1, 2) Symbol Address After reset PLC0 001C 0001 X010 Bit name Function symbol b1b0 PLL multiplying factor PLC00 0 0 0: Do not set select bit 0 0 1: Multiply by 2 0 1 0: Multiply by 4 0 1 1: PLC01...
Page 64: Main Clock
7. Clock Generation Circuit The following describes the clocks generated by the clock generation circuit. 7.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the X and X pins.
Page 65: Sub Clock
7. Clock Generation Circuit 7.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. The sub clock oscillator circuit is configured by connecting a crystal resonator between the X and X COUT...
Page 66: On-Chip Oscillator Clock
7. Clock Generation Circuit 7.3 On-chip Oscillator Clock This clock is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to 10.1 Count source protective mode).
Page 67 7. Clock Generation Circuit START Set the CM07 bit to “0” (main clock), the CM17 to CM16 bits to “00 ”(main clock undivided), and the CM06 bit to “0” (CM16 and CM17 bits enabled). Set the PLC02 to PLC00 bits (multiplying factor). (To select a 16 MHz <...
Page 68: Cpu Clock And Peripheral Function Clock
7. Clock Generation Circuit 7.5 CPU Clock and Peripheral Function Clock The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the periph- eral functions. 7.5.1 CPU Clock This is the operating clock for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the PLL clock.
Page 69: Power Control
7. Clock Generation Circuit 7.6 Power Control There are three power control modes. For convenience’ sake, all modes other than wait and stop modes are referred to as normal operation mode here. 7.6.1 Normal Operation Mode Normal operation mode is further classified into seven modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating.
Page 70: Wait Mode
7. Clock Generation Circuit 7.6.1.6 On-chip Oscillator Mode The selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, f can be used as the count source for timers A and B.
Page 71 7. Clock Generation Circuit 7.6.2.3 Pin Status During Wait Mode Table 7.6.2.3.1 lists pin status during wait mode. Table 7.6.2.3.1 Pin Status in Wait Mode Status I/O ports Retains status before wait mode When fC selected Does not stop Does not stop when the CM02 bit is set to “0”. When f1, f8, f32 selected Retains status before wait mode when the CM02 bit is set to “1”.
Page 72: Stop Mode
7. Clock Generation Circuit 7.6.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode.
Page 73 7. Clock Generation Circuit Figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. Figure 7.6.1.1 shows the state transition in normal operation mode. Table 7.6.1 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line shows state after transition.
Page 74 7. Clock Generation Circuit Main clock oscillation On-chip oscillator clock oscillation On-chip oscillator low power Middle-speed mode Middle-speed mode Middle-speed mode Middle-speed mode PLL operation mode On-chip oscillator mode PLC07=1 dissipation mode (divide by 4) High-speed mode (divide by 2) (divide by 8) (divide by 16) CM11=1...
Page 75 7. Clock Generation Circuit Table 7.6.1. Allowed Transition and Setting State after transition On-chip oscillator High-speed mode, Low power PLL operation On-chip oscillator Low-speed mode 2 low power Stop mode mode 2 Wait mode mode middle-speed mode dissipation mode dissipation mode High-speed mode, (9) 7 (13) 3...
Page 76: System Clock Protective Function
7. Clock Generation Circuit 7.7 System Clock Protective Function When the main clock is selected for the CPU clock source, this function protects the clock from modifica- tions in order to prevent the CPU clock from becoming halted by run-away. If the PM21 bit in the PM2 register is set to “1”...
Page 77: Operation When The Cm27 Bit Is Set To "0" (Oscillation Stop Detection Reset)
7. Clock Generation Circuit 7.8.1 Operation When the CM27 bit is set to "0" (Oscillation Stop Detection Reset) When main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4. SFR, 5.
Page 78: How To Use Oscillation Stop And Re-Oscillation Detect Function
7. Clock Generation Circuit 7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter- rupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
Page 79: Protection
8. Protection 8. Protection Note The PRC3 bit in the PRCR register is not available in M16C/26T. In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
Page 80: Interrupt
9. Interrupt 9. Interrupt Note The 42-pin package does not use UART0 transmission interrupt and UART0 reception interrupt of peripheral function. M16C/26T does not use voltage down detection interrupt. 9.1 Type of Interrupts Figure 9.1.1 shows types of interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction...
Page 81: Software Interrupts
9. Interrupt 9.1.1 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 9.1.1.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 9.1.1.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the opera- tion resulted in an overflow).
Page 82: Hardware Interrupts
9. Interrupt 9.1.2 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 9.1.2.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 9.1.2.1.1 NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details _______ _______ about the NMI interrupt, refer to the section 9.7 NMI Interrupt.
Page 83: Interrupts And Interrupt Vector
9. Interrupt 9.2 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector.
Page 84: Relocatable Vector Tables
9. Interrupt 9.2.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 9.2.2.1 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses.
Page 85: Interrupt Control
9. Interrupt 9.3 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and the ILVL2 to ILVL0 bits in the each interrupt control register to enable/disable the maskable interrupts.
Page 86 9. Interrupt Interrupt control register Symbol Address After reset BCNIC 004A XXXXX000 DM0IC, DM1IC 004B , 004C XXXXX000 KUPIC 004D XXXXX000 ADIC 004E XXXXX000 S0TIC to S2TIC 0051 , 0053 , 004F XXXXX000 S0RIC to S2RIC 0052 , 0054 , 0050 XXXXX000 TA0IC to TA4IC 0055...
Page 87 9. Interrupt Interrupt request cause select register Symbol Address After reset IFSR 035F Bit symbol Bit name Function IFSR0 INT0 interrupt polarity 0 : One edge switching bit 1 : Both edges IFSR1 INT1 interrupt polarity 0 : One edge switching bit 1 : Both edges IFSR2...
Page 88: I Flag
9. Interrupt 9.3.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts. 9.3.2 IR Bit The IR bit is set to “1”...
Page 89: Interrupt Sequence
9. Interrupt 9.4 Interrupt Sequence An interrupt sequence (the devicebehavior from the instant an interrupt is accepted to the instant the inter- rupt routine is executed) is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
Page 90: Interrupt Response Time
9. Interrupt 9.4.1 Interrupt Response Time Figure 9.4.1.1 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes the time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of the time from when an interrupt request is generated till when the instruction then executing is completed ((a) in Figure 9.4.1.1) and the time during which the interrupt sequence is executed ((b) in Figure 9.4.1.1).
Page 91: Saving Registers
9. Interrupt 9.4.3 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first.
Page 92 9. Interrupt The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP at the time of acceptance of an interrupt request, is even or odd. If the stack pointer is even, the FLG register and the PC are saved, 16 bits at a time.
Page 93: Returning From An Interrupt Routine
9. Interrupt 9.4.4 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt se- quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
Page 94 9. Interrupt Priority level of each interrupt Level 0 (initial value) Highest INT1 Timer B2 Timer B0 Timer A3 Timer A1 INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 UART1 reception UART0 reception Priority of peripheral function interrupts (if priority levels are same) UART2 reception, ACK2 A/D conversion DMA1...
Page 95 9. Interrupt ______ 9.6 INT Interrupt _______ INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in the IFSR register. ________ ________ ________ To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to "1" (=INT4). To use the INT5 interrupt, set ________ the IFSR7 bit in the IFSR register to "1"...
Page 96: Key Input Interrupt
9. Interrupt ______ 9.7 NMI Interrupt _______ _______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the _______ ______ NMI interrupt was enabled by writing a “1” to PM24 bit in the PM2 register. The NMI interrupt is a non- maskable interrupt, once it is enabled.
Page 97: Address Match Interrupt
9. Interrupt 9.9 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the ad- dress indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi register.
Page 98 9. Interrupt Address match interrupt enable register Symbol Address After reset AIER 0009 XXXXXX00 Bit symbol Bit name Function Address match interrupt 0 AIER0 0 : Interrupt disabled enable bit 1 : Interrupt enabled AIER1 Address match interrupt 1 0 : Interrupt disabled enable bit 1 : Interrupt enabled Nothing is assigned.
Page 99: Watchdog Timer
10. Watchdog Timer 10. Watchdog Timer The watchdog timer is the function that detects when a program is out of control. Use the watchdog timer is recommended to improve reliability of the system. The watchdog timer contains a 15-bit counter which is decremented by the CPU clock that the prescaler divides.
Page 100: Count Source Protective Mode
10. Watchdog Timer Watchdog Timer Control Register Symbol Address After Reset 000F 00XXXXXX Bit Symbol Bit Name Function (b4-b0) High-order bit of watchdog timer Reserved bit Set to “0” (b6-b5) 0: Divided by 16 WDC7 Prescaler select bit 1: Divided by 128 Watchdog Timer Start Register Symbol Address...
Page 101: Dmac
11. DMAC 11. DMAC Note Do not use UART0 transfer and UART0 reception interrupt request as a DMA request in the 42-pin package. The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address.
Page 102 11. DMAC Table 11.1 DMAC Specifications Item Specification No. of channels 2 (cycle steal method) Transfer memory space • From any address in the 1M bytes space to a fixed address • From a fixed address to any address in the 1M bytes space •...
Page 103 11. DMAC DMA0 request cause select register Symbol Address After reset DM0SL 03B8 Bit symbol Bit name Function DSEL0 DMA request cause Refer to note select bit DSEL1 DSEL2 DSEL3 Nothing is assigned. When write, set to “0”. When read, its content is “0”. (b5-b4) DMA request cause 0: Basic cause of request...
Page 104 11. DMAC DMA1 request cause select register Symbol Address After reset DM1SL 03BA Bit name Function Bit symbol DSEL0 DMA request cause Refer to note select bit DSEL1 DSEL2 DSEL3 Nothing is assigned. When write, set to “0”. (b5-b4) When read, its content is “0”. DMA request cause 0: Basic cause of request expansion select bit...
Page 105 11. DMAC DMAi source pointer (i = 0, 1) (b19) (b16)(b15) (b8) (b23) b0 b7 b0 b7 Symbol Address After reset SAR0 0022 to 0020 Indeterminate SAR1 0032 to 0030 Indeterminate Setting range Function Set the source address of transfer 00000 to FFFFF Nothing is assigned.
Page 106: Transfer Cycles
11. DMAC 11.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer.
Page 107 11. DMAC (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address CPU clock Address Dummy CPU use Source Destination CPU use cycle RD signal WR signal Data Dummy Destination CPU use Source CPU use cycle...
Page 108: Dma Transfer Cycles
11. DMAC 11.2. DMA Transfer Cycles Any combination of even or odd transfer read and write adresses is possible. Table 11.2.1 shows the number of DMA transfer cycles. Table 11.2.2 shows the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No.
Page 109: Dma Enable
11. DMAC 11.3 DMA Enable When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register is “1”...
Page 110: Channel Priority And Dma Transfer Timing
11. DMAC 11.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are de- tected active in the same sampling period (one period from a falling edge to the next falling edge of CPU clock), the DMAS bit on each channel is set to “1”...
Page 111: Timer
12. Timer 12. Timer Note The TB2IN pin is not available in the 42-pin package. Do not use functions associated with the TB2IN pin. Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (three).
Page 112 12. Timer PCLK0 bit = "0" Clock prescaler • Main clock 1 or • PLL clock 1/32 PCLK0 bit = "1" • On-chip Reset Set the CPSR bit in the oscillator clock CPSRF register to “1” (= prescaler reset) 1 or Timer B2 overflow or underflow ( to Timer A count source) •...
Page 113: Timer A
12. Timer 12.1 Timer A Figure 12.1.1 shows a block diagram of the timer A. Figures 12.1.2 to 12.1.4 show registers related to the timer A. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function.
Page 114 12. Timer Timer Ai register (i= 0 to 4) (1) Symbol Address After reset (b15) (b8) 0387 , 0386 Indeterminate b0 b7 0389 , 0388 Indeterminate 038B , 038A Indeterminate 038D , 038C Indeterminate 038F , 038E Indeterminate Function Mode Setting range Timer Divide the count source by n + 1 where n =...
Page 115 12. Timer One-shot start flag Symbol Address After reset ONSF 0382 Bit symbol Bit name Function The timer starts counting by setting Timer A0 one-shot start flag TA0OS this bit to “1” while the TMOD1 to TA1OS Timer A1 one-shot start flag TMOD0 bits in the TAiMR register (i = 0 to 4) is set to ‘10 ’...
Page 116: Timer Mode
12. Timer 12.1.1. Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.1.1.1). Figure 1.2.1.1.1 shows TAiMR register in timer mode. Table 12.1.1.1. Specifications in Timer Mode Item Specification Count source Count operation • Down-count •...
Page 117: Event Counter Mode
12. Timer 12.1.2. Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 12.1.2.1 lists specifica- tions in event counter mode (when not processing two-phase pulse signal). Table 12.1.2.2 lists specifica- tions in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4).
Page 118 12. Timer Timer Ai mode register (i=0 to 4) (When not using two-phase pulse signal processing) Symbol Address After reset TA0MR to TA4MR 0396 to 039A Bit symbol Bit name Function TMOD0 Operation mode select bit b1 b0 0 1 : Event counter mode (1) TMOD1 0 : Pulse is not output Pulse output function...
Page 119 12. Timer Table 12.1.2.2. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4) Item Specification Count source • Two-phase pulse signals input to TAi or TAi pins (i = 2 to 4) Count operation •...
Page 120 12. Timer Timer Ai mode register (i=2 to 4) (When using two-phase pulse signal processing) Symbol Address After reset TA2MR to TA4MR 0398 to 039A Bit symbol Bit name Function TMOD0 b1 b0 Operation mode select bit 0 1 : Event counter mode TMOD1 To use two-phase pulse signal processing, set this bit to “0”.
Page 121 12. Timer 12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two- phase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal process- _______ ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Page 122: One-Shot Timer Mode
12. Timer 12.1.3. One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.1.3.1.) When the trigger occurs, the timer starts up and continues operating for a given period. Figure 12.1.3.1 shows the TAiMR register in one-shot timer mode.
Page 123 12. Timer Timer Ai mode register (i=0 to 4) Symbol Address After reset TA0MR to TA4MR to 039A Bit symbol Bit name Function TMOD0 b1 b0 Operation mode select bit 1 0 : One-shot timer mode TMOD1 Pulse output function 0 : Pulse is not output select bit pin functions as I/O port)
Page 124: Pulse Width Modulation (Pwm) Mode
12. Timer 12.1.4. Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.1.4.1). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 12.1.4.1 shows TAiMR register in pulse width modulation mode.
Page 125 12. Timer Timer Ai mode register (i= 0 to 4) Symbol Address After reset TA0MR to TA4MR 0396 to 039A Bit symbol Bit name Function TMOD0 b1 b0 Operation mode 1 1 : PWM mode select bit TMOD1 0: Pulse is not output (TAiOUT pin functions as I/O port) Pulse output funcion 1: Pulse is output (TAiOUT pin functions as a pulse output select bit...
Page 126 12. Timer 1 / f – 1) Count source “H” Input signal to “L” Trigger is not generated by this signal 1 / f “H” PWM pulse output from TA iOUT “L” “1” IR bit in the TAiIC register “0” : Frequency of count source Set to “0”...
Page 127: Timer B
12. Timer 12.2 Timer B Note The TB2 pin for Timer B2 is not available in 42-pin package. [Precautions when using Timer B2] • Event Counter Mode The external input signals cannot be counted. Set the TCK1 bit in the TB2MR register to “1”...
Page 128 12. Timer Timer Bi mode register (i=0 to 2) Symbol Address After reset TB0MR to TB2MR 039B to 039D 00XX0000 Bit symbol Function Bit name b1 b0 TMOD0 Operation mode select bit 0 0 : Timer mode or A/D trigger mode 0 1 : Event counter mode TMOD1 1 0 : Pulse period measurement mode,...
Page 129 12. Timer Timer Bi register (i=0 to 2)(1) Symbol Address After reset 0391 , 0390 Indeterminate (b15) (b8) b0 b7 0393 , 0392 Indeterminate 0395 , 0394 Indeterminate Function Mode Setting range Timer mode Divide the count source by n + 1 0000 to FFFF where n = set value...
Page 130: Timer Mode
12. Timer 12.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.2.1.1). Figure 12.2.1.1 shows TBiMR register in timer mode. Table 12.2.1.1 Specifications in Timer Mode Item Specification Count source Count operation • Down-count •...
Page 131: Event Counter Mode
12. Timer 12.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 12.2.2.1) . Figure 12.2.2.1 shows TBiMR register in event counter mode. Table 12.2.2.1 Specifications in Event Counter Mode Item Specification Count source...
Page 132: Pulse Period And Pulse Width Measurement Mode
12. Timer 12.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 12.2.3.1). Figure 12.2.3.1 shows TBiMR register in pulse period and pulse width measurement mode.
Page 133 12. Timer Count source “H” Measurement pulse “L” Transfer Transfer (indeterminate value) (measured value) Reload register counter transfer timing Timing at which counter reaches “0000 ” “1” TBiS bit “0” IR bit in the TBiIC “1” register “0” Set to “0” upon accepting an interrupt request or by writing in program “1”...
Page 134: A/D Trigger Mode
12. Timer 12.2.4 A/D Trigger Mode A/D trigger mode is used as conversion start trigger for A/D converter in simultaneous sample sweep mode of A/D conversion or delayed trigger mode 0. This mode is used as conversion start trigger of A/D converter.
Page 135 12. Timer Timer Bi mode register (i= 0 to 1) Symbol Address After reset TB0MR to TB1MR 039B to 039C 00XX0000 Bit symbol Bit name Function TMOD0 b1 b0 Operation Mode Select Bit 0 0 : Timer mode or A/D trigger mode TMOD1 Invalid in A/D trigger mode Either "0"...
Page 136: Three-Phase Motor Control Timer Function
12. Timer 12.3 Three-phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.3.1 lists the specifications of the three-phase motor control timer function. Figure 12.3.1 shows the block diagram for three-phase motor control timer function.
Page 137 12. Timer Figure 12.3.1. Three-phase Motor Control Timer Functions Block Diagram page 118...
Page 138 12. Timer Three-phase PWM control register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset INVC0 0348 Bit symbol Bit name Description Effective interrupt output 0: The ICTB2 counter is incremented by INV00 polarity select bit one on the rising edge of the timer A1 reload control signal 1: The ICTB2 counter is incremented by...
Page 139 12. Timer Three-phase PWM control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset INVC1 0349 Bit symbol Bit name Description Timer A1, A2, A4 start 0: Timer B2 underflow INV10 trigger signal select bit 1: Timer B2 underflow and write to the TB2 register Timer A1-1, A2-1, A4-1...
Page 140 12. Timer Three-phase output buffer register(i=0,1) Symbol Address When reset IDB0 034A 00111111 IDB1 034B 00111111 Bit symbol Bit name Function Write the output level U phase output buffer i 0: Active level 1: Inactive level DUBi U phase output buffer i When read, these bits show the three-phase V phase output buffer i output shift register value.
Page 141 12. Timer (1, 2, 3, 4, 5) Timer Ai, Ai-1 register (i=1, 2, 4) Symbol Address After reset 0389 -0388 Indeterminate 038B -038A Indeterminate (b15) (b8) 038F -038E Indeterminate b0 b7 (6,7) TA11 0343 -0342 Indeterminate (6,7) TA21 0345 -0344 Indeterminate (6,7) TA41...
Page 142 12. Timer Timer B2 Special Mode Register Symbol Address After Reset TB2SC 039E X0000000 Bit Symbol Bit Name Function Timer B2 reload timing PWCON 0: Timer B2 underflow switch bit 1: Timer A output at odd-numbered Three-phase output port 0: Three-phase output forcible cutoff by SD pin input IVPCR1 SD control bit 1 (high impedance) disabled...
Page 143 12. Timer Timer B2 register Symbol Address After reset (b15) (b8) 0395 to 0394 Indeterminate b0 b7 Function Setting range 0000 to FFFF Divide the count source by n + 1 where n = set value. Timer A1, A2 and A4 are started at every occurrence of underflow.
Page 144 12. Timer Timer Ai mode register Symbol Address After reset b7 b6 b5 b4 b3 b2 b1 b0 TA1MR 0397 TA2MR 0398 TA4MR 039A Bit symbol Bit name Function TMOD0 Must set to “10 ” (one-shot timer mode) for Operation mode the three-phase motor control timer function select bit TMOD1...
Page 145 12. Timer The three-phase motor control timer function is enabled by setting the INV02 bit in the VC0 register to “1”. When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to control three-phase PWM outputs (U, U, V, V, W and W).
Page 146 12. Timer Carrier wave: sawtooth waveform Carrier wave Signal wave Timer B2 Start trigger signal for timer A4* Timer A4 one-shot pulse* Rewriting IDB0, IDB1 registers Transfer to three-phase output shift register U phase output signal * U phase output signal * U phase INV14 = 0 Dead time...
Page 147: Position-Data-Retain Function
12. Timer 12.3.1 Position-data-retain Function This function is used to retain the position data synchronously with the three-phase waveform output.There are three position-data input pins for U, V, and W phases. A trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected by the retain-trigger polarity select bit(bit 3 of the position-data-retain function control register, at address 034E ).
Page 148 12. Timer 12.3.1.2 Position-data-retain Function Control Register Figure 12.3.1.2.1 shows the structure of the position-data-retain function contol register. Position-data-retain function control register Symbol Address When reset PDRF 034E XXXX 0000 Bit symbol Bit name Function Input level at pin IDW is read out. W-phase position PDRW 0: "L"...
Page 149: Three-Phase/Port Output Switch Function
12. Timer 12.3.2 Three-phase/Port Output Switch Function When the INVC03 bit in the INVC0 register set to “1”(Timer output enabled for three-phase motor control) and setting the PFCi (i=0 to 5) in the PFCR register to “0”(I/O port), the three-phase PWM output pin (U, U, V, V, W and W) functions as I/O port.
Page 150 12. Timer Port function control register Symbol Address When reset PFCR 0358 0011 1111 Bit symbol Bit name Function 0: Input/Output port P8 Port P8 output PFC0 1: Three-phase PWM output function select bit (U phase output) 0: Input/Output port P8 Port P8 output PFC1...
Page 151: Serial I/O
13. Serial I/O 13. Serial I/O Note UART0 is not available in the 42-pin package. Serial I/O is configured with three channels: UART0 to UART2. 13.1. UARTi (i=0 to 2) UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Page 152 13. Serial I/O PCLK1=0 2SIO 1SIO or 2SIO Main clock, PLL clock, 1SIO or on-chip oscillator clock PCLK1=1 8SIO 32SIO (UART0) SMD2 to SMD0 UART reception Clock source selection Receive 1/16 Reception clock CLK1 to CLK0 Clock synchronous control circuit Transmit/ type U0BRG...
Page 153 13. Serial I/O Clock synchronous type Clock synchronous UART (7 bits) UART (7 bits) type disabled UART (8 bits) UARTi receive register STPS=0 PRYE=0 RxDi STPS=1 PRYE=1 UART enabled UART (9 bits) SMD2 to SMD0 Clock synchronous type UART (8 bits) UART (9 bits) UARTi receive buffer register...
Page 154 13. Serial I/O No reverse IOPOL=0 RxD data RxD2 reverse circuit IOPOL=1 Reverse Clock synchronous type UART Clock (7 bits) synchronous UART(7 bits) disabled type UART UARTi receive register (8 bits) STPS=0 PRYE=0 STPS=1 PRYE=1 UART Clock enabled synchronous type SMD2 to SMD0 UART UART...
Page 155 13. Serial I/O UARTi Transmit Buffer Register (i=0 to 2) Symbol Address After Reset (b15) (b8) U0TB 03A3 -03A2 Indeterminate U1TB 03AB -03AA Indeterminate U2TB 037B -037A Indeterminate Function Transmit data Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1.
Page 156 13. Serial I/O UARTi transmit/receive mode register (i = 0, 1) Symbol Address After reset U0MR, U1MR 03A0 , 03A8 Function Bit name symbol SMD0 b2 b1 b0 Serial I/O mode select bit 0 0 0 : Serial I/O disabled 0 0 1 : Clock synchronous serial I/O mode 1 0 0 : UART mode transfer data 7 bits long SMD1...
Page 157 13. Serial I/O UARTi Transmit/receive Control Rregister 0 (i=0 to 2) Symbol Address After Reset U0C0 to U2C0 03A4 , 03AC , 037C 00001000 Bit Name Function Symbol b1 b0 CLK0 BRG count source 0 0 : f or f is selected 1SIO 2SIO...
Page 158 13. Serial I/O UARTi Transmit/receive Control Register 1 (i=0, 1) Symbol Address After Reset U0C1, U1C1 03A5 ,03AD 00000010 Function Bit Name Symbol Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled Transmit buffer 0 : Data in UiTB register empty flag 1 : No data in UiTB register Receive enable bit...
Page 159 13. Serial I/O UART2 Special Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset U2SMR 0377 X0000000 Function Bit Name Symbol 0 : Other than I C bus mode IICM C bus mode select bit 1 : I C bus mode Arbitration lost detecting...
Page 160 13. Serial I/O UART2 special mode register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset U2SMR3 0375 000X0X0X Bit name Function symbol Nothing is assigned. (b0) When write, set “0”. When read, its content is indeterminate. CKPH Clock phase set bit 0 : Without clock delay...
Page 161: Clock Synchronous Serial I/O Mode
13. Serial I/O 13.1.1. Clock Synchronous serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 13.1.1.1 lists the specifications of the clock synchronous serial I/O mode. Table 13.1.1.2 lists the registers used in clock synchronous serial I/O mode and the register values set.
Page 162 13. Serial I/O Table 13.1.1. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Function UiTB 0 to 7 Set transmission data UiRB 0 to 7 Reception data can be read Overrun error flag UiBRG 0 to 7 Set a transfer rate UiMR...
Page 163 13. Serial I/O Table 13.1.1.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 13.3 shows pin functions for the case where the multiple transfer clock output pin select function is dese- lected. Table 13.1.1.4 lists the P6 pin functions during clock synchronous serial I/O mode.
Page 164 13. Serial I/O (1) Example of Transmit Timing (Internal clock is selected) Transfer clock “1” UiC1 register “0” Write data to the UiTB register TE bit “1” UiC1 register TI bit “0” Transferred from UiTB register to UARTi transmit register “H”...
Page 165 13. Serial I/O 13.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below. •Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to “0” (reception disabled) (2) Set the SMD2 to SMD0 bits in the UiMR register to “000 ”...
Page 166 13. Serial I/O 13.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 13.1.1.3.1 shows the transfer format. (1) When the UFORM bit in the UiC0 register "0" (LSB first) (2) When the UFORM bit in the UiC0 register is set to "1"...
Page 167 13. Serial I/O 13.1.1.5 Serial data logic switch function (UART2) When the U2LCH bit in the U2C1 register is set to "1" (reverse), the data written to the U2TB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the U2RB register.
Page 168 13. Serial I/O _______ _______ 13.1.1.7 CTS/RTS separate function (UART0) _______ _______ _______ _______ This function separates CTS /RTS , outputs RTS from the P6 pin, and accepts as input the CTS from the P6 pin. To use this function, set the register bits as shown below. _______ _______ •...
Page 169: Clock Asynchronous Serial I/O (Uart) Mode
13. Serial I/O 13.1.2. Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 13.1.2.1 lists the specifications of the UART mode. Table 13.1.2.1. UART Mode Specifications Item Specification Transfer data format...
Page 170 13. Serial I/O Table 13.1.2.2. Registers to Be Used and Settings in UART Mode Register Function UiTB 0 to 8 Set transmission data UiRB 0 to 8 Reception data can be read OER,FER,PER,SUM Error flag UiBRG 0 to 7 Set a transfer rate UiMR SMD2 to SMD0 Set these bits to ‘100...
Page 171 13. Serial I/O Table 13.1.2.3 lists the functions of the input/output pins during UART mode. Table 13.1.2.4 lists the P6 pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.) Table 13.1.2.3.
Page 172 13. Serial I/O • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to “L”. Transfer clock UiC1 register “1”...
Page 173 13. Serial I/O • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG count source “1” UiC1 register RE bit “0” Stop bit Start bit RxDi Sampled “L” Receive data taken in Transfer clock Read out from Reception triggered when transfer clock...
Page 174 13. Serial I/O 13.1.2.2. Counter Measure for Communication Error If a communication error occurs while transmitting or receiving in UART mode, follow the procedure below. • Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to “0” (reception disabled) (2) Set the RE bit in the UiC1 register to “1”...
Page 175 13. Serial I/O 13.1.2.4. Serial Data Logic Switching Function (UART2) The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the U2RB register. Figure 13.1.2.4.1 shows serial data logic.
Page 176 13. Serial I/O _______ _______ 13.1.2.6. CTS/RTS Separate Function (UART0) _______ _______ _______ _______ This function separates CTS /RTS , outputs RTS from the P6 pin, and accepts as input the CTS from the P6 pin. To use this function, set the register bits as shown below. _______ _______ •...
Page 177: Special Mode 1 (I 2 C Bus Mode)(Uart2)
13. Serial I/O 13.1.3 Special Mode 1 (I C bus mode)(UART2) C bus mode is provided for use as a simplified I C bus interface compatible mode. Table 13.1.3.1 lists the specifications of the I C bus mode. Table 13.1.3.2 and 13.1.3.3 list the registers used in the I C bus mode and the register values set.
Page 178 13. Serial I/O Start and stop condition generation block SDA2 DMA0, DMA1 request STSPSEL=1 STSP Delay circuit STSP STSPSEL=0 IICM2=1 Transmission UART2 transmit, register NACK interrupt ACKC=1 ACKC=0 request UART2 IICM=1 and IICM2=0 SDHI ACKD bit DMA0 Arbitration Noise Filter IICM2=1 UART2 receive, Reception register...
Page 179 13. Serial I/O Table 13.1.3.2. Registers to Be Used and Settings in I C bus Mode (1) (Continued) Register Function Master Slave U2TB 0 to 7 Set transmission data Set transmission data U2RB 0 to 7 Reception data can be read Reception data can be read ACK or NACK is set in this bit ACK or NACK is set in this bit...
Page 180 13. Serial I/O Table 13.1.3.3. Registers to Be Used and Settings in I C bus Mode (Continued) Register Function Master Slave U2SMR4 STAREQ Set this bit to “1” to generate start Set to “0” condition RSTAREQ Set this bit to “1” to generate restart Set to “0”...
Page 181 13. Serial I/O Table 13.1.3.4. I C bus Mode Functions Clock synchronous serial I/O C bus mode (SMD2 to SMD0 = 010 , IICM = 1) Function mode (SMD2 to SMD0 = 001 IICM2 = 0 IICM2 = 1 IICM = 0) (NACK/ACK interrupt) (UART transmit/ receive interrupt) CKPH = 1...
Page 182 13. Serial I/O (1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay) SCL2 (ACK or NACK) SDA2 ACK interrupt (DMA request) or NACK interrupt Data is transferred to the U2RB register •••...
Page 183 13. Serial I/O 13.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDA pin changes state from high to low while the SCL pin is in the high state.
Page 184 13. Serial I/O Table 13.1.3.2.1. STSPSEL Bit Functions Function STSPSEL = 0 STSPSEL = 1 Output of SCL2 and SDA2 pins Output transfer clock and data/ The STAREQ, RSTAREQ and Program with a port determines STPREQ bit determine how the how the start condition or stop start condition or stop condition is condition is output...
Page 185 13. Serial I/O 13.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 13.1.3.2.1. The CSC bit in the U2SMR2 register is used to synchronize the internally generated clock (internal SCL2) and an external clock supplied to the SCL pin.
Page 186 13. Serial I/O 13.1.3.7 ACK and NACK If the STSPSEL bit in the U2SMR4 register is set to “0” (start and stop conditions not generated) and the ACKC bit in the U2SMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the U2SMR4 register is output from the SDA pin.
Page 187: Special Mode 2 (Uart2)
13. Serial I/O 13.1.4 Special Mode 2 (UART2) Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 13.1.4.1 lists the specifications of Special Mode 2. Table 13.1.4.2 lists the registers used in Special Mode 2 and the register values set. Figure 13.1.4.1 shows communication control ex- ample for Special Mode 2.
Page 188 13. Serial I/O Microcomputer Microcomputer (Master) (Slave) Microcomputer (Slave) Figure 13.1.4.1. Serial Bus Communication Control Example (UART2) page 169...
Page 189 13. Serial I/O Table 13.1.4.2. Registers to Be Used and Settings in Special Mode 2 Register Function U2TB 0 to 7 Set transmission data U2RB 0 to 7 Reception data can be read Overrun error flag U2BRG 0 to 7 Set a transfer rate U2MR SMD2 to SMD0...
Page 190 13. Serial I/O 13.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the U2SMR3 register and the CKPOL bit in the U2C0 register. Make sure the transfer clock polarity and phase are the same for the master and slave to communi- cate.
Page 191 13. Serial I/O "H" Slave control input "L" "H" Clock input "L" (CKPOL=0, CKPH=0) Clock input "H" (CKPOL=1, CKPH=0) "L" "H" Data output timing "L" Data input timing Indeterminate Figure 13.1.4.1.2.1. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) "H"...
Page 192: Special Mode 3 (Ie Bus Mode )(Uart2)
13. Serial I/O 13.1.5 Special Mode 3 (IE Bus mode )(UART2) In this mode, one bit of IE Bus is approximated with one byte of UART mode waveform. Table 13.1.5.1 lists the registers used in IE Bus mode and the register values set. Figure 13.1.5.1 shows the functions of bus collision detect function related bits.
Page 193 13. Serial I/O (1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select) If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Transfer clock TxD2 RxD2 Input to TA0 Timer A0 If ABSCS is set to "1", bus collision is determined when timer A0 (one-shot timer mode) underflows (2) The ACSE bit in the U2SMR register (auto clear of transmit enable bit)
Page 194: Special Mode 4 (Sim Mode) (Uart2)
13. Serial I/O 13.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected. Tables 13.1.6.1 lists the specifications of SIM mode.
Page 195 13. Serial I/O Table 13.1.6.2. Registers to Be Used and Settings in SIM Mode Register Function U2TB 0 to 7 Set transmission data U2RB 0 to 7 Reception data can be read OER,FER,PER,SUM Error flag U2BRG 0 to 7 Set a transfer rate U2MR SMD2 to SMD0 Set to ‘101...
Page 196 13. Serial I/O (1) Transmit Timing Transfer Clock "1" TE bit in U2C1 Data is written to register "0" the UARTi register TI bit in U2C1 "1" register "0" Data is transferred from the U2TB register to the UART2 transmit Parity Stop register...
Page 197 13. Serial I/O Figure 13.1.6.2 shows the example of connecting the SIM interface. Connect T and R and apply pull-up. Microcomputer SIM card Figure 13.1.6.2. SIM Interface Connection 13.1.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register’ to “1”. •...
Page 198 13. Serial I/O 13.1.6.2 Format • Direct Format Set the PRY bit in the U2MR register to “1”, the UFORM bit in the U2C0 register to “0” and the U2LCH bit in the U2C1 register to “0”. • Inverse Format Set the PRY bit to “0”, UFORM bit to “1”...
Page 199: A/D Converter
14. A/D Converter 14. A/D Converter Note and P9 , AN ) are not available in the 42-pin package. Do not use P9 and P9 , AN ) as analog input pins in the 42-pin package. The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier.
Page 200 14. A/D Converter A/D conversion rate selection CKS1=1 CKS2=0 ø CKS0=1 CKS1=0 CKS0=0 CKS2=1 Resistor ladder VCUT=0 VCUT=1 Successive conversion register ADCON1 register (address 03D7 ADCON0 register (address 03D6 Addresses (03C1 to 03C0 A/D register 0(16) (03C3 to 03C2 A/D register 1(16) A/D register 2(16) (03C5 to 03C4...
Page 201 14. A/D Converter A/D control register 0 (1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog Input Pin Select Function varies with each operation mode b4 b3 A/D Operation Mode 0 0 : One-shot mode or Delayed trigger mode 0,1 Select Bit 0 0 1 : Repeat mode 1 0 : Single sweep mode or...
Page 202 14. A/D Converter (1,2) A/D trigger control register Symbol Address After reset ADTRGCON 03D2 Bit symbol Bit name Function 0 : Other than simultaneous sample sweep A/D Operation Mode mode or delayed trigger mode 0,1 Select Bit 2 1 : Simultaneous sample sweep mode or delayed trigger mode 0,1 0 : Other than delayed trigger mode 0,1 A/D Operation Mode...
Page 203 14. A/D Converter A/D conversion status register 0 (1) Symbol Address After reset ADSTAT0 03D3 Bit symbol Bit name Function AN1 Trigger Status Flag 0 : AN1 trigger did not occur during ADERR0 AN0 conversion 1 : AN1 trigger occured during AN0 conversion ADERR1 Conversion Termination...
Page 204 14. A/D Converter Timer B2 special mode register Symbol Address After reset TB2SC 039E X0000000 Bit symbol Bit name Function Timer B2 Reload Timing 0 : Timer B2 underflow PWCOM Switch Bit 1 : Timer A output at odd-numbered Three-Phase Output Port 0 : Three-phase output forcible cutoff IVPCR1 SD Control Bit 1...
Page 205: Operation Modes
14. A/D Converter 14.1 Operation Modes 14.1.1 One-Shot Mode In one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. Table 14.1.1.1 shows the one-shot mode specifications. Figure 14.1.1.1 shows the operation example in one- shot mode.
Page 206 14. A/D Converter A/D control register 0 (1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function b2 b1 b0 Analog Input Pin 0 0 0 : Select AN Select Bit (2, 3) 0 0 1 : Select AN 0 1 0 : Select AN 0 1 1 : Select AN 1 0 0 : Select AN...
Page 207: Repeat Mode
14. A/D Converter 14.1.2 Repeat mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 14.1.2.1 shows the repeat mode specifications. Figure 14.1.2.1 shows the operation example in repeat mode. Figure 14.1.2.2 shows the ADCON0 to ADCON2 registers in repeat mode. Table 14.1.2.1 Repeat Mode Specifications Item Specification...
Page 208 14. A/D Converter A/D control register 0 (1) Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function b2 b1 b0 Analog Input Pin 0 0 0 : Select AN Select Bit (2, 3) 0 0 1 : Select AN 0 1 0 : Select AN 0 1 1 : Select AN 1 0 0 : Select AN...
Page 209: Single Sweep Mode
14. A/D Converter 14.1.3 Single Sweep Mode In single sweep mode, analog voltages applied to the selected pins are converted one-by-one to a digital code. Table 14.1.3.1 shows the single sweep mode specifications. Figure 14.1.3.1 shows the operation example in single sweep mode. Figure 14.1.3.2 shows the ADCON0 to ADCON2 registers in single sweep mode.
Page 210 14. A/D Converter A/D control register 0 Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog Input Pin Invalid in single sweep mode Select Bit b4 b3 A/D Operation Mode 1 0 : Single sweep mode or simultaneous Select Bit 0 sample sweep mode Trigger Select Bit...
Page 211: Repeat Sweep Mode 0
14. A/D Converter 14.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltages applied to the selected pins are repeatedly converted to a digital code. Table 14.1.4.1 shows the repeat sweep mode 0 specifications. Figure 14.1.4.1 shows the operation example in repeat sweep mode 0.
Page 212 14. A/D Converter A/D control register 0 Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog Input Pin Invalid in repeat sweep mode 0 Select Bit b4 b3 A/D Operation Mode 1 1 : Repeat sweep mode 0 or Select Bit 0 Repeat sweep mode 1 0 : Software trigger...
Page 213: Repeat Sweep Mode 1
14. A/D Converter 14.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltages applied to the all selected pins are converted to a digital code, with mainly used in the selected pins. Table 14.1.5.1 shows the repeat sweep mode 1 specifications. Figure 14.1.5.1 shows the operation example in repeat sweep mode 1.
Page 214 14. A/D Converter A/D control register 0 Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog Input Pin Invalid in repeat sweep mode 1 Select Bit b4 b3 A/D Operation Mode 1 1 : Repeat sweep mode 0 or Select Bit 0 Repeat sweep mode 1 0 : Software trigger...
Page 215: Simultaneous Sample Sweep Mode
14. A/D Converter 14.1.6 Simultaneous Sample Sweep Mode In simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-by- one to a digital code. At this time, the input voltage of AN and AN are sampled simultaneously using two circuits of sample and hold circuit.
Page 216 14. A/D Converter A/D control register 0 Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function Analog Input Pin Invalid in simultaneous sample sweep mode Select Bit b4 b3 A/D Operation Mode 1 0 : Single sweep mode or simultaneous Select Bit 0 sample sweep mode Refer to Table 14.1.6.2 Trigger Select Bit...
Page 217 14. A/D Converter A/D trigger control register Symbol Address After reset ADTRGCON 03D2 Bit symbol Bit name Function 1 : Simultaneous sample sweep mode A/D Operation Mode or delayed trigger mode 0, 1 Select Bit 2 0 : Any mode other than delayed trigger A/D Operation Mode mode 0,1 Select Bit 3...
Page 218: Delayed Trigger Mode 0
14. A/D Converter 14.1.7 Delayed Trigger Mode 0 In delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a digital code. The delayed trigger mode 0 used in combination with A/D trigger mode of Timer B. The Timer B0 underflow starts a single sweep conversion.
Page 219 14. A/D Converter •Example when selecting AN to AN to analog input pins (SCAN1 to SCAN0=01 •Example 1: When Timer B1 underflow is generated during AN pin conversion A/D pin input voltage sampling Timer B0 underflow A/D pin conversion Timer B1 underflow •Example 2: When Timer B1 underflow is generated after AN pin conversion Timer B0 underflow...
Page 220 14. A/D Converter •Example when selecting AN to AN to analog input pins (SCAN1 to SCAN0=01 •Example 1: When Timer B1 underflow is generated during AN pin conversion A/D pin input voltage sampling Timer B0 underflow A/D pin conversion Timer B1 underflow "1"...
Page 221 14. A/D Converter •Example 3: When Timer B0 underflow is generated during A/D pin conversion of any pins except AN Timer B0 underflow A/D pin input Timer B0 underflow (Abort othrt pins conversion ) voltage sampling Timer B1 underflow Timer B1 underflow A/D pin conversion "1"...
Page 222 14. A/D Converter A/D control register 0 Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function b2 b1 b0 Analog Input Pin 1 1 1 : Set to "111b" in delayed trigger Select Bit mode 0 b4 b3 A/D Operation Mode 0 0 : One-shot mode or delayed trigger mode Select Bit 0...
Page 223 14. A/D Converter A/D trigger control register (1) Symbol Address After reset ADTRGCON 03D2 Bit symbol Bit name Function Simultaneous sample sweep mode or A/D Operation Mode delayed trigger mode 0,1 Select Bit 2 Delayed trigger mode 0, 1 A/D Operation Mode Select Bit 3 Refer to Table 14.1.7.2 Trigger Select AN0 Trigger Select Bit...
Page 224: Delayed Trigger Mode 1
14. A/D Converter 14.1.8 Delayed Trigger Mode 1 In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a digital code. When the input of the AD pin (falling edge) changes state from “H” to “L”, a single sweep conversion is started.
Page 225 14. A/D Converter •Example when selecting AN to AN to analog input pins (SCAN1 to SCAN0=01 •Example 1: When AD pin falling edge is generated during AN pin conversion A/D pin input voltage sampling A/D pin conversion pin input •Example 2: When AD pin falling edge is generated again after AN pin conversion pin input...
Page 226 14. A/D Converter •Example when selecting AN to AN to analog input pins (SCAN1 to SCAN0=01 •Example 1: When AD pin falling edge is generated during AN pin conversion A/D pin input voltage sampling A/D pin conversion pin input "1" ADST flag "0"...
Page 227 14. A/D Converter •Example 3: When AD input falling edge is generated more than two times after AN pin conversion A/D pin input voltage sampling A/D pin conversion pin input (valid after single sweep conversion) (invalid) "1" ADST flag "0" Do not set to "1"...
Page 228 14. A/D Converter A/D control register 0 Symbol Address After reset ADCON0 03D6 00000XXX Bit symbol Bit name Function b2 b1 b0 Analog Input Pin 1 1 1 : Set to "111b" in delayed trigger Select Bit mode 1 b4 b3 A/D Operation Mode 0 0 : One-shot mode or delayed trigger mode Select Bit 0...
Page 229 14. A/D Converter A/D trigger control register Symbol Address After reset ADTRGCON 03D2 Bit symbol Bit name Function Simultaneous sample sweep mode or A/D Operation Mode delayed trigger mode 0,1 Select Bit 2 Delayed trigger mode 0, 1 A/D Operation Mode Select Bit 3 Refer to Table 14.1.8.2 Trigger Select AN0 Trigger Select Bit...
Page 230: Resolution Select Function
14. A/D Converter 14.2 Resolution Select Function The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to “1” (10-bit precision), the A/D conversion result is stored into bits 0 to 9 in the A/D register i (i=0 to 7). When the BITS bit is set to “0”...
Page 231: Output Impedance Of Sensor Under A/D Conversion
14. A/D Converter 14.5 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 14.5.1 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output imped- ance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of the A/D converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
Page 232: Crc Calculation Circuit
15. CRC Calculation Circuit 15. CRC Calculation Circuit The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X + 1) or CRC-16 (X + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of bytes.
Page 233 15. CRC Calculation Circuit CRC Data Register (b15) (b8) Symbol Address After Reset b0 b7 CRCD 03BD to 03BC Undefined Function Setting Range CRC calculation result output 0000 to FFFF CRC Input Register Symbol Address After Reset CRCIN 03BE Undefined Function Setting Range Data input...
Page 234 15. CRC Calculation Circuit (1) Setting 0000 (initial value) CRD data register CRCD [03BD , 03BC (2) Setting 01 CRC input register CRCIN [03BE 2 cycles After CRC calculation is complete CRD data register CRCD 1189 [03BD , 03BC Stores CRC code The code resulting from sending 01 in LSB first mode is (10000 0000).This the CRC code in the generating polynomial, + 1), becomes the remainder resulting from dividing(1000 0000)X...
Page 235: Programmable I/O Ports
16. Programmable I/O Ports 16. Programmable I/O Ports Note to P6 , P9 and P9 are not available in the 42-pin package. The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 39 lines P1 , P6, P7, P8, P9 to P9 , P10 for the 48-pin package, or 33 lines P1 to P1...
Page 236: Port Control Register
16. Programmable I/O Ports 16.4 Port Control Register Figure 16.4.1 shows the port control register. When the P1 register is read after setting the PCR0 bit in the PCR register to “1”, the corresponding port latch can be read no matter how the PD1 register is set. 16.5 Pin Assignment Control register (PACR) Figure 16.5.1 shows the PACR.
Page 237 16. Programmable I/O Ports Pull-up selection Direction register to P10 Port latch Data bus Analog input Pull-up selection Direction register (inside dotted-line not included) , P1 Port P1 control register Data bus Port latch (inside dotted-line included) Input to respective peripheral functions Digital INPC1 /INT5...
Page 238 16. Programmable I/O Ports Pull-up selection Direction register to P7 "1" Output Port latch Data bus Switching between CMOS and Input to respective peripheral functions Pull-up selection Direction register to P8 Data bus Port latch Input to respective peripheral functions Pull-up selection Direction register , P6...
Page 239 16. Programmable I/O Ports Pull-up selection Direction register , P6 “1” Output Port latch Data bus Switching between CMOS and Nch Pull-up selection NMI Enable Direction register Data bus Port latch Digital Debounce NMI Interrupt Input NMI Enable Pull-up selection , P9 Direction register to P10...
Page 240 16. Programmable I/O Ports Pull-up selection (inside dotted-line included) Direction register (inside dotted-line not included) Output Data bus Port latch Analog input Input to respective peripheral functions Pull-up selection Direction register Data bus Port latch Pull-up selection Direction register Data bus Port latch NOTE: symbolizes a parasitic diode.
Page 241 16. Programmable I/O Ports signal input RESET RESET signal input NOTE: symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 16.5. I/O Pins page 222...
Page 242 16. Programmable I/O Ports Port Pi direction register (i=6 to 8, and 10) (1) Symbol Address After reset PD6 to PD8 03EE , 03EF , 03F2 PD10 03F6 Bit symbol Bit name Function PDi_0 Port Pi direction bit 0 : Input mode PDi_1 Port Pi direction bit...
Page 243 16. Programmable I/O Ports Port Pi register (i=6 to 8 and 10) Symbol Address After reset P6 to P8 03EC , 03ED , 03F0 Indeterminate 03F4 Indeterminate Bit symbol Bit name Function Pi_0 Port Pi The pin level on any I/O port which is set for input mode can be read by Pi_1 Port Pi...
Page 244 16. Programmable I/O Ports Pull-up control register 0 Symbol Address After reset PUR0 03FC Bit symbol Bit name Function Nothing is assigned. In an attempt to write to these bits, write (b2-b0) “0”. The value, if read, turns out to be “0”. 0 : Not pulled high PU03 to P1...
Page 245 16. Programmable I/O Ports Port control register Symbpl Address After reset 03FF Bit symbol Bit name Function PCR0 Port P1 control bit Operation performed when the P1 register is read 0: When the port is set for input, the input levels of P10 to P17 pins are read.
Page 246 16. Programmable I/O Ports (1,2) NMI Digital Debounce Register Symbol Address After Reset NDDR 033E Function Setting Range If the set value =n, - n = 0 to FE ; a signal with pulse width, greater than to FF (n+1)/f8, is input into NMI / SD - n = FF ;...
Page 247 16. Programmable I/O Ports Digital Debounce Filter Clock Port In Signal Out / P1 To NMI and SD / INT5 and INPC17 Reload Value Count Value Data Bus Data Bus (write) (read) Reload Value Port In Signal Out Count Value Reload Value (continued) Port In...
Page 248 16. Programmable I/O Ports Table 16.1. Unassigned Pin Handling in Single-chip Mode Pin name Connection After setting for input mode, connect every pin to V via a resistor(pull-down); Ports P1, P6 to P10 or after setting for output mode, leave these pins open. (1, 2, 4) Open Connect via resistor to V...
Page 249: Flash Memory Version
17. Flash Memory Version 17. Flash Memory Version 17.1 Flash Memory Performance The flash memory version is functionally the same as the mask ROM version except that it internally con- tains flash memory. In the flash memory version, the flash memory can perform in three rewrite mode : CPU rewrite mode, standard serial I/O mode and parallel I/O mode.
Page 250: Boot Mode
17. Flash Memory Version Table 17.2. Flash Memory Rewrite Modes Overview Flash memory CPU rewrite mode Standard serial I/O mode Parallel I/O mode rewrite mode Function The user ROM area is rewrit- The user ROM area is rewrit- The user ROM area is rewrit- ten when the CPU executes ten using a dedicated serial ten using a dedicated paral-...
Page 251: Memory Map
17. Flash Memory Version 17.2 Memory Map The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 17.2.1 to 17.2.3 show the flash memory block diagram. The user ROM area has space to store the microcomputer operation program in single-chip mode and a separate 2-Kbyte space as the block A and B.
Page 252 17. Flash Memory Version 00F000 B l o c k B : 2 K b y t e s (2) 00F7FF 00F800 B l o c k A : 2 K b y t e s (2) 00FFFF 0 F 4 0 0 0 B l o c k 3 : 1 6 K b y t e s (5) NOTES: 1.
Page 253 17. Flash Memory Version 0 0 F 0 0 0 B l o c k B : 2 K b y t e s (2) 0 0 F 7 F F 0 0 F 8 0 0 B l o c k A : 2 K b y t e s (2) 0 0 F F F F NOTES: 1.
Page 254: Functions To Prevent Flash Memory From Rewriting
17. Flash Memory Version 17.3 Functions To Prevent Flash Memory from Rewriting The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code check function for standard input/output mode to prevent the flash memory from reading or rewriting. 17.3.1 ROM Code Protect Function The ROM code protect function disables reading or changing the contents of the on-chip flash memory in parallel I/O mode.
Page 255 17. Flash Memory Version ROM Code Protect Control Address Symbol Address Factory Setting ROMCP 0FFFFF Bit Symbol Bit Name Function Set to 1 Reserved Bit (b5-b0) b7 b6 ROM Code Protect Level ROMCP1 1 Set Bit (1, 2, 3, 4) Enables protect 11: Disables protect NOTES:...
Page 256: Cpu Rewrite Mode
17. Flash Memory Version 17.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board without using a ROM programmer, etc.
Page 257: Ew0 Mode
17. Flash Memory Version 17.4.1 EW0 Mode The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled) and is ready to acknowledge the software commands. EW0 mode is selected by setting the FMR11 bit in the FMR1 register to “0”.
Page 258: Register Description
17. Flash Memory Version 17.5 Register Description Figure 17.5.1 shows the flash memory control register 0 and flash memory control register 1. Figure 17.5.2 shows the flash memory control register 4. 17.5.1 Flash memory control register 0 (FMR0) •FMR 00 Bit This bit indicates the operation status of the flash memory.
Page 259: Flash Memory Control Register 1 (Fmr1)
17. Flash Memory Version 17.5.2 Flash memory control register 1 (FMR1) •FMR11 Bit EW1 mode is entered by setting the FMR11 bit to “1” (EW1 mode). This bit is enabled only when the FMR01 bit is “1”. •FMR16 Bit The combined setting of the FMR02 bit and the FMR16 bit enables to program and erase in the user ROM area.
Page 260 17. Flash Memory Version Flash memory control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After reset FMR0 01B7 00000001 Bit name Function Bit symbol 0: Busy (during writing or erasing) RY/BY status flag FMR00 1: Ready CPU rewrite mode select bit 0: Disables CPU rewrite mode FMR01...
Page 261 17. Flash Memory Version Flash Memory Control Register 4 Symbol Address After Reset b7 b6 b5 b4 b3 b2 b1 b0 01B3 FMR4 01000000 Bit Name Function Bit Symbol Erase suspend function 0: Disabled FMR40 enable bit 1: Enabled Erase suspend 0: Erase restart FMR41 1: Suspend request...
Page 262 17. Flash Memory Version EW0 mode operation procedure Rewrite control program Set the FMR01 bit to “1” after writing “0” Single-chip mode (CPU rewrite mode enabled) (2) Set CM0, CM1, and PM1 registers (1) Execute software commands Transfer a rewrite control program to internal RAM Execute the Read Array command (3) area Write “0”...
Page 263 17. Flash Memory Version Low power consumption mode program Transfer a low power internal consumption mode Set the FMR01 bit to “1” after setting “0” program to RAM area (CPU rewrite mode enabled) Set the FMSTP bit to “1” (flash memory stopped. Jump to the low power consumption mode Low power consumption state) program transferred to internal RAM area.
Page 264: Precautions In Cpu Rewrite Mode
17. Flash Memory Version 17.6 Precautions in CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. 17.6.1 Operation Speed When CPU clock source is the main clock, before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register.
Page 265: Dma Transfer
17. Flash Memory Version 17.6.6 DMA Transfer In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0”. (the auto-programming or auto-erasing duration ). 17.6.7 Writing Command and Data Write the command code and data to even addresses in the user ROM area. 17.6.8 Wait Mode When entering wait mode, set the FMR01 bit to “0”...
Page 266: Software Commands
17. Flash Memory Version 17.7 Software Commands Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing a command code, 8 high-order bits (D –D ) are ignored. Table 17.7.1. Software Commands First bus cycle Second bus cycle Command...
Page 267: Clear Status Register Command (50 )
17. Flash Memory Version 17.7.3 Clear Status Register Command (50 This command clears the status register to “0”. By writing ‘xx50 ’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 bits in the status register are set to “0”. 17.7.4 Program Command (40 The program command writes 2-byte data to the flash memory.
Page 268: Block Erase
17. Flash Memory Version 17.7.5 Block Erase By writing ‘xx20 ’ in the first bus cycle and ‘xxD0 ’ in the second bus cycle to the highest-order (even addresse of a block) and the auto-programming/erasing (erase and erase verify) start. The FMR00 bit in the FMR0 register indicates whether the auto-programming operation has been completed.
Page 269 17. Flash Memory Version (EW0 mode) Start Interrupt service routine FMR40=1 FMR41=1 Write the command code ‘xx20 ’ FMR46=1? Write ‘xxD0 ’ to the highest-order block address Access Flash Memory FMR00=1? FMR41=0 Return Full status check (2,4) (Interrupt service routine end) Block erase completed (EW1 mode) Start...
Page 270: Status Register
17. Flash Memory Version 17.8 Status Register The status register indicates the operating status of the flash memory and whether an erasing or a pro- gramming operates normally and an error ends. The FMR00, FMR06, and FMR07 bits in the FMR0 register indicate the status of the status register.
Page 271: Full Status Check
17. Flash Memory Version 17.8.4 Full Status Check When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur- rence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check).
Page 272 17. Flash Memory Version Full status check FMR06 =1 (1) Execute the clear status register command and set Command the status flag to “0” whether the command is FMR07=1? sequence error entered. (2) Reexecute the command after checking that it is entered correctly or the program command or the block erase command is not executed for the blocks which are protected.
Page 273: Standard Serial I/O Mode
17. Flash Memory Version 17.9 Standard Serial I/O Mode In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is applicable for the M16C/26A group. For more information about serial programmers, contact the manufacturer of your serial programmer.
Page 274 17. Flash Memory Version Table 17.9.1. Pin Functions (Flash Memory Standard Serial I/O Mode) Name Description Apply the voltage guaranteed for Program and Erase to Vcc pin and 0 Power input V to Vss pin. Connect to Vcc pin. Reset input RESET Reset input pin.
Page 275 17. Flash Memory Version M16C/26A Group (M16C/26A) (Flash memory version) PRSP0042GA-B (42P2R) RESET BUSY Connect SCLK oscillator circuit Mode setup method Signal Value CNVss Reset Vss to Vcc NOTE: 1. Set following either or both in serial I/O mode while the RESET pin is held “L”. ⋅...
Page 276 17. Flash Memory Version M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) (Flash memory version) PLQP0048KB-A (48P6Q) Mode setup method Signal Value CNVss Connect Reset Vss to Vcc oscillator circuit NOTE: 1. Set following either or both in serial I/O mode while the RESET pin is held “L”. ⋅...
Page 277: Example Of Circuit Application In Standard Serial I/O Mode
17. Flash Memory Version 17.9.2 Example of Circuit Application in Standard Serial I/O Mode Figure 17.9.2.1 shows an example of a circuit application in standard serial I/O mode 1 and Figure 17.9.2.2 shows an example of a circuit application in standard serial I/O mode 2. Refer to the user's manual for a serial writer to handle pins controlled by the serial writer.
Page 278 17. Flash Memory Version Microcomputer SCLK (CE) TxD output BUSY Monitor output RxD input CNVss (RP) (1) In this example, a selector controls the input voltage applied to CNVss to switch between single-chip mode and standard serial I/O mode. NOTE: 1.
Page 279: Parallel I/O Mode
17. Flash Memory Version 17.10 Parallel I/O Mode In parallel input/output mode, the user ROM can be rewritten using a parallel programmer which is appli- cable for the M16C/26A group. For more information about the parallel programmer, contact your parallel programmer manufacturer.
Page 280: Electrical Characteristics
18. Electrical Characteristics (M16C/26A, M16C/26B) 18. Electrical Characteristics Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for electrical characteristics of V-ver. 18.1. M16C/26A, M16C/26B (Normal version) Table 18.1. Absolute Maximum Ratings 4 - < <...
Page 281 18. Electrical Characteristics (M16C/26A, M16C/26B) Table 18.2. Recommended Operating Conditions " ( ) " L " ) " " ( ) " " ( ) " L " ) " L " ) " l l i l l i l l i l l i l l i...
Page 282 18. Electrical Characteristics (M16C/26A, M16C/26B) Table 18.3. A /D Conversion Characteristics s t i ± n i l y t i ± ± ± ± ± l a i n i l y t i ± ± ± t s i kΩ...
Page 283 18. Electrical Characteristics (M16C/26A, M16C/26B) Table 18.4. Flash Memory Version Electrical Characteristic Program Space and Data Space for U3 and U5, Program Space for U7 and U9 µs ° ) ° ) µs z i l Table 18.5. Flash Memory Version Electrical Characteristics : Data Space for U7 and U9 µs °...
Page 284 18. Electrical Characteristics (M16C/26A, M16C/26B) (1, 3) Table 18.6. Voltage Detection Circuit Electrical Characteristics > h " . " ≤ l a i Table 18.7. Power Supply Circuit Timing Characteristics z i l µs z i l l l i µs µs µs...
Page 285 18. Electrical Characteristics (M16C/26A, M16C/26B) = 5V Table 18.8. Electrical Characteristics " ( ) " µA " ( ) " " ( ) " e i l " ( ) " e i l L " ) " µA L " ) "...
Page 286 18. Electrical Characteristics (M16C/26A, M16C/26B) = 5V Table 18.9. Electrical Characteristics (2) l l i l l i µA µA l l i µA µA µA l l i µA ) 2 ( t i a a l l o i t y t i µA ) 2 (...
Page 287 18. Electrical Characteristics (M16C/26A, M16C/26B) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 18.10. External Clock Input (X input) " ( ) "...
Page 288 18. Electrical Characteristics (M16C/26A, M16C/26B) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 18.11. Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 289 18. Electrical Characteristics (M16C/26A, M16C/26B) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 18.17. Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 290 18. Electrical Characteristics (M16C/26A, M16C/26B) = 5V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input su(UP-TIN) h(TIN-UP) (When count on falling edge is selected) TAiIN input (When count on rising edge is selected)
Page 291 18. Electrical Characteristics (M16C/26A, M16C/26B) = 5V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi d(C–Q) su(D–C) h(C–D) RxDi w(INL) INTi input w(INH) Figure 18.2. Timing Diagram (2) page 272...
Page 292 18. Electrical Characteristics (M16C/26A, M16C/26B) = 3V Table 18.23. Electrical Characteristics " ( ) " " ( ) " µA e i l " ( ) " e i l L " ) " L " ) " µA e i l L "...
Page 293 18. Electrical Characteristics (M16C/26A, M16C/26B) = 3V Table 18.24. Electrical Characteristics (2) l l i l l i µA µA l l i µA µA µA l l i µA ) 2 ( t i a a l l o i t y t i µA ) 2 (...
Page 294 18. Electrical Characteristics (M16C/26A, M16C/26B) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 18.25. External Clock Input (X input) " ( ) "...
Page 295 18. Electrical Characteristics (M16C/26A, M16C/26B) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 18.26. Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 296 18. Electrical Characteristics (M16C/26A, M16C/26B) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 18.32. Timer B Input (Counter Input in Event Counter Mode) Standard Symbo Paramete...
Page 297 18. Electrical Characteristics (M16C/26A, M16C/26B) = 3V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During Event Counter Mode TAiIN input h(TIN-UP) su(UP-TIN) (When count on falling edge is selected) TAiIN input (When count on rising edge is selected)
Page 298 18. Electrical Characteristics (M16C/26A, M16C/26B) = 3V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 18.4. Timing Diagram (2) page 279...
Page 299: M16C/26T (T Version)
18. Electrical Characteristics (M16C/26T) 18.2. M16C/26T (T version) Table 18.38. Absolute Maximum Ratings 4 - < < ° 5 ° ° ° ° page 280...
Page 300 18. Electrical Characteristics (M16C/26T) Table 18.39. Recommended Operating Conditions " ( ) " L " ) " " ( ) " " ( ) " L " ) " L " ) " l l i l l i l l i l l i l l i l l i...
Page 301 18. Electrical Characteristics (M16C/26T) Table 18.40. A/D Conversion Characteristics s t i ± n i l y t i ± ± ± ± ± l a i n i l y t i ± ± ± t s i kΩ µs φ...
Page 302 18. Electrical Characteristics (M16C/26T) Table 18.41. Flash Memory Version Electrical Characteristics Program Space and Data Space for U3, Program Space for U7 µs ° ) ° ) µs z i l Table 18.42. Flash Memory Version Electrical Characteristics : Data Space for U7 , 3 ( µs °...
Page 303 18. Electrical Characteristics (M16C/26T) Table 18.43. Power Supply Circuit Timing Characteristics z i l µs z i l l l i µs d(P-R) Wait time to stabilize internal supply voltage when power-on d(ROC) td(P-R) td(ROC) Wait time to stabilize internal on-chip oscillator when power- RESET Interrupt for...
Page 304 18. Electrical Characteristics (M16C/26T) = 5V Table 18.44. Electrical Characteristics " ( ) " µA " ( ) " " ( ) " e i l " ( ) " e i l L " ) " µA L " ) "...
Page 305 18. Electrical Characteristics (M16C/26T) = 5V Table 18.45. Electrical Characteristics (2) l l i µA µA µA l l i µA ) 2 ( t i a a l l o i t y t i µA ) 2 ( t i a a l l o i t...
Page 306 18. Electrical Characteristics (M16C/26T) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 18.46. External Clock Input (X input) Standard Symbol Parameter Unit Min. Max. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width w(L)
Page 307 18. Electrical Characteristics (M16C/26T) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 18.47. Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max.
Page 308 18. Electrical Characteristics (M16C/26T) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 18.53. Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max.
Page 309 18. Electrical Characteristics (M16C/26T) = 5V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input h(TIN-UP) su(UP-TIN) (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode...
Page 310 18. Electrical Characteristics (M16C/26T) = 5V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 18.6. Timing Diagram (2) page 291...
Page 311 18. Electrical Characteristics (M16C/26T) = 3V Table 18.59. Electrical Characteristics " ( ) " " ( ) " µA e i l " ( ) " e i l L " ) " L " ) " µA e i l L "...
Page 312 18. Electrical Characteristics (M16C/26T) = 3V Table 18.60. Electrical Characteristics (2) l l i µA µA µA l l i µA ) 2 ( t i a a l l o i t y t i µA ) 2 ( t i a a l l o i t...
Page 313 18. Electrical Characteristics (M16C/26T) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 18.61. External Clock Input (X input) Standard Symbol Parameter Unit Min. Max. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width w(L)
Page 314 18. Electrical Characteristics (M16C/26T) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 18.62. Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max.
Page 315 18. Electrical Characteristics (M16C/26T) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 40 to 85 C unless otherwise specified) Table 18.68. Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter Unit Min. Max.
Page 316 18. Electrical Characteristics (M16C/26T) = 3V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During Event Counter Mode TAiIN input h(TIN-UP) su(UP-TIN) (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-Phase Pulse Input in Event Counter Mode...
Page 317 18. Electrical Characteristics (M16C/26T) = 3V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi d(C–Q) su(D–C) h(C–D) RxDi w(INL) INTi input w(INH) Figure 18.8. Timing Diagram (2) page 298...
Page 318: Usage Notes
19. Usage Notes 19. Usage Notes 19.1 SFR 19.1.1 Precaution for 48-pin package Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR register to "100 ". 19.1.2 Precaution for 42-pin package Set the IFSR20 bit in the IFSR2A register to "1"...
Page 319: Pll Frequency Synthesizer
19. Usage Notes 19.2 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. Standard Symbol Unit Parameter Min. Typ. Max. Power supply ripple allowable frequency(V (ripple) Power supply ripple allowabled amplitude =5V) p-p(ripple) voltage =3V)
Page 320: Power Control
19. Usage Notes 19.3 Power Control 1. When exiting stop mode by hardware reset, the device will startup using the on-chip oscillator. 2. Set the MR0 bit in the TAiMR register(i=0 to 4) to “0”(pulse is not output) to use the timer A to exit stop mode.
Page 321 19. Usage Notes 5. Wait until the main clock oscillation stabilization time, before switching the CPU clock source to the main clock. Similarly, wait until the sub clock oscillates stably before switching the CPU clock source to the sub clock. 6.
Page 322: Protect
19. Usage Notes 19.4 Protect Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to “1”.
Page 323: Interrupts
19. Usage Notes 19.5 Interrupts 19.5.1 Reading address 00000 Do not read the address 00000 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000 during the interrupt sequence.
Page 324 19. Usage Notes Changing the interrupt source Disable interrupts (2, 3) Change the interrupt generate factor (including a mode change of peripheral function) Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (3) Enable interrupts (2, 3) End of change IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed...
Page 325: Rewrite The Interrupt Control Register
19. Usage Notes 19.5.6 Rewrite the Interrupt Control Register (1) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register. (2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used.
Page 326: Dmac
19. Usage Notes 19.6 DMAC 19.6.1 Write to DMAE Bit in DMiCON Register When both of the conditions below are met, follow the steps below. Conditions • The DMAE bit is set to “1” again while it remains set (DMAi is in an active state). •...
Page 327: Timer
19. Usage Notes 19.7 Timer 19.7.1 Timer A 19.7.1.1 Timer A (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts).
Page 328 19. Usage Notes 19.7.1.3 Timer A (One-shot Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
Page 329 19. Usage Notes 19.7.1.4 Timer A (Pulse Width Modulation Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
Page 330: Timer B
19. Usage Notes 19.7.2 Timer B 19.7.2.1 Timer B (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to “1” (count starts).
Page 331: Three-Phase Motor Control Timer Function
19. Usage Notes 19.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) 1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 2) register before setting the TBiS bit in the TABSR register to “1” (count starts). Always make sure the TBiMR register is modified while the TBiS bit remains “0”...
Page 332: Serial I/O
19. Usage Notes 19.8 Serial I/O 19.8.1 Clock-Synchronous Serial I/O 19.8.1.1 Transmission/reception _______ ________ 1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmission side ________ that the reception has become ready.
Page 333: Serial I/O (Uart Mode)
19. Usage Notes 19.8.2 Serial I/O (UART Mode) 19.8.1.1 Special Mode 1 (I C bus Mode) When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to “0” and wait for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ, RSTAREQ and STPREQ) from “0”...
Page 334: A/D Converter
19. Usage Notes 19.9 A/D Converter 1. Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs). 2. When the VCUT bit in the ADCON1 register is changed from “0” (Vref not connected) to “1” (V connected), start A/D conversion after waiting 1 µs or longer.
Page 335 19. Usage Notes 8. If the CPU reads the A/D register i (i = 0 to 7) at the same time the conversion result is stored in the A/ D register i after completion of A/D conversion, an incorrect value may be stored in the A/D register i. This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU clock.
Page 336: Programmable I/O Ports
19. Usage Notes 19.10 Programmable I/O Ports _____ 1. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1” _____ (three-phase output forcible cutoff by input on SD pin enabled), the P7 to P7 , P8 and P8...
Page 337: Electric Characteristic Differences Between Mask Rom
19. Usage Notes 19.11 Electric Characteristic Differences Between Mask ROM and Flash Memory Ver- sion Microcomputers Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc.
Page 338: Mask Rom Version
19. Usage Notes 19.12 Mask ROM Version 19.12.1 Internal ROM area When using the masked ROM version, write nothing to internal ROM area. Writing to the area may increase power consumption. 19.12.2 Reserve bit The b3 to b0 in address 0FFFFF are reserved bits.
Page 339: Flash Memory Version
19. Usage Notes 19.13 Flash Memory Version 19.13.1 Functions to Inhibit Rewriting Flash Memory ID codes are stored in addresses 0FFFDF , 0FFFE3 , 0FFFEB , 0FFFEF , 0FFFF3 , 0FFFF7 and 0FFFFB . If wrong data is written to these addresses, the flash memory cannot be read or written in standard serial I/O mode.
Page 340: Interrupts
19. Usage Notes 19.13.9 Interrupts EW0 Mode • Any interrupt which has a vector in the variable vector table can be used, providing that its vector is transferred into the RAM area. _______ • The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 regis- ter are initialized when one of those interrupts occurs.
Page 341: Definition Of Programming/Erasure Times
19. Usage Notes 19.13.14 Definition of Programming/Erasure Times "Number of programs and erasure" refers to the number of erasure per block. If the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times. For example, if a 2K byte block A is erased after writing 1 word data 1024 times, each to a different address, this is counted as one program and erasure.
Page 342: Noise
19. Usage Notes 19.14 Noise Connect a bypass capacitor (approximately 0.1µF) across the V and V pins using the shortest and thicker possible wiring. Figure 19.4 shows the bypass capacitor connection. M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Connecting Pattern Connecting Pattern Bypass Capacitor Figure 19.4 Bypass Capacitor Connection page 323...
Page 343: Instruction For A Device Use
19. Usage Notes 19.15 Instruction for a Device Use When handling a device, extra attention is necessary to prevent it from crashing during the electrostatic discharge period. page 324...
Page 344: Appendix 1. Package Dimensions
Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP48-7x7-0.50 PLQP0048KB-A 48P6Q-A 0.2g NOTE) 1. DIMENSIONS "*1" AND "*2" DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Reference Symbol Terminal cross section Index mark 0.17...
Page 345: Appendix 2. Functional Difference
Appendix 2. Functional Difference Appendix 2. Functional Difference Appendix 2.1 Differences between M16C/26A, M16C/26B, and M16C/26T Item M16C/26A, M16C/26B M16C/26T Main Clock during Oscillating Stoped and after Reset (Default value “0” while and after the (Default value “1” while and after the CM05 bit is reset.) CM05 bit is reset.) Voltage Detection...
Page 346: Appendix 2.2 Differences Between M16C/26A Group And M16C/26 Group
Appendix 2. Functional Difference Appendix 2.2 Differences between M16C/26A Group and M16C/26 Group Item M16C/26A Group M16C/26 Group Clock Generation 4 circuits (Main clock oscillation circuit, 3 circuits (Main clock oscillation circuit, Circuit Sub clock oscillation circuit, Sub clock oscillation circuit, on-chip oscillator, on-chip oscillator) PLL frequency synthesizer)
Page 347: Register Index
Register Index Register Index IFSR2A 68 INT0IC to INT2IC 67 AD0 to AD7 184 INT3IC 67 ADCON0 to ADCON2 182 INT4IC 67 ADIC 67 INT5IC 67 ADSTAT0 184 INVC0 119 ADTRGCON 183 INVC1 120 AIER 79 KUPIC 67 BCNIC 67 NDDR 227 CM0 40 CM1 41...
Page 348 Register Index TA0 to TA4 95 WDC 81 TA0IC to TA4IC 67 WDTS 81 TA0MR to TA4MR 94 TA1 122 TA11 122 TA1MR 125 TA2 122 TA21 122 TA2MR 125 TA2MR to TA4MR 101 TA4 122 TA41 122 TA4MR 125 TABSR 95, 110, 124 TAiMR 99, 106 TB0 to TB5 110...
Page 349 REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual Rev. Date Description Page Summary 2.00 Feb.15,07 M16C/26B newly added, word standardized: on-chip oscillator, development tool Overview •Description partially deleted 2 - 3 •1.2 Performance Outline modified 4 - 5 •Figure 1.1 and 1.2 Block Diagrams updated •1.4 Product List updated •Figure 1.3 Product Numbering System updated •Tables 1.7 to 1.10 Product Codes updated...
Page 350 REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual Rev. Date Description Page Summary ______ •9.7 NMI Interrupt Description partially added •Table 9.9.1 Value of the PC that is saved to the stack area when an address match interrupt request is accepted modified, note 1 added Watchdog Timer •Section of Cold Start/Warm Start deleted •Description partially added...
Page 351 REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual Rev. Date Description Page Summary 1 added CRC Calculation Circuit •15.1 CRC Snoop Description partially modified •Figure 15.2 CRCSAR Register note 1 added Programable I/O Ports •16.3 Pull-up Control Register 0 to Pull-up Control Register 2 description modified •16.6 Digital Debounce function equation modified 218 - 221 •Figure 16.1 I/O Ports (1) to 16.4 I/O Ports (4) modified...
Page 352 REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual Rev. Date Description Page Summary •Tables 18.41 and 18.42 Flash Memory Version Electrical Characteristics note 4 , note 10, note 11 modified •Figure for td(P-R) and td(ROC) modified •Table 18.45 Electrical Characteristics note 4 deleted •Table 18.60 Electrical Characteristics (2) note 4 deleted Usage Notes •19.1.3 Register Setting newly added...
Page 353 RENESAS 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Publication Date: Rev.1.00 Mar.15, 2005 Rev.2.00 Feb.15, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 354 M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0202-0200...

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