Advertisement
M16C/5L Group, M16C/56 Group
12.7.3
Interrupt Response Time
Figure 12.4 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time
denotes the time from when an interrupt request is generated until the first instruction in the interrupt
routine is executed. Specifically, it consists of the time from when an interrupt request is generated until
the executing instruction is completed ((a) in Figure 12.4) and the time during which the interrupt
sequence is executed ((b) in Figure 12.4).
Interrupt request
generated
Instruction
(a) The time from when an interrupt request is generated until the instruction currently executing is completed. The length of this time
varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (no wait state if
the divisor is a register).
(b) The time during which the interrupt sequence is executed. For details, see the table below. Note, however, that the values in this table
must be increased by 2 cycles for the DBC interrupt and by 1 cycle for the address match and single-step interrupts.
Interrupt Vector Address
Even
Even
Odd
Odd
Figure 12.4
Interrupt Response Time
12.7.4
Variation of IPL When Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is
set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels
listed in Table 12.10 is set in the IPL. Table 12.10 lists the IPL Level Set in IPL When Software or
Special Interrupt is Accepted.
Table 12.10
IPL Level Set in IPL When Software or Special Interrupt is Accepted
Watchdog timer, NMI , oscillator stop/restart detect,
voltage monitor 2
Software, address match, DBC , single-step
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Interrupt request
acknowledged
Interrupt sequence
(a)
(b)
Interrupt response time
SP Value
Even
Odd
Even
Odd
Interrupt Source
Instruction in
interrupt routine
No Wait State
18 cycles
19 cycles
19 cycles
20 cycles
12. Interrupts
Time
Level Set in IPL
7
Not changed
Page 187 of 803
Advertisement
