Renesas M16C/50 Series User Manual page 539

M16C/5L Group, M16C/56 Group
22.2 Registers Descriptions
Table 22.4 lists registers associated with multi-master I
register is set to 1 (sub clock is CPU clock), registers listed in Table 22.4 should not be accessed. Set
them after the CM07 bit is set to 0 (main clock, PLL clock, or on-chip oscillator clock).
Table 22.4 Registers
Address
02B0h I2C0 Data Shift Register
02B2h I2C0 Address Register 0
02B3h I2C0 Control Register 0
02B4h I2C0 Clock Control Register
02B5h I2C0 Start/Stop Condition Control Register
02B6h I2C0 Control Register 1
02B7h I2C0 Control Register 2
02B8h I2C0 Status Register 0
02B9h I2C0 Status Register 1
02BAh I2C0 Address Register 1
02BBh I2C0 Address Register 2
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Register
22. Multi-master I
2
C-bus interface. When the CM07 bit in the CM0
Symbol
S00
S0D0
S1D0
S20
S2D0
S3D0
S4D0
S10
S11
S0D1
S0D2
2
C-bus Interface
Reset Value
XXh
0000 000Xb
00h
00h
0001 1010b
0011 0000b
00h
0001 000Xb
XXXX X000b
0000 000Xb
0000 000Xb
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