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M16C/5L Group, M16C/56 Group
22.3.2
Generating a Start Condition
Follow the procedure below when the ES0 bit in the S1D0 register is 1 (I
BB bit in the S10 register is set to 0 (bus free). Figure 22.6 shows the Procedure to Generate a Start
Condition.
(1) Write E0h to the S10 register.
2
The I
C interface enters the start condition standby state and the SDAMM pin is released.
(2) Write a slave address to the S00 register.
A start condition is generated. Then, the bit counter becomes 000b, the SCL clock signal is output
for 1 byte, and the slave address is transmitted.
After a stop condition is generated and the BB bit becomes 0 (bus free), a write to the S10 register is
disabled for 1.5 fVIIC cycles. Therefore, even if the S00 register is subsequently written to, a start
condition is not generated. When generating a start condition shortly after changing the BB bit from 1 to
0, confirm that both bits TRX and MST are 1 after executing step (1), then execute step (2).
Figure 22.6
Procedure to Generate a Start Condition
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Start condition generated
Interrupt disabled
BB bit in the S10 register = 0?
Yes (Bus free)
Set E0h to the S10 register
Set slave address to the S00 register
Interrupt enabled
Completed
22. Multi-master I
No (Bus busy)
Bus status checked
Start condition standby
Start condition trigger generated
2
C-bus Interface
2
C interface enabled) and the
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