Advertisement
M16C/5L Group, M16C/56 Group
23.1.5
CAN0 FIFO Received ID Compare Register n (C0FIDCR0 to C0FIDCR1)
(n = 0, 1)
CAN0 FIFO Received ID Compare Register n
b31b28
b18b17
0
Notes:
1. Write to registers C0FIDCR0 and C0FIDCR1 in CAN reset mode or CAN halt mode.
2. The IDE bit is enabled when the IDFM bit in the C0CTLR register is 10b (mixed ID mode).
When the IDFM bit is not 10b, the IDE bit should be written with 0.
Figure 23.6
Registers C0FIDCR0 to C0FIDCR1
Registers C0FIDCR0 and C0FIDCR1 are enabled when the MBM bit in the C0CTLR register is set to 1
(FIFO mailbox mode). Bits EID, SID, RTR, and IDE in registers C0MB28 to C0MB31 are disabled.
Refer to 23.5 "Acceptance Filtering and Masking Function" about the usage of these registers.
23.1.5.1
EID Bit
The EID bit sets the extended ID of data frames and remote frames. This bit is used to receive
extended ID messages.
23.1.5.2
SID Bit
The SID bit sets the standard ID of data frames and remote frames. This bit is used to receive both
standard ID and extended ID messages.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b0
C0FIDCR0
C0FIDCR1
Bit Symbol
EID
Extended ID Bit
SID
Standard ID Bit
—
Reserved
(b29)
RTR
Remote Frame Request Bit
IDE
ID Extension Bit
(1)
(n = 0, 1)
Address
D723h-D720h
D727h-D724h
Bit Name
0: Corresponding EID bit is 0
1: Corresponding EID bit is 1
0: Corresponding SID bit is 0
1: Corresponding SID bit is 1
Set to 0.
0: Data frame
1: Remote frame
0: Standard ID
(2)
1: Extended ID
23. CAN Module
Reset Value
Undefined
Undefined
Function
RW
RW
RW
RW
RW
RW
Page 558 of 803
Advertisement
