Renesas M16C/50 Series User Manual page 402

M16C/5L Group, M16C/56 Group
18.2.16 Interrupt Request Register (G1IR)
Interrupt Request Register
b7 b6 b5 b4 b3 b2 b1
The G1IRj bit does not become 0 (interrupt not requested) automatically when an interrupt is received
(j = 0 to 7).
To set the bit to 0, wait one or more fBT1 cycles after the G1IRj bit becomes 1 (interrupt requested), and
perform the operation shown in 18.5.2 "Changing the G1IR Register".
The value written to these bits is reflected to the internal circuit in synchronization with the CPU clock.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0
Symbol
G1IR
Bit Symbol Bit Name
G1IR0 Channel 0 interrupt request bit
G1IR1 Channel 1 interrupt request bit
G1IR2 Channel 2 interrupt request bit
G1IR3 Channel 3 interrupt request bit
G1IR4 Channel 4 interrupt request bit
G1IR5 Channel 5 interrupt request bit
G1IR6 Channel 6 interrupt request bit
G1IR7 Channel 7 interrupt request bit
Address
02F0h
Function
0: Interrupt not requested
1: Interrupt requested
18. Timer S
Reset Value
XXh
RW
RW
RW
RW
RW
RW
RW
RW
RW
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