Renesas M16C/50 Series User Manual page 509

M16C/5L Group, M16C/56 Group
(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 1 (clock delay)
1st bit
SCL2
D7
SDA2
(2) IICM2 = 1 (UART transmit / receive interrupt), CKPH = 1
1st bit
SCL2
D7
SDA2
IICM2: Bit in the U2SMR2 register
CKPH: Bit in the U2SMR3 register
The above assumes the following:
· The CKDIR bit in the U2MR register = 1 (slave selected)
Figure 21.15 Transfer to U2RB Register and Interrupt Timing
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
2nd bit 3rd bit 4th bit 5th bit
D6 D5 D4 D3
2nd bit 3rd bit 4th bit 5th bit
D6 D5 D4 D3
Transfer to U2RB register
b15 b9
...
6th bit 7th bit 8th bit 9th bit
D2 D1 D0
ACK interrupt (DMA1, DMA3 request),
NACK interrupt
Transfer to U2RB register
6th bit 7th bit 8th bit 9th bit
D2 D1 D0
Receive interrupt
(DMA1, DMA3
request)
b8 b7 b0
D0 D7 D6 D5 D4 D3 D2 D1
U2RB register
21. Serial Interface UARTi (i = 0 to 4)
D8 (ACK, NACK)
b15 b9 b8 b7
...
D8 D7 D6 D5 D4 D3
U2RB register
D8 (ACK, NACK)
Transmit interrupt
Transfer to U2RB register
b15 b9 b8 b7
...
D8 D7 D6 D5 D4 D3
U2RB register
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b0
D2 D1 D0
b0
D2 D1 D0