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M16C/5L Group, M16C/56 Group
21.3.3
Special Mode 1 (I
2
I
C mode is compatible with the simplified I
Table 21.14 and Table 21.15 list the Registers Used and Settings in I
Mode Functions. Figure 21.13 shows the I
As shown in Table 21.16, the MCU is placed in I
register to 010b and the IICM bit in the U2SMR register to 1. Because SDA2 transmit output has a delay
circuit attached, SDA2 output does not change state until SCL2 goes low and remains stably low.
I 2 C Mode Specifications
Table 21.12
Item
Data format
Transfer clock
Transmit/receive clock
Reception start conditions
Interrupt request
generation timing
Error detection
Selectable functions
Notes:
1.
These requirements do not have to be set in any particular order. When transmission/reception is
started as a slave and the TXEPT bit in the U2C0 register is 1 (no data present in transmit register),
meet the last requirement when the external clock is high.
2.
If an overrun error occurs, the received data of the U2RB register will be undefined.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
2
C Mode) (UART2)
2
C interface. Table 21.12 lists the I
2
C Mode Block Diagram.
2
Character bit length: 8 bits
•
Master mode
The CKDIR bit in the U2MR register is 0 (internal clock): fj / (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO
n = setting value of the U2BRG register (03h to FFh)
•
Slave mode
The CKDIR bit is 1 (external clock): input from the SCL2 pin
To start transmission, satisfy the following requirements
•
The TE bit in the U2C1 register is 1 (transmission enabled)
•
The TI bit in the U2C1 register is 0 (data present in U2TB register)
To start reception, satisfy the following requirements
•
The RE bit in the U2C1 register is 1 (reception enabled)
•
The TE bit in the U2C1 register is 1 (transmission enabled)
•
The TI bit in the U2C1 register is 0 (data present in the U2TB register)
When a start condition, stop condition, ACK (acknowledge), or NACK (not-
acknowledge) is detected.
(2)
Overrun error
This error occurs if the serial interface starts receiving the next unit of data
before reading the U2RB register and receives the eighth bit of the unit of
next data.
•
Arbitration lost
Timing at which the ABT bit in the U2RB register is updated can be
selected.
•
SDA2 digital delay
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles can
be selected.
•
Clock phase setting
With or without clock delay can be selected.
21. Serial Interface UARTi (i = 0 to 4)
2
C Mode. Table 21.16 lists the I
C mode by setting bits SMD2 to SMD0 in the U2MR
Specification
2
C Mode Specifications.
2
(1)
(1)
Page 467 of 803
C
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