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M16C/5L Group, M16C/56 Group
12.7.2
Interrupt Sequence
The interrupt sequence is explained here. The sequence starts when an interrupt request is accepted
and ends when the interrupt routine is executed.
When an interrupt request occurs during execution of an instruction, the processor determines its
priority after the execution of the instruction is completed, and transfers control to the interrupt
sequence from the next cycle. However, if an interrupt occurs during execution of either the SMOVB,
SMOVF, SSTR, or RMPA instruction, the processor temporarily suspends the instruction being
executed, and transfers control to the interrupt sequence.
The CPU behavior during the interrupt sequence is described below. Figure 12.3 shows Time Required
for Executing Interrupt Sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading
address 00000h. Then, the IR bit applicable to the interrupt information is set to 0 (interrupt not
requested).
(2) The FLG register, prior to the interrupt sequence, is saved to a temporary register
CPU.
(3) Flags I, D, and U in the FLG register are set as follows:
The I flag is set to 0 (interrupt disabled)
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
Note that the U flag does not change states when an INT instruction for software interrupt numbers
32 to 63 is executed.
(4) The temporary register
(5) The PC is saved on the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, an instruction is executed from the starting address of the
interrupt routine.
Note:
1. Temporary registers cannot be modified by the user.
1
2
CPU clock
Address
Address
00000h
bus
Data bus
information
RD
(2)
WR
Notes:
1. The undefined state depends on the instruction queue buffer. A read cycle is generated when
the instruction queue buffer is ready to prefetch.
2. The WR signal timing shown here applies when the stack is located in the internal RAM.
Figure 12.3
Time Required for Executing Interrupt Sequence
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
(1)
within the CPU is saved on the stack.
3
4
5
6
7
(1)
Undefined
Interrupt
Undefined
Undefined
8
9
10
11
SP-2
SP-4
SP-2
(1)
contents
contents
(1)
12
13
14
15
16
vec
vec+2
vec
vec+2
SP-4
contents
contents
12. Interrupts
(1)
within the
17
18
PC
Page 186 of 803
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