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M16C/5L Group, M16C/56 Group
23.1.1.1
CANM Bit
The CANM bit selects one of the following modes for the CAN module: CAN operation mode, CAN
reset mode, or CAN halt mode. Refer to 23.2 "Operating Mode" for details.
CAN sleep mode is set by the SLPM bit.
Do not set the CANM bit to 11b.
When the CAN module enters CAN halt mode according to the setting of the BOM bit, the CANM bit is
automatically set to 10b.
23.1.1.2
SLPM Bit
When the SLPM bit is set to 1, the CAN module enters CAN sleep mode.
When this bit is set to 0, the CAN module exits CAN sleep mode.
Refer to 23.2 "Operating Mode" for details.
23.1.1.3
BOM Bit
The BOM bit is used to select bus-off recovery mode.
When the BOM bit is 00b, the recovery from bus-off is compliant with ISO11898-1, i.e. the CAN module
reenters CAN communication (error-active state) after detecting 11 consecutive recessive bits 128
times. A bus-off recovery interrupt request is generated when recovering from bus-off.
When the BOM bit is 01b, as soon as the CAN module reaches the bus-off state, the CANM bit in the
C0CTLR register is set to 10b (CAN halt mode) and the CAN module enters CAN halt mode. No bus-off
recovery interrupt request is generated when recovering from bus-off and registers C0TECR and
C0RECR are set to 00h.
When the BOM bit is 10b, the CANM bit is set to 10b as soon as the CAN module reaches the bus-off
state. The CAN module enters CAN halt mode after the recovery from the bus-off state, i.e. after
detecting 11 consecutive recessive bits 128 times. A bus-off recovery interrupt request is generated
when recovering from bus-off and registers C0TECR and C0RECR are set to 00h.
When the BOM bit is 11b, the CAN module enters CAN halt mode by setting the CANM bit to 10b while
the CAN module is still in bus-off state. No bus-off recovery interrupt request is generated when
recovering from bus-off and registers C0TECR and C0RECR are set to 00h. However, if the CAN
module recovers from bus-off after detecting 11 consecutive recessive bits 128 times before the CANM
bit is set to10b, a bus-off recovery interrupt request is generated.
If the CPU requests an entry to CAN reset mode at the same time as the CAN module attempts to enter
CAN halt mode (at bus-off entry when the BOM bit is 01b, or at bus-off end when the BOM bit is 10b),
then the CPU request to enter CAN reset mode has higher priority.
23.1.1.4
RBOC Bit
When the RBOC bit is set to 1 (force return from bus-off) in bus-off state, the CAN module forcibly
returns from the bus-off state. This bit is automatically set to 0. The error state changes from bus-off to
error-active.
When the RBOC bit is set to 1, registers C0RECR and C0TECR are set to 00h and the BOST bit in the
C0STR register is set to 0 (the CAN module is not in bus-off state). The other registers remain
unchanged. No bus-off recovery interrupt request is generated by this recovery from the bus-off state.
Use the RBOC bit only when the BOM bit is 00b (normal mode).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
23. CAN Module
Page 551 of 803
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