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M16C/5L Group, M16C/56 Group
22.2.5
I2C0 Start/Stop Condition Control Register (S2D0)
I2C0 Start/Stop Condition Control Register
b7 b6 b5 b4
b3
b2
b1
SSC4 to SSC0 (Start/stop condition setting bit) (b4-b0)
Set bits SSC4 to SSC0 to select the start/stop condition detect parameter (SCL open time, setup time,
hold time) in standard-speed clock mode. Refer to 22.3.7 "Detecting Start/Stop Conditions".
Do not set an odd value or 00000b to these bits.
SIP (SCL/SDA interrupt pin polarity select bit) (b5)
SIS (SCL/SDA interrupt pin select bit) (b6)
The IR bit in the SCLDAIC register becomes 1 (interrupt requested) when the I
edge selected by the SIP bit for the pin signal selected by the SIS bit. Refer to 22.4 "Interrupts".
STSPSEL (Start/stop condition generation select bit) (b7)
See Table 22.12 "Setup/Hold Time for Generating a Start/Stop Condition".
If the fVIIC frequency is more than 4 MHz, set the STSPSEL bit to 1 (long mode).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b0
S2D0
Bit Symbol
Bit Name
SSC0
SSC1
SSC2
Start/stop condition setting bit
SSC3
SSC4
SCL/SDA interrupt pin polarity
SIP
select bit
SIS
SCL/SDA interrupt pin select bit
Start/stop condition generation
STSPSEL
select bit
22. Multi-master I
Address
02B5h
Function
Refer to SSC4 to SSC0 (Start/Stop
Condition Setting Bit) (b4 to b0) in the
same page
0: Falling edge
1: Rising edge
0: SDAMM
1: SCLMM
0: Short setup/hold time mode
1: Long setup/hold time mode
2
C-bus Interface
Reset Value
0001 1010b
RW
RW
RW
RW
RW
RW
RW
RW
RW
2
C interface detects the
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