Renesas M16C/50 Series User Manual page 630

M16C/5L Group, M16C/56 Group
23.1.23.4 CEF Bit
The CEF bit is set to 1 when a CRC error is detected.
23.1.23.5 BE1F Bit
The BE1F bit is set to 1 when a recessive bit error is detected.
23.1.23.6 BE0F Bit
The BE0F bit is set to 1 when a dominant bit error is detected.
23.1.23.7 ADEF Bit
The ADEF bit is set to 1 when a form error is detected with the ACK delimiter during transmission.
23.1.23.8 EDPM Bit
The EDPM bit selects the output mode of the C0ECSR register.
When this bit is set to 0, the C0ECSR register outputs the first error code.
When this bit is set to 1, the C0ECSR register outputs the accumulated error code.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
23. CAN Module
Page 593 of 803