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M16C/5L Group, M16C/56 Group
28.17 Notes on Serial Interface UARTi (i = 0 to 4)
Note
Pins CLK4, RXD4, and TXD4 do not exist in the 64-pin package. Do not access the UART4
associated registers.
28.17.1 Common Notes on Multiple Modes
28.17.1.1 Influence of SD
When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance:
P7_2/CLK2/TA1OUT/V/RXD1, P7_3/ CTS2 / RTS2 /TA1IN/ V /TXD1, P7_4/TA2OUT/W,
P7_5/TA2IN/ W , P8_0/TA4OUT/U/TSUDA, P8_1/TA4IN/ U /TSUDB
28.17.1.2 Register Setting
Set the OCOSEL0 or OCOSEL1 bit in the UCLKSEL0 register before setting other registers
associated with UART0 to UART4. After changing the OCOSEL0 or OCOSEL1 bit, set other registers
associated with UART0 to UART4 again.
28.17.2 Clock Synchronous Serial I/O Mode
28.17.2.1 Transmission/Reception
When the RTS function is used with an external clock, the RTSi pin (i = 0 to 3) outputs a low-level
signal, which informs the transmitting side that the MCU is ready for a receive operation. The RTSi
pin outputs a high-level signal when a receive operation starts. Therefore, transmit timing and receive
timing can be synchronized by connecting the RTSi pin to the CTSi pin on the transmitting side. The
RTS function is disabled when an internal clock is selected.
28.17.2.2 Transmission
If the transmission is started while an external clock is selected and the TXEPT bit in the UiC0
register (i = 0 to 4) is 1 (no data present in transmit register), meet the last requirement at either of the
following timings:
External clock level:
•
The CKPOL bit in the UiC0 register is 0 (transmit data is output at the falling edge of
transmit/receive clock and receive data is input at the rising edge) and the external clock is high.
•
The CKPOL bit is 1 (transmit data is output at the rising edge of transmit/receive clock and receive
data is input at the falling edge) and the external clock is low.
Requirements to start transmission (in no particular order):
•
The TE bit in the UiC1 register is 1 (transmission enabled).
•
The TI bit in the UiC1 register is 0 (data present in the UiTB register).
When the CTS function is selected, input on the CTSi pin is low.
•
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
28. Usage Notes
Page 789 of 803
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