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13.6
Notes on the Watchdog Timer ...................................................................................................211
14. DMAC................................................................................................... 212
14.1
Introduction ............................................................................................................................... 212
14.2
Registers................................................................................................................................... 214
14.2.1
DMAi Source Pointer (SARi) (i = 0 to 3) .......................................................................... 215
14.2.2
DMAi Destination Pointer (DARi) (i = 0 to 3) ................................................................... 215
14.2.3
DMAi Transfer Counter (TCRi) (i = 0 to 3) ....................................................................... 216
14.2.4
DMAi Control Register (DMiCON) (i = 0 to 3) .................................................................. 217
14.2.5
DMAi Source Select Register (DMiSL) (i = 0 to 3) .......................................................... 218
14.3
Operations ................................................................................................................................ 221
14.3.1
DMA Enabled .................................................................................................................. 221
14.3.2
DMA Request .................................................................................................................. 221
14.3.3
Transfer Cycles ............................................................................................................... 222
14.3.4
DMAC Transfer Cycles .................................................................................................... 224
14.3.5
Single Transfer Mode ...................................................................................................... 225
14.3.6
Repeat Transfer Mode ..................................................................................................... 226
14.3.7
Channel Priority and DMA Transfer Timing ..................................................................... 227
14.4
Interrupts................................................................................................................................... 228
14.5
Notes on DMAC........................................................................................................................ 229
14.5.1
Write to the DMAE Bit in the DMiCON Register (i = 0 to 3) ............................................. 229
14.5.2
Changing the DMA Request Source ............................................................................... 229
15. Timer A ................................................................................................. 230
15.1
Introduction ............................................................................................................................... 230
15.2
Registers................................................................................................................................... 233
15.2.1
Peripheral Clock Select Register (PCLKR) ..................................................................... 234
15.2.2
Clock Prescaler Reset Flag (CPSRF) ............................................................................. 234
15.2.3
Timer AB Division Control Register 0 (TCKDIVC0) ......................................................... 235
15.2.4
Timer A Count Source Select Register i (TACSi) (i = 0 to 2) ........................................... 236
15.2.5
16-bit Pulse Width Modulation Mode Function Select Register (PWMFS) ...................... 237
15.2.6
Timer A Waveform Output Function Select Register (TAPOFS) ..................................... 238
15.2.7
Timer A Output Waveform Change Enable Register (TAOW) ......................................... 239
15.2.8
Timer Ai Register (TAi) (i = 0 to 4) ................................................................................... 240
15.2.9
Timer Ai-1 Register (TAi1) (i = 1, 2, 4) ............................................................................. 241
15.2.10
Count Start Flag (TABSR) ............................................................................................... 241
15.2.11
One-Shot Start Flag (ONSF) ........................................................................................... 242
15.2.12
Trigger Select Register (TRGSR) .................................................................................... 243
15.2.13
Increment/Decrement Flag (UDF) ................................................................................... 244
15.2.14
Timer Ai Mode Register (TAiMR) (i = 0 to 4) ................................................................... 245
15.3
Operations ................................................................................................................................ 246
A- 7
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