Renesas M16C/50 Series User Manual

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M16C/5L Group, M16C/56 Group

RENESAS MCU

M16C Family / M16C/50 Series

All information contained in these materials, including products and product specifications, represents

information on the product at the time of publication and is subject to change by Renesas Electronics

Corp. without notice. Please review the latest informaton published by Renesas Electronics Corp.

through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.1.10

Sep 2011

Summary of Contents for Renesas M16C/50 Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest informaton published by Renesas Electronics Corp.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4 For details, please refer to the relative chapters or sections of this manual. The M16C/5L Group, M16C/56 Group includes the documents listed below. Verify this manual is the latest version by visiting the Renesas Electronics website. Type of Document...
Page 5 Numbers and Symbols The following explains the denotations used in this manual for registers, bits, pins and various numbers. (1) Registers, bits, and pins Registers, bits, and pins are indicated by symbols. Each symbol has a register/bit/pin identifier after the symbol. Example: PM03 bit in the PM0 register P3_5 pin, VCC pin (2) Numbers...
Page 6 Registers The following illustration describes registers used throughout this manual. See Note 1 Example Register See Note 2 b7 b6 b5 b4 b3 b2 b1 Symbol Address Reset Value EXAMPLE 9999h 000X 1X00b Bit Symbol Bit Name Description b2 b1 AAAA0 0 0 : XX function Example bit 0...
Page 7 Abbreviations and Acronyms The following acronyms and terms are used throughout this manual. Abbreviation/Acronym Meaning ACIA Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus...
Page 8 Table of Contents Quick Reference .......................B-1 Overview ....................1 Features............................1 1.1.1 Applications ......................... 1 Specifications..........................2 Product List........................... 6 Block Diagram ..........................8 Pin Assignments ......................... 10 Pin Functions ..........................16 Central Processing Unit (CPU)............... 19 Data Registers (R0, R1, R2, and R3) ..................20 Address Registers (A0 and A1) ....................
Page 9 5.2.1 Protect Register (PRCR) ....................57 Notes on Protection ........................59 Resets ....................60 Introduction ..........................60 Registers............................. 62 6.2.1 Processor Mode Register 0 (PM0) ..................62 6.2.2 Reset Source Determine Register (RSTFR) ..............63 Optional Function Select Area ....................64 6.3.1 Optional Function Select Address 1 (OFS1) ..............
Page 10 Clock Generator ..................90 Introduction ..........................90 Registers............................. 92 8.2.1 System Clock Control Register 0 (CM0) ................93 8.2.2 System Clock Control Register 1 (CM1) ................95 8.2.3 Oscillation Stop Detection Register (CM2) ................ 97 8.2.4 Peripheral Clock Select Register (PCLKR) ............... 99 8.2.5 PLL Control Register 0 (PLC0) ..................
Page 11 9.3.1 Normal Operating Mode ....................122 9.3.2 Clock Mode Transition Procedure ................... 126 9.3.3 Wait Mode ........................129 9.3.4 Stop Mode ........................131 Power Control in Flash Memory ....................133 9.4.1 Stopping Flash Memory ....................133 9.4.2 Reading Flash Memory ....................134 Reducing Power Consumption ....................
Page 12 11.3.10 Pin Assignment Control Register (PACR) ............... 159 11.3.11 Port Pi Register (Pi) (i = 0 to 3, 6 to 10) ................160 11.3.12 Port Pi Direction Register (PDi) (i = 0 to 3, 6 to 10) ............161 11.4 Peripheral Function I/O......................
Page 13 12.6.2 Relocatable Vector Tables ....................183 12.7 Interrupt Control........................185 12.7.1 Maskable Interrupt Control ....................185 12.7.2 Interrupt Sequence ......................186 12.7.3 Interrupt Response Time ....................187 12.7.4 Variation of IPL When Interrupt Request is Accepted ............. 187 12.7.5 Saving Registers ......................188 12.7.6 Returning from an Interrupt Routine ................
Page 14 13.6 Notes on the Watchdog Timer ....................211 14. DMAC....................212 14.1 Introduction ..........................212 14.2 Registers........................... 214 14.2.1 DMAi Source Pointer (SARi) (i = 0 to 3) ................215 14.2.2 DMAi Destination Pointer (DARi) (i = 0 to 3) ..............215 14.2.3 DMAi Transfer Counter (TCRi) (i = 0 to 3) ...............
Page 15 15.3.1 Common Operations ....................... 246 15.3.2 Timer Mode ........................248 15.3.3 Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing) ....252 15.3.4 Event Counter Mode (When Processing Two-Phase Pulse Signal) ........ 256 15.3.5 One-Shot Timer Mode ..................... 261 15.3.6 Pulse Width Modulation (PWM) Mode ................
Page 16 17. Three-Phase Motor Control Timer Function ......... 304 17.1 Introduction ..........................304 17.2 Registers........................... 308 17.2.1 Timer B2 Register (TB2) ....................309 17.2.2 Timer Ai, Ai-1 Register (TAi, TAi1) (i = 1, 2, 4) ..............309 17.2.3 Three-Phase PWM Control Register 0 (INVC0) .............. 310 17.2.4 Three-Phase PWM Control Register 1 (INVC1) ..............
Page 17 18.2.13 Waveform Output Master Enable Register (G1OER) ............362 18.2.14 Timer S I/O Control Register 0 (G1IOR0) ................ 363 18.2.15 Timer S I/O Control Register 1 (G1IOR1) ................ 364 18.2.16 Interrupt Request Register (G1IR) ................... 365 18.2.17 Interrupt Enable Register 0 (G1IE0) ................366 18.2.18 Interrupt Enable Register 1 (G1IE1) ................
Page 18 20.2.3 Real-Time Clock Hour Data Register (RTCHR) .............. 409 20.2.4 Real-Time Clock Day Data Register (RTCWK) ............... 410 20.2.5 Real-Time Clock Control Register 1 (RTCCR1) ...............411 20.2.6 Real-Time Clock Control Register 2 (RTCCR2) .............. 413 20.2.7 Real-Time Clock Count Source Select Register (RTCCSR) ........... 415 20.2.8 Real-Time Clock Second Compare Data Register (RTCCSEC) ........
Page 19 21.4 Interrupts........................... 493 21.4.1 Interrupt Related Registers ....................493 21.4.2 Reception Interrupt ......................494 21.5 Notes on Serial Interface UARTi (i = 0 to 4) ................495 21.5.1 Common Notes on Multiple Modes ................. 495 21.5.2 Clock Synchronous Serial I/O Mode ................495 21.5.3 Special Mode 1 (I C Mode) .....................
Page 20 23.1.3 CAN0 Bit Configuration Register (C0BCR) ..............555 23.1.4 CAN0 Mask Register k (C0MKRk) (k = 0 to 7) ..............557 23.1.5 CAN0 FIFO Received ID Compare Register n (C0FIDCR0 to C0FIDCR1) (n = 0, 1) ..558 23.1.6 CAN0 Mask Invalid Register (C0MKIVLR) ..............560 23.1.7 CAN0 Mailbox Register j (C0MBj) (j = 0 to 31) ..............
Page 21 24. A/D Converter..................616 24.1 Introduction ..........................616 24.2 Registers........................... 618 24.2.1 Open-Circuit Detection Assist Function Register (AINRST) ..........619 24.2.2 A/D Register i (ADi) (i = 0 to 7) ..................620 24.2.3 A/D Control Register 2 (ADCON2) .................. 621 24.2.4 A/D Control Register 0 (ADCON0) ..................
Page 22 25.3.2 CRC Snoop ........................645 26. Flash Memory..................648 26.1 Introduction ..........................648 26.2 Memory Map..........................650 26.3 Registers........................... 651 26.3.1 Flash Memory Control Register 0 (FMR0) ............... 651 26.3.2 Flash Memory Control Register 1 (FMR1) ............... 654 26.3.3 Flash Memory Control Register 2 (FMR2) ............... 655 26.3.4 Flash Memory Control Register 3 (FMR3) ...............
Page 23 27. Electrical Characteristics ..............702 27.1 Electrical Characteristics (J-Version, Common to 3 V and 5 V)..........702 27.1.1 Absolute Maximum Rating ....................702 27.1.2 Recommended Operating Conditions ................703 27.1.3 A/D Conversion Characteristics ..................705 27.1.4 Flash Memory Electrical Characteristics ................. 706 27.1.5 Voltage Detector and Power Supply Circuit Electrical Characteristics ......
Page 24 28.5.3 CPU Clock ........................765 28.5.4 Oscillator Stop/Restart Detect Function ................765 28.5.5 PLL Frequency Synthesizer .................... 766 28.6 Notes on Power Control......................767 28.6.1 CPU Clock ........................767 28.6.2 Wait Mode ........................767 28.6.3 Stop Mode ........................767 28.6.4 Low Current Consumption Read Mode ................
Page 25 28.14.1 Register Access ....................... 783 28.14.2 Changing the G1IR Register ................... 783 28.14.3 Changing Registers ICOCiIC (i = 0, 1) ................785 28.14.4 Output Waveform During the Base Timer Reset with the BTS bit ........785 28.14.5 OUTC1_0 Pin Output During the Base Timer Reset with the G1PO0 register ....785 28.14.6 Interrupt Request When Selecting Time Measurement Function ........
Page 26 Quick Reference Only one page number is listed for each register. Refer to the REGISTER INDEX for more details. Address Register Symbol Page Address Register Symbol Page INT4 Interrupt Control Register 0049h INT4IC 0000h UART2 Bus Collision Detection Interrupt 0001h BCNIC, 004Ah Control Register, Task Monitoring Timer...
Page 27 Address Register Symbol Page Address Register Symbol Page 01C0h 0180h Timer B0-1 Register TB01 01C1h 0181h DMA0 Source Pointer SAR0 01C2h 0182h Timer B1-1 Register TB11 01C3h 0183h 01C4h 0184h Timer B2-1 Register TB21 01C5h 0185h DMA0 Destination Pointer DAR0 Pulse Period/Pulse Width Measurement 0186h 01C6h...
Page 28 Address Register Symbol Page Address Register Symbol Page 0200h 0244h 0201h 0245h 0202h 0246h 0203h 0247h 0204h 0248h UART0 Transmit/Receive Mode Register U0MR 0205h Interrupt Source Select Register 3 IFSR3A 0249h UART0 Bit Rate Register U0BRG 0206h Interrupt Source Select Register 2 IFSR2A 024Ah UART0 Transmit Buffer Register...
Page 29 Address Register Symbol Page Address Register Symbol Page 0288h 02C0h Time Measurement Register 0, G1TM0, Waveform Generation Register 0 G1PO0 0289h 02C1h 028Ah 02C2h Time Measurement Register 1, G1TM1, Waveform Generation Register 1 G1PO1 028Bh 02C3h 028Ch 02C4h Time Measurement Register 2, G1TM2, Waveform Generation Register 2 G1PO2...
Page 30 Address Register Symbol Page Address Register Symbol Page 0300h 033Bh Timer B0 Mode Register TB0MR 0301h 033Ch Timer B1 Mode Register TB1MR 0302h 033Dh Timer B2 Mode Register TB2MR Timer A1-1 Register TA11 0303h 033Eh Timer B2 Special Mode Register TB2SC 0304h 033Fh...
Page 31 Address Register Symbol Page Address Register Symbol Page 0377h 03B3h 0378h 03B4h SFR Snoop Address Register CRCSAR 0379h 03B5h 037Ah 03B6h CRC Mode Register CRCMR 037Bh 03B7h 037Ch Count Source Protection Mode Register CSPR 03B8h 037Dh Watchdog Timer Refresh Register WDTR 03B9h 037Eh...
Page 32 Address Register Symbol Page Address Register Symbol Page 03F0h Port P8 Register D500h 03F1h Port P9 Register D501h CAN0 Mailbox 0: Message Identifier 03F2h Port P8 Direction Register D502h 03F3h Port P9 Direction Register D503h 03F4h Port P10 Register D504h 03F5h D505h CAN0 Mailbox 0: Data Length...
Page 33 Address Register Symbol Page Address Register Symbol Page D540h D580h D541h D581h CAN0 Mailbox 4: Message Identifier CAN0 Mailbox 8: Message Identifier D542h D582h D543h D583h D544h D584h D545h D585h CAN0 Mailbox 4: Data Length CAN0 Mailbox 8: Data Length D546h D586h D547h...
Page 34 Address Register Symbol Page Address Register Symbol Page D5C0h D600h D5C1h D601h CAN0 Mailbox 12: Message Identifier CAN0 Mailbox 16: Message Identifier D5C2h D602h D5C3h D603h D5C4h D604h D5C5h CAN0 Mailbox 12: Data Length D605h CAN0 Mailbox 16: Data Length D5C6h D606h D5C7h...
Page 35 Address Register Symbol Page Address Register Symbol Page D640h D680h D641h D681h CAN0 Mailbox 20: Message Identifier CAN0 Mailbox 24: Message Identifier D642h D682h D643h D683h D644h D684h D645h CAN0 Mailbox 20: Data Length D685h CAN0 Mailbox 24: Data Length D646h D686h D647h...
Page 36 Address Register Symbol Page Address Register Symbol Page D6C0h D700h D6C1h D701h C0MKR0 CAN0 Mailbox 28: Message Identifier CAN0 Mask Register 0 D6C2h D702h D6C3h D703h D6C4h D704h D6C5h CAN0 Mailbox 28: Data Length D705h C0MKR1 CAN0 Mask Register 1 D6C6h D706h D6C7h...
Page 37 Address Register Symbol Page C0MCTL16 D7B0h CAN0 Message Control Register 16 D7B1h CAN0 Message Control Register 17 C0MCTL17 C0MCTL18 D7B2h CAN0 Message Control Register 18 C0MCTL19 D7B3h CAN0 Message Control Register 19 C0MCTL20 D7B4h CAN0 Message Control Register 20 C0MCTL21 D7B5h CAN0 Message Control Register 21 C0MCTL22...
Page 38 M16C/5L Group, M16C/56 Group R01UH0127EJ0110 RENESAS MCU Rev.1.10 Sep 01, 2011 Overview Features The M16C/5L and M16C/56 Group’s microcomputers (MCUs) are single-chip control units that utilize high-performance silicon gate CMOS technology with the M16C/60 Series CPU core. The M16C/5L Group and M16C/56 Group are available in 64-pin and 80-pin plastic molded LQFP packages. The MCUs employ sophisticated instructions for a high level of efficiency and they are capable of executing instructions at high speed.
Page 39 M16C/5L Group, M16C/56 Group 1. Overview Specifications Table 1.1 to Table 1.4 list specifications of the M16C/5L Group, M16C/56 Group. Table 1.1 Specifications (80-pin Package) (1/2) Item Function Specification M16C/60 Series CPU Core (Multiplier: 16 × 16 32 bits, Multiply-accumulate unit: 16 ×...
Page 40 M16C/5L Group, M16C/56 Group 1. Overview Table 1.2 Specifications (80-pin Package) (2/2) Item Function Specification • 1 circuit • CRC Calculator CRC-CCITT (X + 1), CRC-16 (X + 1) compliant • MSB/LSB selectable CAN Module 32-slot message buffer × 1 channel (M16C/5L Group only) •...
Page 41 M16C/5L Group, M16C/56 Group 1. Overview Table 1.3 Specifications (64-pin Package) (1/2) Item Function Specification M16C/60 Series CPU Core (Multiplier: 16 × 16 32 bits, Multiply-accumulate unit: 16 × 16 + 32 32 bits)) • Basic instructions: 91 Central processing unit •...
Page 42 M16C/5L Group, M16C/56 Group 1. Overview Table 1.4 Specifications (64-pin Package) (2/2) Item Function Specification • 1 circuit • CRC Calculator CRC-CCITT (X + 1), CRC-16 (X + 1) compliant • MSB/LSB selectable CAN Module 32-slot message buffer × 1 channel (M16C/5L Group only) •...
Page 43 M16C/5L Group, M16C/56 Group 1. Overview Product List Table 1.5 and Table 1.6 list product information on the M16C/5L Group, M16C/56 Group. Figure 1.1 shows part numbers, memory sizes, and packages. Figure 1.2 shows marking drawing (top view). Table 1.5 Product List of M16C/5L Group As of September 2011 ROM Capacity...
Page 44 Group Name 5L: M16C/5L Group 56: M16C/56 Group 16-bit MCU Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Correspondence of Part Number, Memory Size, and Package M 1 6 C Part number (See Figure 1.1 “Correspondence of Part Number, Memory Size, and Package”.)
Page 45 M16C/5L Group, M16C/56 Group 1. Overview Block Diagram Figure 1.3 shows a block diagram of M16C/5L Group, M16C/56 Group 80-pin package. Figure 1.4 shows a block diagram of the M16C/5L Group, M16C/56 Group 64-pin package. I/O ports Port P0 Port P1 Port P2 Port P3 Peripherals...
Page 46 M16C/5L Group, M16C/56 Group 1. Overview I/O ports Port P0 Port P1 Port P2 Port P3 Peripherals UART/clock synchronous Timer (16 bits) Clock generator serial interface Output (timer A): 5 XIN-XOUT (4 channels) XCIN-XCOUT Input (timer B): 3 40 MHz on-chip oscillator 125 kHz on-chip oscillator DMAC Three-phase motor control...
Page 47 M16C/5L Group, M16C/56 Group 1. Overview Pin Assignments Figure 1.5 shows the pin assignments for 80-pin package and Figure 1.6 shows the pin assignments for 64-pin package. P0_6 / AN0_6 P6_3 / TXD0 P0_5 / AN0_5 P3_0 / CLK3 P0_4 / AN0_4 P3_1 / RXD3 P0_3 / AN0_3 P3_2 / TXD3...
Page 48 M16C/5L Group, M16C/56 Group 1. Overview Table 1.7 Pin Names, 80-Pin Package (1/2) Multi- Inter- master Control Analog Port rupt Timer Pin Timer S Pin UART/CAN Pin C-bus P9_5 CLK4 AN2_5 P9_3 AN2_4 CTX0 P9_2 TB2IN AN3_2 CRX0 P9_1 TB1IN AN3_1 CLKOUT P9_0 TB0IN...
Page 49 M16C/5L Group, M16C/56 Group 1. Overview Table 1.8 Pin Names, 80-Pin Package (2/2) Multi- Inter- master Control Analog Port rupt Timer Pin Timer S Pin UART/CAN Pin C-bus P6_2 RXD0 P6_1 CLK0 CTS0/RTS0 P6_0 RTCOUT P2_7 OUTC1_7/INPC1_7 P2_6 OUTC1_6/INPC1_6 P2_5 OUTC1_5/INPC1_5 P2_4 OUTC1_4/INPC1_4...
Page 50 M16C/5L Group, M16C/56 Group 1. Overview P0_2 / AN0_2 P3_0 / CLK3 P0_1 / AN0_1 P3_1 / RXD3 P0_0 / AN0_0 P3_2 / TXD3 P10_7 / AN_7 / KI3 P3_3 / CTS3 / RTS3 M16C/5L Group P10_6 / AN_6 / KI2 P6_4 / RTS1 / CTS1 M16C/56 Group P10_5 / AN_5 / KI1...
Page 51 M16C/5L Group, M16C/56 Group 1. Overview Table 1.9 Pin Names, 64-Pin Package (1/2) Multi- Inter- master Control Analog Port rupt Timer Pin Timer S Pin UART/CAN Pin C-bus P9_1 TB1IN AN3_1 CLKOUT P9_0 TB0IN AN3_0 CNVSS XCIN P8_7 XCOUT P8_6 RESET XOUT 10 VCC...
Page 52 M16C/5L Group, M16C/56 Group 1. Overview Table 1.10 Pin Names, 64-Pin Package (2/2) Multi- Inter- master Control Port rupt Timer Pin Timer S Pin UART/CAN Pin Analog Pin C-bus P2_3 OUTC1_3/INPC1_3 P2_2 OUTC1_2/INPC1_2 P2_1 OUTC1_1/INPC1_1 SCLMM P2_0 OUTC1_0/INPC1_0 SDAMM INT5 P1_7 INPC1_7 INT4...
Page 53 M16C/5L Group, M16C/56 Group 1. Overview Pin Functions Table 1.11 Pin Functions (64-Pin and 80-Pin Packages) (1/2) Signal Name Pin Name Description Power supply VCC, VSS Apply 3.0 to 5.5 V to VCC pin and 0 V to VSS pin. Analog power AVCC, Power supply for the A/D converter.
Page 54 M16C/5L Group, M16C/56 Group 1. Overview Table 1.12 Pin Functions (64-Pin and 80-Pin Packages) (2/2) Signal Name Pin Name Description Reference voltage VREF Reference voltage input for the A/D converter. input AN_0 to AN_7 AN0_0 to AN0_3 Analog input AN2_4 A/D converter AN3_0 to AN3_2 ADTRG...
Page 55 M16C/5L Group, M16C/56 Group 1. Overview Table 1.13 Pin Functions (80-Pin Package Only) Signal Name Pin Name Description Serial interface CLK4 Transfer clock I/O pin UART4 RXD4 Serial data input pin TXD4 Serial data output pin A/D converter AN0_4 to AN0_7 Analog input AN2_0 to AN2_3 AN2_5 to AN2_7...
Page 56 M16C/5L Group, M16C/56 Group 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a register bank, and there are two register banks. b8 b7 R0H (upper bits of R0) R0L (lower bits of R0)
Page 57 M16C/5L Group, M16C/56 Group 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2, and R3) R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can be split into upper (R0H/R1H) and lower (R0L/R1L) bits to be used separately as 8-bit data registers. R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers R2R0 and R3R1, respectively.
Page 58 M16C/5L Group, M16C/56 Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I Flag) The I flag enables maskable interrupts. Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0 when an interrupt request is accepted.
Page 59 M16C/5L Group, M16C/56 Group 3. Memory Memory Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to 0D7FFh. Peripheral function control registers are located here. All blank spaces within SFRs are reserved, so do not access any blank spaces. The internal RAM is allocated from address 00400h to superior direction.
Page 60 M16C/5L Group, M16C/56 Group 3. Memory 00000h SFRs 00400h Internal RAM XXXXXh Reserved 0D000h SFRs 0D800h Reserved 13000h On-chip debugger 0E000h Internal ROM monitor area (Data flash) 13FF0h 10000h Internal ROM Internal RAM User boot code area (Program ROM 2) 13FFFh Capacity XXXXXh...
Page 61 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Special Function Registers (SFRs) SFRs An SFR is a control register for a peripheral function. Table 4.1 SFR Information (1) Address Register Symbol Reset Value 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0000 1000b...
Page 62 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.2 SFR Information (2) Address Register Symbol Reset Value 0020h 0021h 0022h 40 MHz On-Chip Oscillator Control Register 0 FRA0 XXXX XX00b 0023h 0024h 40 MHz On-Chip Oscillator Control Register 2 FRA2 0XX0 X000b 0025h...
Page 63 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.3 SFR Information (3) Address Register Symbol Reset Value 0040h 0041h 0042h 0043h INT3 Interrupt Control Register 0044h INT3IC XX00 X000b 0045h 0046h 0047h INT5 Interrupt Control Register 0048h INT5IC XX00 X000b INT4 Interrupt Control Register 0049h...
Page 64 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.4 SFR Information (4) Address Register Symbol Reset Value 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h DMA2 Interrupt Control Register DM2IC XXXX X000b 006Ah DMA3 Interrupt Control Register DM3IC XXXX X000b 006Bh...
Page 65 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.5 SFR Information (5) Address Register Symbol Reset Value 0180h 0181h DMA0 Source Pointer SAR0 0182h 0183h 0184h 0185h DMA0 Destination Pointer DAR0 0186h 0187h 0188h DMA0 Transfer Counter TCR0 0189h 018Ah 018Bh...
Page 66 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.6 SFR Information (6) Address Register Symbol Reset Value 01B0h 01B1h DMA3 Source Pointer SAR3 01B2h 01B3h 01B4h 01B5h DMA3 Destination Pointer DAR3 01B6h 01B7h 01B8h DMA3 Transfer Counter TCR3 01B9h 01BAh 01BBh...
Page 67 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.7 SFR Information (7) Address Register Symbol Reset Value 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h Task Monitor Timer Register TMOS 01F1h 01F2h...
Page 68 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.8 SFR Information (8) Address Register Symbol Reset Value 0210h 0211h Address Match Interrupt Register 0 RMAD0 0212h 0213h 0214h 0215h Address Match Interrupt Register 1 RMAD1 0216h 0217h 0218h 0219h Address Match Interrupt Register 2 RMAD2...
Page 69 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.9 SFR Information (9) Address Register Symbol Reset Value 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h UART0 Transmit/Receive Mode Register U0MR 0249h UART0 Bit Rate Register U0BRG 024Ah UART0 Transmit Buffer Register U0TB 024Bh...
Page 70 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.10 SFR Information (10) Address Register Symbol Reset Value 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h...
Page 71 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.11 SFR Information (11) Address Register Symbol Reset Value 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h UART3 Transmit/Receive Mode Register U3MR 02A9h UART3 Bit Rate Register U3BRG 02AAh UART3 Transmit Buffer Register U3TB 02ABh...
Page 72 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.12 SFR Information (12) Address Register Symbol Reset Value 02D0h Waveform Generation Control Register 0 G1POCR0 0X00 XX00b 02D1h Waveform Generation Control Register 1 G1POCR1 0X00 XX00b 02D2h Waveform Generation Control Register 2 G1POCR2 0X00 XX00b 02D3h...
Page 73 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.13 SFR Information (13) Address Register Symbol Reset Value 0300h 0301h 0302h Timer A1-1 Register TA11 0303h 0304h Timer A2-1 Register TA21 0305h 0306h Timer A4-1 Register TA41 0307h 0308h Three-Phase PWM Control Register 0 INVC0 0309h...
Page 74 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.14 SFR Information (14) Address Register Symbol Reset Value 0330h Timer B0 Register 0331h 0332h Timer B1 Register 0333h 0334h Timer B2 Register 0335h 0336h Timer A0 Mode Register TA0MR 0337h Timer A1 Mode Register TA1MR...
Page 75 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.15 SFR Information (15) Address Register Symbol Reset Value 0360h Pull-Up Control Register 0 PUR0 0361h Pull-Up Control Register 1 PUR1 0362h Pull-Up Control Register 2 PUR2 0363h 0364h 0365h 0366h Port Control Register 0XX0 0XX0b...
Page 76 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.16 SFR Information (16) Address Register Symbol Reset Value 0390h DMA2 Source Select Register DM2SL 0391h 0392h DMA3 Source Select Register DM3SL 0393h 0394h 0395h 0396h 0397h 0398h DMA0 Source Select Register DM0SL 0399h 039Ah...
Page 77 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.17 SFR Information (17) Address Register Symbol Reset Value 03C0h XXXX XXXXb A/D Register 0 03C1h 0000 00XXb 03C2h XXXX XXXXb A/D Register 1 03C3h 0000 00XXb 03C4h XXXX XXXXb A/D Register 2 03C5h 0000 00XXb...
Page 78 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.18 SFR Information (18) Address Register Symbol Reset Value 03F0h Port P8 Register 03F1h Port P9 Register 03F2h Port P8 Direction Register 03F3h Port P9 Direction Register 000X 0000b 03F4h Port P10 Register 03F5h 03F6h...
Page 79 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.19 SFR Information (19) Address Register Symbol Reset Value D500h D501h CAN0 Mailbox 0: Message Identifier D502h D503h D504h D505h CAN0 Mailbox 0: Data Length D506h D507h C0MB0 D508h D509h CAN0 Mailbox 0: Data Field D50Ah D50Bh...
Page 80 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.20 SFR Information (20) Address Register Symbol Reset Value D530h D531h CAN0 Mailbox 3: Message Identifier D532h D533h D534h D535h CAN0 Mailbox 3: Data Length D536h D537h C0MB3 D538h D539h CAN0 Mailbox 3: Data Field D53Ah D53Bh...
Page 81 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.21 SFR Information (21) Address Register Symbol Reset Value D560h D561h CAN0 Mailbox 6: Message Identifier D562h D563h D564h D565h CAN0 Mailbox 6: Data Length D566h D567h C0MB6 D568h D569h CAN0 Mailbox 6: Data Field D56Ah D56Bh...
Page 82 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.22 SFR Information (22) Address Register Symbol Reset Value D590h D591h CAN0 Mailbox 9: Message Identifier D592h D593h D594h D595h CAN0 Mailbox 9: Data Length D596h D597h C0MB9 D598h D599h CAN0 Mailbox 9: Data Field D59Ah D59Bh...
Page 83 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.23 SFR Information (23) Address Register Symbol Reset Value D5C0h D5C1h CAN0 Mailbox 12: Message Identifier D5C2h D5C3h D5C4h D5C5h CAN0 Mailbox 12: Data Length D5C6h D5C7h C0MB12 D5C8h D5C9h CAN0 Mailbox 12: Data Field D5CAh D5CBh...
Page 84 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.24 SFR Information (24) Address Register Symbol Reset Value D5F0h D5F1h CAN0 Mailbox 15: Message Identifier D5F2h D5F3h D5F4h D5F5h CAN0 Mailbox 15: Data Length D5F6h D5F7h C0MB15 D5F8h D5F9h CAN0 Mailbox 15: Data Field D5FAh D5FBh...
Page 85 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.25 SFR Information (25) Address Register Symbol Reset Value D620h D621h CAN0 Mailbox 18: Message Identifier D622h D623h D624h D625h CAN0 Mailbox 18: Data Length D626h D627h C0MB18 D628h D629h CAN0 Mailbox 18: Data Field D62Ah D62Bh...
Page 86 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.26 SFR Information (26) Address Register Symbol Reset Value D650h D651h CAN0 Mailbox 21: Message Identifier D652h D653h D654h D655h CAN0 Mailbox 21: Data Length D656h D657h C0MB21 D658h D659h CAN0 Mailbox 21: Data Field D65Ah D65Bh...
Page 87 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.27 SFR Information (27) Address Register Symbol Reset Value D680h D681h CAN0 Mailbox 24: Message Identifier D682h D683h D684h D685h CAN0 Mailbox 24: Data Length D686h D687h C0MB24 D688h D689h CAN0 Mailbox 24: Data Field D68Ah D68Bh...
Page 88 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.28 SFR Information (28) Address Register Symbol Reset Value D6B0h D6B1h CAN0 Mailbox 27: Message Identifier D6B2h D6B3h D6B4h D6B5h CAN0 Mailbox 27: Data Length D6B6h D6B7h C0MB27 D6B8h D6B9h CAN0 Mailbox 27: Data Field D6BAh D6BBh...
Page 89 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.29 SFR Information (29) Address Register Symbol Reset Value D6E0h D6E1h CAN0 Mailbox 30: Message Identifier D6E2h D6E3h D6E4h D6E5h CAN0 Mailbox 30: Data Length D6E6h D6E7h C0MB30 D6E8h D6E9h CAN0 Mailbox 30: Data Field D6EAh D6EBh...
Page 90 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.30 SFR Information (30) Address Register Symbol Reset Value D710h D711h CAN0 Mask Register 4 C0MKR4 D712h D713h D714h D715h CAN0 Mask Register 5 C0MKR5 D716h D717h D718h D719h CAN0 Mask Register 6 C0MKR6 D71Ah D71Bh...
Page 91 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.31 SFR Information (31) Address Register Symbol Reset Value D7B0h CAN0 Message Control Register 16 C0MCTL16 D7B1h CAN0 Message Control Register 17 C0MCTL17 D7B2h CAN0 Message Control Register 18 C0MCTL18 D7B3h CAN0 Message Control Register 19 C0MCTL19...
Page 92 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Notes on SFRs 4.2.1 Register Settings Table 4.32 lists Registers with Write-Only Bits and registers whose function differs between reading and writing. Set these registers with immediate values. Do not use read-modify-write instructions. When establishing the next value by altering the existing value, write the existing value to the RAM as well as to the register.
Page 93 M16C/5L Group, M16C/56 Group 4. Special Function Registers (SFRs) Table 4.33 Read-Modify-Write Instructions Function Mnemonic Transfer MOV Dir Bit processing BCLR, BM Cnd , BNOT, BSET, BTSTC, and BTSTS Shifting ROLC, RORC, ROT, SHA, and SHL ABS, ADC, ADCF, ADD, DEC, DIV, DIVU, DIVX, EXTS, INC, MUL, MULU, NEG, Arithmetic operation SBB, and SUB Decimal operation...
Page 94 M16C/5L Group, M16C/56 Group 5. Protection Protection Introduction In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Register Table 5.1 Registers Address Register Symbol Reset Value 000Ah Protect Register PRCR...
Page 95 M16C/5L Group, M16C/56 Group 5. Protection PRC6, PRC3, PRC1, PRC0 (Protect bits 6, 3, 1, 0) (b6, b3, b1, b0) When setting bits PRC6, PRC3, PRC1, and PRC0 to 1 (write enabled), these bits remain 1 (write enabled). To change registers protected by these bits, follow these steps: Set the PRCi bit to 1.
Page 96 M16C/5L Group, M16C/56 Group 5. Protection Notes on Protection After setting the PRC2 bit to 1 (write enabled), by writing to a given SFR, the PRC2 bit becomes 0 (write disabled). Change the registers protected by the PRC2 bit in the next instruction after setting the PRC2 bit to 1.
Page 97 M16C/5L Group, M16C/56 Group 6. Resets Resets Introduction The following resets can be used to reset the MCU: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 2 reset, oscillator stop detect reset, watchdog timer reset, and software reset. Table 6.1 lists the Types of Resets and Figure 6.1 shows the Reset Circuit Block Diagram.
Page 98 M16C/5L Group, M16C/56 Group 6. Resets Table 6.2 Classification of SFRs Which are Reset Register and Bit SFR (A) OSDR bit in the RSTFR register Registers VCR1, VCR2, and VW0C SFR (B) Bits VW2C2 and VW2C3 in the VW2C register SFR (C) VD2LS register SFR (D)
Page 99 M16C/5L Group, M16C/56 Group 6. Resets Registers Refer to 7. “Voltage Detector” for registers used with the voltage monitor 0 reset, and voltage monitor 2 reset. Refer to 13. “Watchdog Timer” for registers used with the watchdog timer reset. Refer to 8.7 “Oscillator Stop/Restart Detect Function”...
Page 100 M16C/5L Group, M16C/56 Group 6. Resets 6.2.2 Reset Source Determine Register (RSTFR) Reset Source Determine Register b6 b5 b4 Symbol Address Reset Value See Table 6.5. RSTFR 0018h Bit Name Function Bit Symbol — If necessary, set to 0. The read value is Reserved bit undefined.
Page 101 M16C/5L Group, M16C/56 Group 6. Resets Optional Function Select Area In the optional function select area, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected. The optional function select area is not an SFR, and therefore cannot be rewritten by a program. Set an appropriate value when writing a program to flash memory.
Page 102 M16C/5L Group, M16C/56 Group 6. Resets ROMCR (ROM code protect cancel bit) (b2) ROMCP1 (ROM code protect bit) (b3) These bits prevent the flash memory from being read or changed in parallel I/O mode. Table 6.6 ROM Code Protection Bit Setting ROM Code Protection ROMCR bit ROMCP1 bit...
Page 103 M16C/5L Group, M16C/56 Group 6. Resets Operations 6.4.1 Status after Reset The status of SFRs after reset depends on the reset type. See the Reset Value column in 4. “Special Function Registers (SFRs)”. Table 6.7 lists Pin Status When RESET Pin Level is Low, Figure 6.2 shows CPU Register Status after Reset, and Figure 6.3 shows Reset Sequence.
Page 104 M16C/5L Group, M16C/56 Group 6. Resets td(P-R) Must be equal to or more than x 20 cycles fOCO-S × 60 cycles (max.) RESET tps + fOCO-S BCLK Content of reset vector FFFFCh Address FFFFEh Figure 6.3 Reset Sequence R01UH0127EJ0110 Rev.1.10 Page 67 of 803 Sep 01, 2011...
Page 105 M16C/5L Group, M16C/56 Group 6. Resets 6.4.2 Hardware Reset This reset is triggered by the RESET pin. When the power supply voltage meets the recommended operating conditions, the MCU resets the pins, CPU, and SFRs when a low-level signal is applied to the RESET pin.
Page 106 M16C/5L Group, M16C/56 Group 6. Resets 6.4.3 Power-On Reset Function When the RESET pin is connected to VCC via a pull-up resistor, and the VCC voltage level rises while the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets the pins, CPU, and SFRs.
Page 107 M16C/5L Group, M16C/56 Group 6. Resets 6.4.4 Voltage Monitor 0 Reset This reset is triggered by the MCU's on-chip voltage detector 0. The voltage detector 0 monitors the voltage applied to the VCC pin (Vdet0). The MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC pin drops to Vdet0 or below.
Page 108 M16C/5L Group, M16C/56 Group 6. Resets 6.4.8 Software Reset The MCU resets the pins, CPU, and SFRs when the PM03 bit in the PM0 register is 1 (MCU reset). Then the MCU executes the program at the address determined by the reset vector. fOCO-S divided by 8 is automatically selected as the CPU clock after reset.
Page 109 M16C/5L Group, M16C/56 Group 6. Resets Notes on Resets 6.5.1 Power Supply Rising Gradient When supplying power to the MCU, make sure that the power supply voltage applied to the VCC pin meets the SVCC conditions. Standard Symbol Parameter Unit Min.
Page 110 M16C/5L Group, M16C/56 Group 7. Voltage Detector Voltage Detector Introduction The voltage detector monitors the voltage applied to the VCC pin. This circuit can be programmed to monitor the VCC input voltage. Voltage monitor 0 reset, voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used.
Page 111 M16C/5L Group, M16C/56 Group 7. Voltage Detector Registers Table 7.2 Registers Address Register Name Register Symbol Reset Value Voltage Detector 2 Flag Register (1, 5) 0019h VCR1 0000 1000b (2, 5) 000X 0000b 001Ah Voltage Detector Operation Enable Register VCR2 (3, 5) 001X 0000b 0026h...
Page 112 M16C/5L Group, M16C/56 Group 7. Voltage Detector 7.2.1 Voltage Detector 2 Flag Register (VCR1) Voltage Detector 2 Flag Register b6 b5 b4 Reset Value Symbol Address 0000 1000b (hardware reset, power-on VCR1 0019h reset, voltage monitor 0 reset) Bit Symbol Bit Name Function —...
Page 113 M16C/5L Group, M16C/56 Group 7. Voltage Detector 7.2.2 Voltage Detector Operation Enable Register (VCR2) Voltage Detector Operation Enable Register b6 b5 b4 Symbol Address Reset Value 000X 0000b 001Ah VCR2 001X 0000b Bit Symbol Bit Name Function — Reserved bits Set to 0 (b3-b0) —...
Page 114 M16C/5L Group, M16C/56 Group 7. Voltage Detector 7.2.3 Voltage Monitor Function Select Register (VWCE) Voltage Monitor Function Select Register b6 b5 b4 Symbol Address Reset Value VWCE 0026h Bit Symbol Bit Name Function 0: Voltage monitor 2 disabled Voltage monitor 2 enable bit VW12E 1: Voltage monitor 2 enabled —...
Page 115 M16C/5L Group, M16C/56 Group 7. Voltage Detector 7.2.4 Voltage Detector 2 Level Select Register (VD2LS) Voltage Detector 2 Level Select Register b6 b5 b4 Symbol Address Reset Value 0028h 0000 0100b (Hardware reset, power-on reset, voltage VD2LS monitor 0 reset, voltage monitor 2 reset) Bit Symbol Bit Name Function...
Page 116 M16C/5L Group, M16C/56 Group 7. Voltage Detector 7.2.5 Voltage Monitor 0 Control Register (VW0C) Voltage Monitor 0 Control Register b6 b5 b4 Reset Value Symbol Address 1100 1X10b VW0C 002Ah 1100 1X11b Bit Symbol Bit Name Function Voltage monitor 0 reset 0 : Disabled VW0C0 enable bit...
Page 117 M16C/5L Group, M16C/56 Group 7. Voltage Detector 7.2.6 Voltage Monitor 2 Control Register (VW2C) Voltage Monitor 2 Control Register b7 b6 b5 b4 Symbol Address Reset Value 1000 0X10b VW2C 002Ch (hardware reset, power-on reset, voltage monitor 0 reset) Bit Symbol Bit Name Function Voltage monitor 2 interrupt/...
Page 118 M16C/5L Group, M16C/56 Group 7. Voltage Detector VW2C2 (Voltage change detection flag) (b2) The VW2C2 bit is enabled when the VC27 bit in the VCR2 register is 1 (voltage detector 2 enabled). This bit does not change even if set to 1. Condition to become 0: •...
Page 119 M16C/5L Group, M16C/56 Group 7. Voltage Detector Optional Function Select Area In the optional function select area, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected. The optional function select area is not an SFR, and therefore cannot be rewritten by a program. Set an appropriate value when writing a program to flash memory.
Page 120 M16C/5L Group, M16C/56 Group 7. Voltage Detector Operations 7.4.1 Digital Filter A digital filter can be used to monitor VCC input voltage. For voltage detector 2, the digital filter is enabled when the VW2C1 bit in the VW2C register is set to 0 (digital filter enabled). fOCO-S divided by 1, 2, 4, or 8 is selected as a sampling clock.
Page 121 M16C/5L Group, M16C/56 Group 7. Voltage Detector 7.4.2 Voltage Detector 0 When the VC25 bit in the VCR2 register is 1 (voltage detector 0 enabled), voltage detector 0 monitors the voltage applied to the VCC pin and detects whether the voltage rises through or falls through Vdet0. Voltage detector 0 VC25 Voltage monitor 0 reset generator...
Page 122 M16C/5L Group, M16C/56 Group 7. Voltage Detector 7.4.2.1 Voltage Monitor 0 Reset Table 7.5 lists Steps to Set Voltage Monitor 0 Reset Related Bits. Table 7.5 Steps to Set Voltage Monitor 0 Reset Related Bits Step Set the VC25 bit in the VCR2 register to 1 (voltage detector 0 enabled). Wait for td(E-A).
Page 123 M16C/5L Group, M16C/56 Group 7. Voltage Detector 7.4.3 Voltage Detector 2 When the VW12E bit in the VWCE register is 1 (voltage monitor 2 enabled) and the VC27 bit in the VCR2 register is 1 (voltage detector 2 enabled), voltage detector 2 monitors the voltage applied to the VCC pin and detects whether the voltage rises through or falls through Vdet2.
Page 124 M16C/5L Group, M16C/56 Group 7. Voltage Detector 7.4.3.2 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 7.6 lists Procedure for Setting Voltage Monitor 2 Interrupt/Reset Related Bits. Table 7.6 Procedure for Setting Voltage Monitor 2 Interrupt/Reset Related Bits When Using the Digital Filter When Not Using the Digital Filter Step...
Page 125 M16C/5L Group, M16C/56 Group 7. Voltage Detector Vdet2 VC13 bit Digital filter sampling clock × 3 cycles Digital filter sampling clock × 3 cycles VW2C2 bit Set to 0 by a program When the VW2C1 Set to 0 automatically by bit is 0 (digital filter Voltage monitor 2 enabled)
Page 126 M16C/5L Group, M16C/56 Group 7. Voltage Detector Interrupts The voltage monitor 2 interrupt is a non-maskable interrupt. The watchdog timer interrupt, oscillator stop/restart detect interrupt, and voltage monitor 2 interrupt share the same vector. When using some functions together, read the detect flags of the events in an interrupt processing program, and determine the source of the interrupt.
Page 127 M16C/5L Group, M16C/56 Group 8. Clock Generator Clock Generator Introduction The clock generator generates operating clocks for the CPU and peripheral functions. The following circuits are incorporated to generate the system clock signals. • Main clock oscillator • PLL frequency synthesizer •...
Page 128 M16C/5L Group, M16C/56 Group 8. Clock Generator CM01 to CM00 = 00b, PCLK5 = 0 I/O ports CM01 to CM00 = 01b, PCLK5 = 0 Sub clock oscillator CM01 to CM00 = 10b, PCLK5 = 0 XCIN XCOUT CLKOUT CM04 CM01 to CM00 = 00b, CM01 to CM00 = 11b, PCLK5 = 0 PCLK5 = 1...
Page 129 M16C/5L Group, M16C/56 Group 8. Clock Generator Table 8.2 I/O Pins Pin Name Function Input I/O pins for the main clock oscillator XOUT Output XCIN Input I/O pins for a sub clock oscillator XCOUT Output CLKOUT Output Clock output Note: Set the port direction bits which share pins to 0 (input mode).
Page 130 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.2.1 System Clock Control Register 0 (CM0) System Clock Control Register 0 b7 b6 b5 b4 Symbol Address Reset Value 0006h 0100 1000b Bit Symbol Bit Name Function CM00 0 : I/O port Clock output function select 1 : Output fC 0 : Output f8...
Page 131 M16C/5L Group, M16C/56 Group 8. Clock Generator CM02 (Wait mode peripheral function clock stop bit) (b2) This bit is used to stop the f1 peripheral function clock in wait mode. fC, fC32, fOCO-S, fOCO-F, and fOCO40M are not affected by the CM02 bit. When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM02 bit remains unchanged even when written to.
Page 132 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.2.2 System Clock Control Register 1 (CM1) System Clock Control Register 1 b6 b5 b4 Symbol Address Reset Value 0007h 0010 0000b Bit Symbol Bit Name Function 0 : Clock on CM10 All clock stop control bit 1 : All clocks off (stop mode) 0 : Main clock CM11...
Page 133 M16C/5L Group, M16C/56 Group 8. Clock Generator CM13 (XIN-XOUT feedback resistor select bit) (b3) The CM13 bit can be used when the main clock is not used at all, or when the externally generated clock is supplied to the XIN pin. When connecting a ceramic resonator or crystal between pins XIN and XOUT, set the CM13 bit to 0 (internal feedback resistor connected).
Page 134 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.2.3 Oscillation Stop Detection Register (CM2) Oscillation Stop Detection Register b6 b5 b4 Symbol Address Reset Value 000Ch 0X00 0010b Bit Symbol Bit Name Function 0: Oscillator stop/restart detect function Oscillator stop/restart detect disabled CM20 enable bit...
Page 135 M16C/5L Group, M16C/56 Group 8. Clock Generator CM22 (Oscillator stop/restart detect flag) (b2) Condition to become 0: • Set it to 0. Conditions to become 1: • Main clock stop is detected. • Main clock restart is detected. (The CM22 bit remains unchanged even if 1 is written.) When the CM22 bit changes state from 0 to 1, an oscillator stop/restart detect interrupt is generated.
Page 136 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.2.4 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register Symbol Address Reset Value b6 b5 b4 PCLKR 0012h 00000011b Bit Symbol Bit Name Function Timers A, B, S, multi-master I C-bus interface clock select bit 0: f2TIMAB/f2IIC PCLK0 (clock source for timers A , B, S,...
Page 137 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.2.5 PLL Control Register 0 (PLC0) PLL Control Register 0 Symbol Address Reset Value b7 b6 b5 b4 PLC0 001Ch 0X01 X010b Bit Symbol Bit Name Function b2 b1 b0 PLC00 0 : Do not set 1 : Multiply-by-2 0 : Multiply-by-4 PLL multiplying factor...
Page 138 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.2.6 Processor Mode Register 2 (PM2) Processor Mode Register 2 Reset Value b6 b5 b4 Symbol Address 001Eh XX00 0X01b Bit Symbol Bit Name Function — Reserved bit Set to 1. (b0) 0 : Clock is protected by PRCR register PM21 System clock protection bit 1 : Clock change disabled...
Page 139 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.2.7 40 MHz On-Chip Oscillator Control Register 0 (FRA0) 40 MHz On-Chip Oscillator Control Register 0 Reset Value b7 b6 b5 b4 Symbol Address FRA0 0022h XXXX XX00b Bit Symbol Bit Name Function 40 MHz on-chip oscillator start 0 : 40 MHz on-chip oscillator off FRA00...
Page 140 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.2.8 40 MHz On-Chip Oscillator Control Register 2 (FRA2) 40 MHz On-Chip Oscillator Control Register 2 b6 b5 b4 Symbol Address Reset Value FRA2 0024h 0XX0 X000b Bit Symbol Bit Name Function FRA20 b2 b1 b0 0 0 0: Divide-by-2 mode 40 MHz on-chip oscillator division...
Page 141 M16C/5L Group, M16C/56 Group 8. Clock Generator Clocks Generated by Clock Generators Clocks generated by the clock generators are described below. 8.3.1 Main Clock This clock is supplied by the main clock oscillator and used as a clock source for the CPU and peripheral function clocks.
Page 142 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.3.2 PLL Clock PLL clock is generated by the PLL frequency synthesizer. This clock is used as the clock source for the CPU and peripheral function clocks. After reset, the PLL frequency synthesizer is stopped. PLL clock is a clock which divides the main clock by the selected values of bits PLC05 to PLC04 in the PLC0 register, and then multiplied by the selected values of bits PLC02 to PLC00.
Page 143 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.3.3 fOCO40M fOCO40M is a 40 MHz clock (approx.) supplied by the 40 MHz on-chip oscillator. It is the clock source for φ AD in the A/D converter. Follow the steps below to start or stop the 40 MHz on-chip oscillator clock. Refer to 8.2 “Registers” for details on register and bit access.
Page 144 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.3.6 Sub Clock (fC) The sub clock is supplied by the sub clock oscillator. This clock is the clock source for count sources of the CPU clock, timer A, timer B, real-time clock. The sub clock oscillator is configured by connecting a crystal between pins XCIN and XCOUT.
Page 145 M16C/5L Group, M16C/56 Group 8. Clock Generator CPU Clock and Peripheral Function Clocks The CPU is run by the CPU clock, and the peripheral functions are run by the peripheral function clocks. 8.4.1 CPU Clock and BCLK The CPU clock is an operating clock for the CPU and watchdog timer. The main clock, PLL clock, fOCO-F, fOCO-S, or fC can be selected as the clock source for the CPU clock.
Page 146 M16C/5L Group, M16C/56 Group 8. Clock Generator Watchdog timer CPU clock BCLK CAN module Main clock Reset Voltage detector fOCO-S fC32 Timer A, timer B Timer S Task monitor timer Peripheral function clock Real-time clock PM25 UART0 to UART4 fOCO-F Multi-master I C-bus interface...
Page 147 M16C/5L Group, M16C/56 Group 8. Clock Generator Clock Output Function The f1, f8, f32 or fC clock can be output from the CLKOUT pin. Use bits CM01 to CM00 in the CM0 register, and the PCLK5 bit in the PCLKR register to select a clock. f8 has the same frequency as f1 divided by 8, and f32 has the same frequency as f1 divided by 32.
Page 148 M16C/5L Group, M16C/56 Group 8. Clock Generator Oscillator Stop/Restart Detect Function This function detects a stop/restart of the main clock oscillator. The oscillator stop/restart detect function can be enabled and disabled with the CM20 bit in the CM2 register. A reset or oscillator stop/restart detect interrupt is generated when an oscillator stop or restart is detected. Set the CM27 bit in the CM2 register to select the reset or interrupt.
Page 149 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.7.2 Operation When CM27 Bit is 1 (Oscillator Stop/Restart Detect Interrupt) When the CM20 bit is 1 (oscillator stop/restart detect function enabled), the system is placed in the state shown in Table 8.7 if the main clock detects oscillator stop or restart. The CM21 bit becomes 1 in high-speed, medium-speed, or low-speed mode.
Page 150 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.7.3 Using the Oscillator Stop/Restart Detect Function After oscillator stop is detected, if the main clock reoscillates, set the main clock back to the clock source for the CPU clock and peripheral functions by a program. Figure 8.6 shows the Switching from On-Chip Oscillator Clock to Main Clock.
Page 151 M16C/5L Group, M16C/56 Group 8. Clock Generator Notes on Clock Generator 8.9.1 Oscillator Using a Crystal or a Ceramic Resonator To connect a crystal/ceramic resonator follow the instructions below: • The oscillation characteristics are tied closely to the user’s board design. Perform a careful evaluation of the board before connecting an oscillator.
Page 152 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.9.2 Noise Countermeasure 8.9.2.1 Clock I/O Pin Wiring • Connect the shortest possible wiring to the clock I/O pin. • Connect (a) the capacitor's ground lead connected to the crystal/ceramic resonator, and (b) the MCU's VSS pin, with the shortest possible wiring (maximum 20 mm).
Page 153 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.9.2.3 Signal Line Whose Level Changes at a High-Speed For a signal line whose level changes at a high-speed, wire it as far away from the crystal/ceramic resonator and its wiring pattern as possible. Do not wire it across or extend it parallel to a clock- related signal line or other signal lines which are sensitive to noise.
Page 154 M16C/5L Group, M16C/56 Group 8. Clock Generator 8.9.5 PLL Frequency Synthesizer To use the PLL frequency synthesizer, stabilize the supply voltage within the acceptable range of power supply ripple. Table 8.9 Acceptable Range of Power Supply Ripple Standard Symbol Parameter Unit Min.
Page 155 M16C/5L Group, M16C/56 Group 9. Power Control Power Control Introduction This chapter describes how to reduce the amount of current consumption. Registers Refer to 8. “Clock Generator” for clock-related registers. Table 9.1 Registers Address Register Symbol Reset Value 0000 0001b (Other than user boot mode) 0220h Flash Memory Control Register 0...
Page 156 M16C/5L Group, M16C/56 Group 9. Power Control 9.2.1 Flash Memory Control Register 0 (FMR0) Flash Memory Control Register 0 b6 b5 b4 Symbol Address Reset Value 0000 0001b (other than user boot mode) FMR0 0220h 0010 0001b (user boot mode) Bit Symbol Bit Name Function...
Page 157 M16C/5L Group, M16C/56 Group 9. Power Control 9.2.2 Flash Memory Control Register 2 (FMR2) Flash Memory Control Register 2 b6 b5 b4 Symbol Address Reset Value FMR2 XXXX 0000b 0222h Bit Symbol Bit Name Function — Set to 0 Reserved bits (b1-b0) Slow read mode enable 0 : Disabled...
Page 158 M16C/5L Group, M16C/56 Group 9. Power Control Do not set the FMR23 bit to 1 (low current consumption read mode enabled) when any of the following occurs: • When the CM07 bit is 0 (main clock, PLL clock, or on-chip oscillator clock selected as CPU clock source).
Page 159 M16C/5L Group, M16C/56 Group 9. Power Control Clock The amount of current consumption correlates with the number of operating clocks and frequency. When there are fewer operating clocks and a lower frequency, current consumption will be low. Normal operating mode, wait mode, and stop mode can be used to control power consumption. All mode states, except wait mode and stop mode, are referred to as normal operating mode in this document.
Page 160 M16C/5L Group, M16C/56 Group 9. Power Control 9.3.1.4 125 kHz On-Chip Oscillator Mode The fOCO-S clock divided by 1 (no division), 2, 4, 8 or 16 is used as the CPU clock. f1 with the same frequency of the fOCO-S clock divided by 1 is used as the peripheral function clocks. When fC is supplied, fC and fC32 can be used as the peripheral function clocks.
Page 161 M16C/5L Group, M16C/56 Group 9. Power Control Table 9.2 Clocks in Normal Operating Mode Peripheral Clocks Mode CPU Clock fOCO-F fC, fC32 fOCO-S fOCO40M Main clock High-speed mode divided by 1 Main clock divided by 1 Main clock Medium-speed Enabled Enabled Enabled mode...
Page 162 M16C/5L Group, M16C/56 Group 9. Power Control Table 9.4 Selecting Clock Division Related Bits CM1 Register CM0 Register Division Bits CM17 to CM16 CM06 bit No division Divide-by-2 Divide-by-4 − Divide-by-8 Divide-by-16 − : Any value from 00b to 11b Notes: While in high-speed mode, medium-speed mode, PLL operating mode, 125 kHz on-chip oscillator mode, or 125 kHz on-chip oscillator low power mode.
Page 163 M16C/5L Group, M16C/56 Group 9. Power Control 9.3.2 Clock Mode Transition Procedure Figure 9.1 shows Clock Mode Transition. Arrows indicate possible mode transitions. Reset Normal Operating Mode Transitions to wait mode and stop mode enabled 125 kHz on-chip 40 MHz on-chip 125 kHz on-chip oscillator low power oscillator mode...
Page 164 M16C/5L Group, M16C/56 Group 9. Power Control a. Entering high-speed mode or medium-speed mode from 40 MHz on-chip oscillator mode, 125 kHz on-chip oscillator mode or low-speed mode (1) Start the main clock and wait until the oscillation stabilizes. Refer to 8.3.1 “Main Clock” for details.
Page 165 M16C/5L Group, M16C/56 Group 9. Power Control h. Entering 125 kHz on-chip oscillator mode from 125 kHz on-chip oscillator low power mode Entering low-speed mode from low power mode Follow both or either of the procedures below (in no particular order). (1) Start the main clock and wait until the oscillation stabilizes.
Page 166 M16C/5L Group, M16C/56 Group 9. Power Control 9.3.3 Wait Mode The CPU clock stops in wait mode, therefore, the CPU and the watchdog timer clocked by the CPU clock stops running. However, if the CSPRO bit in the CSPR register is 1 (count source protection mode enabled), the watchdog timer remains active.
Page 167 M16C/5L Group, M16C/56 Group 9. Power Control 9.3.3.4 Exiting Wait Mode The MCU exits wait mode by a reset or interrupt. Table 9.7 lists Resets and Interrupts to Exit Wait Mode and Conditions for Use. The peripheral function interrupts are affected by the CM02 bit in the CM0 register. When the CM02 bit is 0 (peripheral function clock f1 does not stop in wait mode), peripheral function interrupts can be used to exit wait mode.
Page 168 M16C/5L Group, M16C/56 Group 9. Power Control 9.3.4 Stop Mode In stop mode, all oscillator are stopped, so the CPU clock and peripheral function clocks are also stopped. Therefore, the CPU and the peripheral functions using these clocks stop operating. The least amount of power is consumed in this mode.
Page 169 M16C/5L Group, M16C/56 Group 9. Power Control 9.3.4.3 Exiting Stop Mode Use a reset or an interrupt to exit stop mode. Table 9.9 lists Resets and Interrupts to Exit Stop Mode and Conditions for Use. Table 9.9 Resets and Interrupts to Exit Stop Mode and Conditions for Use Interrupt, Reset Conditions for Use Usable(I NT5 is usable when the digital debounce filter is disabled...
Page 170 M16C/5L Group, M16C/56 Group 9. Power Control Power Control in Flash Memory 9.4.1 Stopping Flash Memory When the flash memory is stopped, current consumption is reduced. Execute a program in the RAM. Figure 9.2 shows the setting procedure to stop and restart the flash memory. Follow the flowchart of Figure 9.2.
Page 171 M16C/5L Group, M16C/56 Group 9. Power Control 9.4.2 Reading Flash Memory Current consumption while reading the flash memory can be reduced by using bits FMR22 and FMR23 in the FMR2 register. 9.4.2.1 Slow Read Mode Slow read mode can be used when f(BCLK) is less than or equal to f(SLOW_R) and the PM17 bit in the PM1 register is 1 (one wait).
Page 172 M16C/5L Group, M16C/56 Group 9. Power Control 9.4.2.2 Low Current Consumption Read Mode Low current consumption read mode can be used when the CM07 bit in the CM0 register is 1 (sub clock used as CPU clock). Figure 9.4 shows Setting and Canceling Low Current Consumption Read Mode.
Page 173 M16C/5L Group, M16C/56 Group 9. Power Control Reducing Power Consumption To reduce power consumption, refer to the following descriptions when designing a system or writing a program. 9.5.1 Ports The MCU retains the state of each I/O port even when it enters wait mode or stop mode. A current flows in the active output ports.
Page 174 M16C/5L Group, M16C/56 Group 9. Power Control Notes on Power Control 9.6.1 CPU Clock When switching the CPU clock source, wait until oscillation of the switched clock source is stable. After exiting stop mode, wait until oscillation stabilizes before changing the division. 9.6.2 Wait Mode •...
Page 175 M16C/5L Group, M16C/56 Group 9. Power Control The following is an example program for entering stop mode: Program Example: FSET BSET 0, CM1 ; Enter stop mode JMP.B ; Insert a JMP.B instruction ; At least four NOP instructions • The CLKOUT pin outputs a high-level signal in stop mode.
Page 176 M16C/5L Group, M16C/56 Group 10. Processor Mode 10. Processor Mode 10.1 Introduction Single-chip mode is supported as a processor mode. Table 10.1 lists the Processor Mode Features. Table 10.1 Processor Mode Features Processor Mode Access Space Pins Assigned as I/O Ports All pins are I/O ports or Single-chip mode SFR, internal RAM, internal ROM...
Page 177 M16C/5L Group, M16C/56 Group 10. Processor Mode 10.2 Registers Table 10.2 Registers Address Register Symbol Reset Value 0005h Processor Mode Register 1 0000 1000b 0010h Program 2 Area Control Register PRG2C XXXX XX00b 0221h Flash Memory Control Register 1 FMR1 00X0 XX0Xb 10.2.1 Processor Mode Register 1 (PM1)
Page 178 M16C/5L Group, M16C/56 Group 10. Processor Mode 10.2.2 Program 2 Area Control Register (PRG2C) Program 2 Area Control Register b6 b5 b4 Reset Value Symbol Address PRG2C 0010h XXXX XX00b Bit Symbol Bit Name Function 0 : Enable program ROM 2 PRG2C0 Program ROM 2 disable bit (reserved area)
Page 179 M16C/5L Group, M16C/56 Group 10. Processor Mode 10.2.3 Flash Memory Control Register 1 (FMR1) Flash Memory Control Register 1 b6 b5 b4 Symbol Address Reset Value FMR1 00X0 XX0Xb 0221h Bit Symbol Bit Name Function — Reserved bit The read value is undefined. (b0) Write to FMR6 register 0 : Disabled...
Page 180 M16C/5L Group, M16C/56 Group 10. Processor Mode 10.3 Software Wait The PM17 bit in the PM1 register, PM20 bit in the PM2 register, and FMR17 bit in the FMR1 register select software wait and the bus cycles will be determined accordingly. Table 10.3 lists the relation between software wait related bits and bus cycle.
Page 181 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11. Programmable I/O Ports Note The 64-pin package has no P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P9_5 to P9_7. 11.1 Introduction Table 11.1 lists Programmable I/O Port Specifications (hereafter referred to as I/O ports). Each pin functions as a programmable I/O port or a peripheral function input/output.
Page 182 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.2 I/O Ports and Pins Figure 11.1 to Figure 11.6, and Table 11.3 and Table 11.8 show the programmable I/O ports, and Figure 11.7 shows the pins. Pull-up selection Direction register Data bus Port latch (See Note 1) Input level switch...
Page 183 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports Pull-up selection Direction register Output Data bus Port latch (See Note 1) Input level switch function Input to peripheral functions Analog input Note: symbolizes a parasitic diode. Make sure the input voltage to each port does not exceed VCC. Figure 11.2 I/O Ports (Output) Table 11.4...
Page 184 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports Pull-up selection Direction register PCR0 bit in the PCR register Data bus Port latch (See Note 1) Input level switch function Input to peripheral functions Analog input INPC1_7/INT5 Digital debounce filter Note: symbolizes a parasitic diode.
Page 185 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports Pull-up selection Direction register Output Data bus Port latch (See Note 1) CMOS output/ N-channel open drain output selection Input level switch function Input to peripheral functions Analog output Input to peripheral functions Note: symbolizes a parasitic diode.
Page 186 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports Pull-up selection PM24 bit in the PM2 register (NMI enabled) Direction register Port latch Data bus (See Note 1) Input level switch function Digital debounce filter NMI interrupt input input PM24 bit in the PM2 register (NMI enabled) Note: symbolizes a parasitic diode.
Page 187 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports Pull-up selection CM04 bit in the CM0 register Direction register P8_7 Data bus Port latch (See Note 1) CM04 bit Input level switch function Pull-up selection CM04 bit in the CM0 register Direction register P8_6 CM04 bit...
Page 188 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports CNVSS signal input CNVSS (See Note 1) RESET signal input RESET (See Note 1) Note: symbolizes a parasitic diode. Make sure the input voltage to each port does not exceed VCC. Figure 11.7 Pins R01UH0127EJ0110 Rev.1.10 Page 151 of 803...
Page 189 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.3 Registers Table 11.9 Registers Address Register Name Register Symbol Reset Value NMI Digital Debounce Register 02FEh NDDR 02FFh P1_7 Digital Debounce Register P17DDR 0360h Pull-Up Control Register 0 PUR0 0361h Pull-Up Control Register 1 PUR1 0362h Pull-Up Control Register 2...
Page 190 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports NMI Digital Debounce Register (NDDR) 11.3.1 NMI Digital Debounce Register Reset Value Symbol Address NDDR 02FEh Function Setting Range With n being the setting value: • n = 00h to FEh: (n + 1) x 8 A signal with larger pulse width than is input to NMI/SD.
Page 191 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.3.3 Pull-Up Control Register 0 (PUR0) Pull-Up Control Register 0 b7 b6 b5 b4 Symbol Address Reset Value PUR0 0360h Bit Symbol Bit Name Function PU00 P0_0 to P0_3 pull-up PU01 P0_4 to P0_7 pull-up PU02 P1_0 to P1_3 pull-up PU03...
Page 192 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.3.5 Pull-Up Control Register 2 (PUR2) Pull-Up Control Register 2 b7 b6 b5 b4 Symbol Address Reset Value PUR2 0362h Bit Symbol Bit Name Function PU20 P8_0 to P8_3 pull-up PU21 P8_4 to P8_7 pull-up PU22 P9_0 to P9_4 pull-up 0: Not pulled high...
Page 193 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.3.6 Port Control Register (PCR) Port Control Register Symbol Address Reset Value b6 b5 b4 0366h 0XX0 0XX0b Bit Symbol Bit Name Function Operation performed when the P1 register is read 0: When the port is set to input, the input PCR0 Port P1 control bit levels of pins P1_0 to P1_7 are read.
Page 194 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.3.7 Input Threshold Select Register 0 (VLT0) Input Threshold Select Register 0 Reset Value b7 b6 b5 b4 Symbol Address VLT0 036Ch Bit Symbol Bit Name Function b1 b0 × VLT00 0 0: 0.50 P0 input level select bit 0 1: Do not set.
Page 195 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.3.8 Input Threshold Select Register 1 (VLT1) Input Threshold Select Register 1 Symbol Address Reset Value b7 b6 b5 b4 VLT1 036Dh 0000XXXXb Bit Symbol Bit Name Function — No register bits. If necessary, set to 0. The read value is undefined. —...
Page 196 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.3.10 Pin Assignment Control Register (PACR) Pin Assignment Control Register Reset Value b7 b6 b5 b4 Symbol Address PACR 0370h 0XXXX000b Bit Symbol Bit Name Function PACR0 b2 b1 b0 0: 64-pin version 1: 80-pin version Pin enable bit PACR1...
Page 197 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.3.11 Port Pi Register (Pi) (i = 0 to 3, 6 to 10) Port Pi Register (i=0 to 3, 6 to 8, 10) Symbol Address Reset Value b7 b6 b5 b4 P0 to P3 03E0h, 03E1h, 03E4h, 03E5h P6 to P7 03ECh, 03EDh...
Page 198 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.3.12 Port Pi Direction Register (PDi) (i = 0 to 3, 6 to 10) Port Pi Direction Register (i=0 to 3, 6 to 8, 10) Symbol Address After Reset PD0 to PD3 03E2h, 03E3h, 03E6h, 03E7h b7 b6 b5 b4 PD6 to PD7...
Page 199 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.4 Peripheral Function I/O 11.4.1 Peripheral Function I/O and Port Direction Bits Programmable I/O ports can share pins with peripheral function I/O (see Table 1.7 to Table 1.10 Pin Names). Some peripheral function I/O are affected by a port direction bit which shares the same pin. Table 11.10 lists The Setting of Direction Bits Functioning as Peripheral Function I/O.
Page 200 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.4.3 Digital Debounce Filters The MCU has two digital debounce filters for noise reduction, assigned to NMI / SD and INT5 /INPC1_7. Registers NDDR and P17DDR set the filter widths, respectively. The digital debounce function is triggered by a rising or falling edge of digital input signal to either NMI / SD and INT5 /INPC1_7.
Page 201 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports Example of the P1_7/INT5 digital debounce filter function, P17DDR = 03h Digital debounce filter Clock Signal output INT5 interrupt or internal INPC1_7 input (internal signal) P1_7/INT5/INPC1_7 Pin input Count value Data bus Data bus Reload value (read)
Page 202 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.5 Unassigned Pin Handling Table 11.11 Unassigned Pin Handling in Single-Chip Mode Pin Name Connection One of the following: • Set the pin to input mode and connect a pin to VSS via resistor (pull-down) Ports P0 to P3, P6 toP10 •...
Page 203 M16C/5L Group, M16C/56 Group 11. Programmable I/O Ports 11.6 Notes on Programmable I/O Ports 11.6.1 Pin Assignment Control Bits PACR2 to PACR0 in the PACR register are 000b after reset. Set 010b (64-pin package) or 011b (80-pin package) to select the pin package, depending on the product. After setting bits PACR2 to PACR0, set the programmable I/O ports and I/O pins for peripherals.
Page 204 M16C/5L Group, M16C/56 Group 12. Interrupts 12. Interrupts 12.1 Introduction Table 12.1 lists Types of Interrupts, and Table 12.2 lists I/O Pins. The pins shown in Table 12.2 are external interrupt input pins. Refer to the peripheral functions for the pins related to the peripheral functions.
Page 205 M16C/5L Group, M16C/56 Group 12. Interrupts 12.2 Registers Table 12.3 Registers (1/2) Address Register Symbol Reset Value 001Eh Processor Mode Register 2 XX00 0X01b INT3 Interrupt Control Register 0044h INT3IC XX00 X000b INT5 Interrupt Control Register 0048h INT5IC XX00 X000b INT4 Interrupt Control Register 0049h INT4IC...
Page 206 M16C/5L Group, M16C/56 Group 12. Interrupts Table 12.4 Registers (2/2) Address Register Symbol Reset Value UART4 Transmit Interrupt Control Register, S4TIC, 006Fh Real-Time Clock Compare Interrupt Control XXXX X000b RTCCIC Register 0070h UART4 Receive Interrupt Control Register S4RIC XXXX X000b 0071h CAN0 Wake-up Interrupt Control Register C0WIC...
Page 207 M16C/5L Group, M16C/56 Group 12. Interrupts 12.2.1 Processor Mode Register 2 (PM2) Processor Mode Register 2 Reset Value b6 b5 b4 Symbol Address 001Eh XX00 0X01b Bit Symbol Bit Name Function — Reserved bit Set to 1. (b0) 0 : Clock is protected by PRCR register PM21 System clock protection bit 1 : Clock change disabled...
Page 208 M16C/5L Group, M16C/56 Group 12. Interrupts 12.2.2 Interrupt Control Register 1 (BCNIC/TMOSIC, DM0IC to DM3IC, KUPIC,ADIC, S0TIC to S2TIC, S0RIC to S3RIC, TA0IC to TA4IC, TB0IC to TB2IC, S4TIC/RTCCIC, S4RIC, C0WIC,S3TIC/C0EIC, RTCTIC C0RIC, C0TIC, C0FRIC, C0FTIC, ICOC0IC, ICOCH0IC, ICOC1IC/IICIC, ICOCH1IC/SCLDAIC, ICOCH2IC to ICOCH3IC, BTIC) Interrupt Control Register 1 Symbol...
Page 209 M16C/5L Group, M16C/56 Group 12. Interrupts 12.2.3 Interrupt Control Register 2 (INT3IC, INT5IC, INT4IC, INT0IC to INT2IC) Interrupt Control Register 2 b7 b6 b5 b4 Symbol Address Reset Value XX00 X000b Refer to the table below for symbols and addresses. Bit Symbol Bit Name Function...
Page 210 M16C/5L Group, M16C/56 Group 12. Interrupts 12.2.4 Interrupt Source Select Register 3 (IFSR3A) Interrupt Select Register 3 b6 b5 b4 Symbol Address Reset Value IFSR3A 0205h Bit Symbol Bit Name Function — Reserved bits Set to 0. (b5-b0) 0: UART4 transmission IFSR36 Interrupt source select bit 1: Real-time clock compare...
Page 211 M16C/5L Group, M16C/56 Group 12. Interrupts 12.2.5 Interrupt Source Select Register 2 (IFSR2A) Interrupt Source Select Register 2 b6 b5 b4 Symbol Address Reset Value IFSR2A 0206h Bit Symbol Bit Name Function 0: UART2 bus collision detection IFSR20 Interrupt source select bit 1: Task monitor timer —...
Page 212 M16C/5L Group, M16C/56 Group 12. Interrupts 12.2.6 Interrupt Source Select Register (IFSR) Interrupt Source Select Register b7 b6 b5 b4 Symbol Address Reset Value IFSR 0207h Bit Symbol Bit Name Function INT0 interrupt polarity select 0 : One edge IFSR0 1 : Both edges INT1 interrupt polarity select 0 : One edge...
Page 213 M16C/5L Group, M16C/56 Group 12. Interrupts 12.2.7 Address Match Interrupt Enable Register (AIER) Address Match Interrupt Enable Register b7 b6 b5 b4 Symbol Address Reset Value AIER 020Eh XXXX XX00b Bit Symbol Bit Name Function Address match interrupt 0 0 : Interrupt disabled AIER0 enable bit 1 : Interrupt enabled...
Page 214 M16C/5L Group, M16C/56 Group 12. Interrupts 12.2.9 Address Match Interrupt Register i (RMADi) (i = 0 to 3) Address Match Interrupt Register i (i = 0 to 3) (b23) (b16) (b15) (b8) Symbol Address Reset Value 0212h to 0210h X0 0000h RMAD0 X0 0000h 0216h to 0214h...
Page 215 M16C/5L Group, M16C/56 Group 12. Interrupts 12.2.10 NMI Digital Debounce Register (NDDR) NMI Digital Debounce Register Reset Value Symbol Address NDDR 02FEh Function Setting Range With n being the setting value: • n = 00h to FEh: (n + 1) x 8 A signal with larger pulse width than is input to NMI/SD.
Page 216 M16C/5L Group, M16C/56 Group 12. Interrupts 12.3 Types of Interrupts Figure 12.1 shows Types of Interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction (non-maskable interrupt) INT instruction Interrupt Watchdog timer Special Oscillator stop/restart detect (non-maskable interrupt) Voltage monitor 2 Hardware Single-step Address match...
Page 217 M16C/5L Group, M16C/56 Group 12. Interrupts 12.4 Software Interrupts A software interrupt occurs when executing instructions. Software interrupts are non-maskable interrupts. 12.4.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 12.4.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set to 1 (the operation resulted in an overflow).
Page 218 M16C/5L Group, M16C/56 Group 12. Interrupts 12.5 Hardware Interrupts Hardware interrupts are classified into two types: special interrupts and peripheral function interrupts. 12.5.1 Special Interrupts Special interrupts are non-maskable interrupts. NMI Interrupt 12.5.1.1 An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details on the NMI interrupt, refer to 12.9 “...
Page 219 M16C/5L Group, M16C/56 Group 12. Interrupts 12.6 Interrupts and Interrupt Vectors One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector.
Page 220 M16C/5L Group, M16C/56 Group 12. Interrupts 12.6.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register compose a relocatable vector table area. Setting an even address in the INTB register results in the interrupt sequence being executed faster than setting an odd address.
Page 221 M16C/5L Group, M16C/56 Group 12. Interrupts Table 12.7 Relocatable Vector Tables (2/2) Software Vector Address Interrupt Source Interrupt Reference Address (L) to Address (H) Number INT0 +116 to +119 (0074h to 0077h) INT1 12.8 “ INT Interrupt” +120 to +123 (0078h to 007Bh) INT2 +124 to +127 (007Ch to 007Fh) DMA2...
Page 222 M16C/5L Group, M16C/56 Group 12. Interrupts 12.7 Interrupt Control 12.7.1 Maskable Interrupt Control The settings for enabling/disabling the maskable interrupts and of the acceptance priority are explained below. Note that these explanations do not apply to non-maskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control register to enable or disable a maskable interrupt.
Page 223 M16C/5L Group, M16C/56 Group 12. Interrupts 12.7.2 Interrupt Sequence The interrupt sequence is explained here. The sequence starts when an interrupt request is accepted and ends when the interrupt routine is executed. When an interrupt request occurs during execution of an instruction, the processor determines its priority after the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
Page 224 M16C/5L Group, M16C/56 Group 12. Interrupts 12.7.3 Interrupt Response Time Figure 12.4 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes the time from when an interrupt request is generated until the first instruction in the interrupt routine is executed.
Page 225 M16C/5L Group, M16C/56 Group 12. Interrupts 12.7.5 Saving Registers In the interrupt sequence, the FLG register and PC are saved on the stack. At this time, the 4 upper bits of the PC and the 4 upper (IPL) and 8 lower bits in the FLG register, 16 bits in total, are saved on the stack first.
Page 226 M16C/5L Group, M16C/56 Group 12. Interrupts 12.7.6 Returning from an Interrupt Routine The FLG register and PC saved in the stack immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Then, the CPU returns to the program which was being executed before the interrupt request was accepted.
Page 227 M16C/5L Group, M16C/56 Group 12. Interrupts Priority level of each interrupt Level 0 (initial value) High IC/OC channel 3 IC/OC channel 1, SCL/SDA IC/OC channel 0 CAN0 transmit FIFO CAN0 transmission complete Priority level of each interrupt IC/OC base timer Timer B1 IC/OC channel 2 Timer A4...
Page 228 M16C/5L Group, M16C/56 Group 12. Interrupts 12.7.9 Multiple Interrupts The following shows the internal bit states when control has branched to an interrupt routine. • I flag = 0 (interrupt disabled) • IR bit = 0 (interrupt not requested) • Interrupt priority level = IPL By setting the I flag to 1 (interrupt enabled) in the interrupt routine, an interrupt request with higher priority than the IPL can be acknowledged.
Page 229 M16C/5L Group, M16C/56 Group 12. Interrupts NMI Interrupt 12.9 An NMI interrupt is generated when input to the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. To use the NMI interrupt, set the PM24 bit in the PM2 register to 1 ( NMI interrupt enabled).
Page 230 M16C/5L Group, M16C/56 Group 12. Interrupts 12.11 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi register. Use bits AIER0 and AIER1 in the AIER register, and bits AIER20 and AIER21 in the AIER2 register to enable or disable the interrupt.
Page 231 M16C/5L Group, M16C/56 Group 12. Interrupts 12.12 Non-Maskable Interrupt Source Discrimination The watchdog timer interrupt, oscillator stop/restart detect interrupt, and voltage monitor 2 interrupt share the same interrupt vector. When using some functions together, read the detect flags of the events in an interrupt processing program, and determine the source of the interrupt.
Page 232 M16C/5L Group, M16C/56 Group 12. Interrupts 12.13 Notes on Interrupts 12.13.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from address 00000h during the interrupt sequence.
Page 233 M16C/5L Group, M16C/56 Group 12. Interrupts 12.13.4 Changing an Interrupt Source When the interrupt source is changed, the IR bit in the interrupt control register may become 1 (interrupt requested). To use an interrupt, change the interrupt source, and then set the IR bit to 0 (interrupt not requested).
Page 234 M16C/5L Group, M16C/56 Group 12. Interrupts 12.13.5 Rewriting the Interrupt Control Register To modify the interrupt control register, follow either of the procedures below: • Modify in places where no interrupt requests corresponding to the interrupt control register may occur. •...
Page 235 M16C/5L Group, M16C/56 Group 12. Interrupts 12.13.7 INT Interrupt • Either a low level of at least tw(INL) width or a high level of at least tw(INH) width is necessary for the signal input to pins INT0 through INT5 , regardless of the CPU operation clock. •...
Page 236 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13. Watchdog Timer 13.1 Introduction The watchdog timer contains a 15-bit counter, and the count source protection mode can be enabled/disabled. Table 13.1 shows the watchdog timer specifications and Figure 13.1 shows a block diagram of the watchdog timer.
Page 237 M16C/5L Group, M16C/56 Group 13. Watchdog Timer Prescaler CM07 = 0, WDC7 = 0 1/16 CSPRO = 0 PM12 = 0 1/128 CPU clock Watchdog timer CM07 = 0, interrupt request WDC7 = 1 Watchdog timer counter CM07 = 1 (See Note 1) PM12 = 1 CSPRO = 1...
Page 238 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13.2 Registers Table 13.2 Registers Address Register Names Register Symbol Reset Value 002Ch Voltage Monitor 2 Control Register VW2C 1000 0X10b Count Source Protection Mode Register 037Ch CSPR 037Dh Watchdog Timer Refresh Register WDTR 037Eh Watchdog Timer Start Register...
Page 239 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13.2.1 Voltage Monitor 2 Control Register (VW2C) Voltage Monitor 2 Control Register b7 b6 b5 b4 Symbol Address Reset Value 1000 0X10b (hardware reset, VW2C 002Ch power-on reset, voltage monitor 0 reset) Bit Symbol Bit Name Function Voltage monitor 2 interrupt/...
Page 240 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13.2.2 Count Source Protection Mode Register (CSPR) Count Source Protection Mode Register Symbol Address Reset Value b7 b6 b5 b4 CSPR 037Ch 0000 0000b (when the CSPROINI bit in the OFS1 address is 1) 1000 0000b (when the CSPROINI bit in the OFS1 address is 0) Bit Symbol...
Page 241 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13.2.4 Watchdog Timer Start Register (WDTS) Watchdog Timer Start Register Symbol Address Reset Value WDTS 037Eh Function The watchdog timer starts counting after a write instruction to this register. The WDTS register is enabled when the WDTON bit in the OFS1 address is 1 (watchdog timer stops after reset).
Page 242 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13.3 Optional Function Select Area In the optional function select area, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected. The optional function select area is not an SFR, and therefore cannot be rewritten by a program. Set an appropriate value when writing a program to flash memory.
Page 243 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13.3.2 Optional Function Select Address 2 (OFS2) Optional Function Select Address 2 b6 b5 b4 Symbol Address OFS2 FFFDBh Bit Symbol Bit Name Function b1 b0 WDTUFS0 0 0: 03FFh Watchdog timer initial setting bit 0 1: 0FFFh 1 0: 1FFFh WDTUFS1...
Page 244 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13.4 Operations 13.4.1 Refresh Operation Period To refresh the watchdog timer, the period writing to the WDTR register can be limited to the fixed period before the underflow. The refresh period can be selected by setting bits WDTRCS1 and WDTRCS0 in the OFS2 address.
Page 245 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13.4.2 Count Source Protection Mode Disabled The CPU clock is used as the watchdog timer count source when the count source protection mode is disabled. Table 13.3 lists the specifications of watchdog timer when the count source protection mode is disabled. Table 13.3 Watchdog Timer Specifications (When Count Source Protection Mode is Disabled) Item...
Page 246 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13.4.3 Count Source Protection Mode Enabled When the count source protection mode is enabled, fWDT is used as the watchdog timer count source. Table 13.4 lists the specifications of the watchdog timer when the count source protection mode is enabled.
Page 247 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13.5 Interrupts The watchdog timer interrupt is a non-maskable interrupt. The watchdog timer interrupt, oscillator stop/restart detect interrupt, and voltage monitor 2 interrupt share an vector. When using multiple functions, read the detect flag in an interrupt handler to determine which interrupt factor generates an interrupt request.
Page 248 M16C/5L Group, M16C/56 Group 13. Watchdog Timer 13.6 Notes on the Watchdog Timer After the watchdog timer interrupt is generated, use the WDTR register to refresh the watchdog timer counter. R01UH0127EJ0110 Rev.1.10 Page 211 of 803 Sep 01, 2011...
Page 249 M16C/5L Group, M16C/56 Group 14. DMAC 14. DMAC 14.1 Introduction The direct memory access controller (DMAC) allows data to be transferred without CPU intervention. There are four DMAC channels. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit) unit of data from the source address to the destination address.
Page 250 M16C/5L Group, M16C/56 Group 14. DMAC Address bus DMA0 source pointer SAR0 DMA0 destination pointer DAR0 DMA0 forward address pointer DMA1 source pointer SAR1 DMA1 destination pointer DAR1 DMA1 forward address pointer DMA0 transfer counter reload register TCR0 DMA0 transfer counter TCR0 DMA2 source pointer SAR2 DMA2 destination pointer DAR2 DMA1 transfer counter reload register TCR1...
Page 251 M16C/5L Group, M16C/56 Group 14. DMAC 14.2 Registers Table 14.2 lists Registers. Do not access these registers using the DMAC. Table 14.2 Registers Address Register Symbol Reset Value 0180h 0181h DMA0 Source Pointer SAR0 0182h 0184h 0185h DMA0 Destination Pointer DAR0 0186h 0188h...
Page 252 M16C/5L Group, M16C/56 Group 14. DMAC 14.2.1 DMAi Source Pointer (SARi) (i = 0 to 3) DMAi Source Pointer (i = 0 to 3) (b23) (b16) (b15) (b8) Symbol Address Reset Value SAR0 0182h to 0180h 0X XXXXh 0192h to 0190h SAR1 0X XXXXh 01A2h to 01A0h...
Page 253 M16C/5L Group, M16C/56 Group 14. DMAC 14.2.3 DMAi Transfer Counter (TCRi) (i = 0 to 3) DMAi Transfer Counter (i = 0 to 3) (b15) (b8) Symbol Address Reset Value 0189h to 0188h TCR0 Undefined TCR1 0199h to 0198h Undefined TCR2 01A9h to 01A8h Undefined...
Page 254 M16C/5L Group, M16C/56 Group 14. DMAC 14.2.4 DMAi Control Register (DMiCON) (i = 0 to 3) DMAi Control Register (i = 0 to 3) b7 b6 b5 b4 Symbol Address Reset Value DM0CON 018Ch 0000 0X00b DM1CON 019Ch 0000 0X00b DM2CON 01ACh 0000 0X00b...
Page 255 M16C/5L Group, M16C/56 Group 14. DMAC 14.2.5 DMAi Source Select Register (DMiSL) (i = 0 to 3) DMAi Source Select Register (i = 0 to 3) b7 b6 b5 b4 Symbol Address Reset Value DM0SL 0398h DM1SL 039Ah DM2SL 0390h DM3SL 0392h Bit Symbol...
Page 256 M16C/5L Group, M16C/56 Group 14. DMAC Table 14.3 Sources of DMA Request (DMA0) DSEL4 to DSEL0 DMS is 0 (Basic Source of Request) DMS is 1 (Expanded Source of Request) Falling edge of the INT0 pin 0 0 0 0 0 b IC/OC base timer 0 0 0 0 1 b Software trigger...
Page 257 M16C/5L Group, M16C/56 Group 14. DMAC Table 14.5 Sources of DMA Request (DMA2) DSEL4 to DSEL0 DMS is 0 (Basic Source of Request) DMS is 1 (Expanded Source of Request) Falling edge of the INT2 pin 0 0 0 0 0 b IC/OC base timer 0 0 0 0 1 b Software trigger...
Page 258 M16C/5L Group, M16C/56 Group 14. DMAC 14.3 Operations 14.3.1 DMA Enabled When data transfer starts after setting the DMAE bit in the DMiCON register to 1 (enabled), the DMAC operates as listed below (i = 0 to 3). If 1 is written to the DMAE bit when it is already set to 1, the DMAC also performs the following operations.
Page 259 M16C/5L Group, M16C/56 Group 14. DMAC 14.3.3 Transfer Cycles A transfer cycle is composed of a bus cycle to read data from a source address (source read), and a bus cycle to write data to a destination address (destination write). The number of read and write bus cycles varies with the source and destination addresses.
Page 260 M16C/5L Group, M16C/56 Group 14. DMAC (1) Transfers are performed in 8-bit or 16-bit units, and the transfer source is an even address. BCLK Address Dummy CPU use Source CPU use Destination cycle RD signal WR signal Data bus Dummy CPU use Source CPU use...
Page 261 M16C/5L Group, M16C/56 Group 14. DMAC 14.3.4 DMAC Transfer Cycles The formula for calculating the number of DMAC transfer cycles is shown below. Number of transfer cycles per transfer unit = Number of read cycles × j + Number of write cycles × k Table 14.8 DMAC Transfer Cycles Single-Chip Mode...
Page 262 M16C/5L Group, M16C/56 Group 14. DMAC 14.3.5 Single Transfer Mode In single transfer mode, the transfer stops when the DMAi transfer counter underflows. Figure 14.3 shows an Operation Example in Single Transfer Mode. Single Transfer Mode When a DMA transfer begins, the DMAS bit becomes 0. DMAS bit Underflow TCRi register...
Page 263 M16C/5L Group, M16C/56 Group 14. DMAC 14.3.6 Repeat Transfer Mode In repeat transfer mode, when the DMAi transfer counter underflows, it is reloaded with the value of the DMAi transfer counter reload register and DMA transfer continues. Figure 14.4 shows an Operation Example in Repeat Transfer Mode.
Page 264 M16C/5L Group, M16C/56 Group 14. DMAC 14.3.7 Channel Priority and DMA Transfer Timing If multiple channels among DMA0 to DMA3 are enabled and DMA transfer request signals are detected as active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel becomes 1 (DMA requested) at the same time.
Page 265 M16C/5L Group, M16C/56 Group 14. DMAC 14.4 Interrupts Refer to operation examples for interrupt request generation timing. For details on interrupt control, refer to 12.7 “Interrupt Control”. Table 14.10 DMAC Interrupt Related Registers Address Register Symbol Reset Value 004Bh DMA0 Interrupt Control Register DM0IC XXXX X000b 004Ch...
Page 266 M16C/5L Group, M16C/56 Group 14. DMAC 14.5 Notes on DMAC 14.5.1 Write to the DMAE Bit in the DMiCON Register (i = 0 to 3) (Technical update number: TN-M16C-92-0306) When both of the following conditions are met, follow steps (1) and (2) below. Conditions •...
Page 267 M16C/5L Group, M16C/56 Group 15. Timer A 15. Timer A 15.1 Introduction Timers A consists of timers A0 to A4. Each timer operates independently of the others. Table 15.1 lists Timer A Specifications, Table 15.2 lists Differences in Timer A Mode, Figure 15.1 shows Timer A and B Count Sources, Figure 15.2 shows Timer A Configuration, Figure 15.3 shows Timer A Block Diagram, and Table 15.3 lists I/O Ports.
Page 268 M16C/5L Group, M16C/56 Group 15. Timer A fC32 fOCO-S fOCO-F f64TIMAB f32TIMAB f8TIMAB f1TIMAB or f2TIMAB TCK1 to TCK0 TMOD1 to TMOD0 00b: Timer mode TCS3 10b: One-shot timer mode 11b: PWM mode Timer A0 Timer A0 interrupt TCS2 to TCS0 000b 01b: Event counter mode 001b...
Page 269 M16C/5L Group, M16C/56 Group 15. Timer A fC32 Data Bus fOCO-S fOCO-F PWMFSi f64TIMAB TAi1 register TAi register f32TIMAB f8TIMAB Count source select f1TIMAB TCS3 TCK1 to TCK0 or f2TIMAB ·Timer: TMOD1 to TMOD0 = 00b, MR2 = 0 Reload register ·One-shot timer: TMOD1 to TMOD0 = 10b TMOD1 to TMOD0,...
Page 270 M16C/5L Group, M16C/56 Group 15. Timer A 15.2 Registers Table 15.4 lists registers associated with timer A. Set the TCDIV00 bit in the TCKDIVC0 register before setting other registers associated with timer A. After changing the TCDIV00 bit, set other registers associated with timer A again. Refer to “registers and the setting”...
Page 271 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.1 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register Symbol Address Reset Value b6 b5 b4 PCLKR 0012h 00000011b Bit Symbol Bit Name Function Timers A, B, S, multi-master I C-bus interface clock select bit 0: f2TIMAB/f2IIC PCLK0 (clock source for timers A , B, S,...
Page 272 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.3 Timer AB Division Control Register 0 (TCKDIVC0) Timer AB Division Control Register 0 Symbol Address Reset Value b6 b5 b4 TCKDIVC0 0000 X000b 01CBh Bit Symbol Bit Name Function Clock select prior to timer AB 0 : f1 TCDIV00 1 : fOCO-F...
Page 273 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.4 Timer A Count Source Select Register i (TACSi) (i = 0 to 2) Timer A Count Source Select Register 0, Timer A Count Source Select Register 1 Symbol Address Reset Value b7 b6 b5 b4 TACS0 to TACS1 01D0h to 01D1h Bit Symbol...
Page 274 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.5 16-bit Pulse Width Modulation Mode Function Select Register (PWMFS) 16-bit Pulse Width Modulation Mode Function Select Register b6 b5 b4 Symbol Address Reset Value PWMFS 0XX0 X00Xb 01D4h Bit Symbol Bit Name Function —...
Page 275 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.6 Timer A Waveform Output Function Select Register (TAPOFS) Timer A Waveform Output Function Select Register Symbol Address Reset Value b7 b6 b5 b4 TAPOFS XXX0 0000b 01D5h Bit Symbol Bit Name Function POFS0 TA0OUT output polar control bit POFS1...
Page 276 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.7 Timer A Output Waveform Change Enable Register (TAOW) Timer A Output Waveform Change Enable Register Symbol Address Reset Value b7 b6 b5 b4 TAOW XXX0 X00Xb 01D8h Bit Symbol Bit Name Function —...
Page 277 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.8 Timer Ai Register (TAi) (i = 0 to 4) Timer Ai Register (i = 0 to 4) (b15) (b8) Address Reset Value Symbol 0327h to 0326h XXXXh 0329h to 0328h XXXXh 032Bh to 032Ah XXXXh 032Dh to 032Ch XXXXh...
Page 278 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.9 Timer Ai-1 Register (TAi1) (i = 1, 2, 4) Timer Ai-1 Register (i = 1, 2, 4) (b15) (b8) Symbol Address Reset Value TA11 0303h to 0302h XXXXh TA21 0305h to 0304h XXXXh TA41 0307h to 0306h...
Page 279 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.11 One-Shot Start Flag (ONSF) One-Shot Start Flag Symbol Address Reset Value b7 b6 b5 b4 ONSF 0322h Bit Name Function Bit Symbol TA0OS Timer A0 one-shot start flag TA1OS Timer A1 one-shot start flag The timer starts counting by setting this bit TA2OS Timer A2 one-shot start flag...
Page 280 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.12 Trigger Select Register (TRGSR) Trigger Select Register Symbol Address Reset Value b7 b6 b5 b4 TRGSR 0323h Bit Symbol Bit Name Function Timer A1 event/trigger b1 b0 TA1TGL select bit 0 : Input on TA1IN selected 1 : TB2 selected 0 : TA0 selected TA1TGH...
Page 281 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.13 Increment/Decrement Flag (UDF) Increment/Decrement Flag b7 b6 b5 b4 Symbol Address Reset Value 0324h Bit Symbol Bit Name Function Timer A0 increment/ TA0UD decrement flag Timer A1 increment/ TA1UD decrement flag 0 : Decrement Timer A2 increment/ TA2UD 1 : Increment...
Page 282 M16C/5L Group, M16C/56 Group 15. Timer A 15.2.14 Timer Ai Mode Register (TAiMR) (i = 0 to 4) Timer Ai Mode Register (i = 0 to 4) Symbol b7 b6 b5 b4 Address Reset Value TA0MR to TA4MR 0336h to 033Ah Bit Name Function Bit Symbol...
Page 283 M16C/5L Group, M16C/56 Group 15. Timer A 15.3 Operations 15.3.1 Common Operations 15.3.1.1 Operating Clock The count source for each timer acts as a clock, controlling such timer operations as counting and reloading. If the conditions to start counting are met, the stopped counter starts counting at the count timing of the first count source.
Page 284 M16C/5L Group, M16C/56 Group 15. Timer A 15.3.1.3 Count Source Internal clocks are counted in timer mode, one-shot timer mode, PWM mode, and programmable output mode. Refer to Figure 15.1 “Timer A and B Count Sources” for details. Table 15.5 lists the Timer A Count Sources.
Page 285 M16C/5L Group, M16C/56 Group 15. Timer A 15.3.2 Timer Mode In timer mode, the timer counts an internally generated count source. Table 15.6 lists Timer Mode Specifications, Table 15.7 lists Registers and the Setting in Timer Mode, and Figure 15.5 shows an Operation Example in Timer Mode.
Page 286 M16C/5L Group, M16C/56 Group 15. Timer A Table 15.7 Registers and Settings in Timer Mode Register Function and Setting PCLKR PCLK0 Select the count source. CPSRF CPSR Write 1 to reset the clock prescaler. TCKDIVC0 TCDIV00 Select the clock used prior to timer AB frequency dividing. PWMFS PWMFSi Set to 0.
Page 287 M16C/5L Group, M16C/56 Group 15. Timer A Timer Mode Timer Ai Mode Register (i = 0 to 4) Symbol Address Reset Value b6 b5 b4 TA0MR to TA4MR 0336h to 033Ah Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 0 : Timer mode TMOD1 0 : No pulse output...
Page 288 M16C/5L Group, M16C/56 Group 15. Timer A Count source Count stopped Count stopped by TAiIN gate function by TAiS bit Count started Count operations 0000h n + 1 Underflow and reload TAiS bit in the TABSR register TAiIN input TAiOUT output Output inverted Low-level output POFSi = 0...
Page 289 M16C/5L Group, M16C/56 Group 15. Timer A 15.3.3 Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing) In event counter mode, the timer counts pulses from an external device, or overflows/underflows of other timers. Timers A2, A3, and A4 can count two-phase external signals. Refer to 15.3.4 “Event Counter Mode (When Processing Two-Phase Pulse Signal)”...
Page 290 M16C/5L Group, M16C/56 Group 15. Timer A Table 15.9 Registers and Settings in Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing) Register Function and Setting PCLKR PCLK0 - (setting unnecessary) CPSRF CPSR Write 1 to reset the clock prescaler. TCKDIVC0 TCDIV00 - (setting unnecessary)
Page 291 M16C/5L Group, M16C/56 Group 15. Timer A Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing) Timer Ai Mode Register (i = 0 to 4) Symbol Address Reset Value b6 b5 b4 TA0MR to TA4MR 0336h to 033Ah Bit Symbol Bit Name Function TMOD0...
Page 292 M16C/5L Group, M16C/56 Group 15. Timer A TAiIN input Overflow and reload FFFFh Decrement Counter operations Count started Increment 0000h Underflow FFFFh-n+1 Count reload stopped TAiS bit in the TABSR register TAiUD bit in the UDF register TAiOUT output POFSi = 0 Low-level output Output inverted at underflow or overflow Low-level output at count stop...
Page 293 M16C/5L Group, M16C/56 Group 15. Timer A 15.3.4 Event Counter Mode (When Processing Two-Phase Pulse Signal) Timers A2, A3, and A4 can be used to count two-phase pulse signals. Table 15.10 lists Event Counter Mode Specifications (When Processing Two-Phase Pulse Signal with Timers A2, A3, and A4). Table 15.11 lists Registers and the Setting in Event Counter Mode (When Processing Two-Phase Pulse Signal).
Page 294 M16C/5L Group, M16C/56 Group 15. Timer A Table 15.11 Registers and Settings in Event Counter Mode (When Processing Two-Phase Pulse Signal) Register Function and Setting PCLKR PCLK0 - (setting unnecessary) CPSRF CPSR Write 1 to reset the clock prescaler. TCKDIVC0 TCDIV00 - (setting unnecessary) PWMFS...
Page 295 M16C/5L Group, M16C/56 Group 15. Timer A Event Counter Mode (When Using Two-Phase Pulse Signal Processing) Timer Ai Mode Register (i = 2 to 4) Symbol Address Reset Value b6 b5 b4 TA2MR to TA4MR 0338h to 033Ah Bit Symbol Bit Name Function TMOD0...
Page 296 M16C/5L Group, M16C/56 Group 15. Timer A 15.3.4.1 Normal Processing The timer increments at rising edges or decrements at falling edges on the TAjIN pin when input signals to the TAjOUT (j = 2, 3) pin is high level. TAjOUT TAjIN Increment Increment Increment Decrement Decrement Decrement j = 2, 3...
Page 297 M16C/5L Group, M16C/56 Group 15. Timer A 15.3.4.3 Counter Initialization Using Two-Phase Pulse Signal Processing This function initializes the timer count value to 0000h using Z-phase (counter initialization) input during two-phase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal processing, free-running type, multiply-by-4 processing, with Z-phase entered from the ZP pin.
Page 298 M16C/5L Group, M16C/56 Group 15. Timer A 15.3.5 One-Shot Timer Mode In one-shot timer mode, the timer is activated only once per trigger. When the trigger occurs, the timer starts and continues operating for a given period. Table 15.12 lists One-Shot Timer Mode Specifications.
Page 299 M16C/5L Group, M16C/56 Group 15. Timer A Table 15.13 Registers and Settings in One-Shot Timer Mode Register Setting PCLKR PCLK0 Select the count source. CPSRF CPSR Write 1 to reset the clock prescaler. TCKDIVC0 TCDIV00 Select a clock used prior to dividing timer AB frequency. PWMFS PWMFSi Set to 0.
Page 300 M16C/5L Group, M16C/56 Group 15. Timer A One-Shot Timer Mode Timer Ai Mode Register (i = 0 to 4) Symbol Address Reset Value b6 b5 b4 TA0MR to TA4MR 0336h to 033Ah Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 1 0 : One-shot timer mode TMOD1...
Page 301 M16C/5L Group, M16C/56 Group 15. Timer A Count source Count starts with a maximum of a 1.5 cycle delay of the count source after an external trigger. Reload and Reload stop counting Count operations 0000h Reload and stop After retrigger, counting when 0000h is set.
Page 302 M16C/5L Group, M16C/56 Group 15. Timer A 15.3.6 Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession. The counter functions as either a 16-bit pulse width modulator or 8-bit pulse width modulator. Table 15.14 lists PWM Mode Specifications.
Page 303 M16C/5L Group, M16C/56 Group 15. Timer A Table 15.15 Registers and Settings in PWM Mode Register Setting PCLKR PCLK0 Select the count source. CPSRF CPSR Write 1 to reset the clock prescaler. TCKDIVC0 TCDIV00 Select the clock used prior to dividing timer AB frequency. PWMFS PWMFSi Set to 0.
Page 304 M16C/5L Group, M16C/56 Group 15. Timer A Pulse Width Modulation (PWM) Mode Timer Ai Mode Register (i = 0 to 4) Symbol Address Reset Value b6 b5 b4 TA0MR to TA4MR 0336h to 033Ah Bit Symbol Bit Name Function TMOD0 Operation mode select bit 1 : PWM mode or programmable output mode...
Page 305 M16C/5L Group, M16C/56 Group 15. Timer A 65535 65535 65535 Reload count started 65535-n when a value other than Count started 0000h is written. Count operations Count stopped 0000h 65535-n Reload 0000h and Write 0000h to the TAi Becomes 0 stop counting.
Page 306 M16C/5L Group, M16C/56 Group 15. Timer A Count started Counter operations of 0000h lower bits 255-n Count started Counter operations of upper bits 0000h 255-n TAiS bit in the TABSR register TAiOUT output POFSi = 0 POFSi = 1 (n+1)(m+1) n(m+1) n(m+1) 255(m+1)
Page 307 M16C/5L Group, M16C/56 Group 15. Timer A 15.3.7 Programmable Output Mode (Timers A1, A2, and A4) In programmable output mode, the timer outputs low- and high-levels of pulse width successively. Table 15.16 lists Programmable Output Mode Specifications. Table 15.17 lists Registers and the Setting in Programmable Output Mode.
Page 308 M16C/5L Group, M16C/56 Group 15. Timer A Table 15.17 Registers and Settings in Programmable Output Mode Register Function and Setting PCLKR PCLK0 Select the count source. CPSRF CPSR Write 1 to reset the clock prescaler. TCKDIVC0 TCDIV00 Select a clock used prior to dividing timer AB frequency. PWMFS PWMFSi Set to 1.
Page 309 M16C/5L Group, M16C/56 Group 15. Timer A Programmable Output Mode Timer Ai Mode Register (i = 1, 2, 4) Symbol Address Reset Value b6 b5 b4 TA0MR to TA4MR 0336h to 033Ah Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 1 : PWM mode or programmable output mode TMOD1...
Page 310 M16C/5L Group, M16C/56 Group 15. Timer A Count started Count stopped 0000h Count the updated Update registers TAi and Set to 0 value. TAi1 during this period. by a program TAiS bit Cannot be a retrigger in the TABSR register after count start Count stopped TAiIN input...
Page 311 M16C/5L Group, M16C/56 Group 15. Timer A 15.4 Interrupts Refer to individual operation examples for interrupt request generating timing. Refer to 12.7 “Interrupt Control” for details of interrupt control. Table 15.18 lists Timer A Interrupt Related Registers. Table 15.18 Timer A Interrupt Related Registers Address Register Symbol...
Page 312 M16C/5L Group, M16C/56 Group 15. Timer A 15.5 Notes on Timer A 15.5.1 Common Notes on Multiple Modes 15.5.1.1 Register Setting The timer stops after reset. Set the mode, count source, counter value, etc., using registers TAiMR, TAi, TAi1, UDF, TRGSR, PWMFS, TACS0 to TACS2, TAPOFS, TCKDIVC0, PCLKR, and bits TAZIE, TA0TGL, and TA0TGH in the ONSF register before setting the TAiS bit in the TABSR register to 1 (count started) (i = 0 to 4).
Page 313 M16C/5L Group, M16C/56 Group 15. Timer A 15.5.2 Timer A (Timer Mode) 15.5.2.1 Reading the Timer The counter value can be read from the TAi register at any time while counting. However, if the counter is read at the same time as it is reloaded, the read value is FFFFh. Also, if the counter is read before it starts counting, or after a value is set in the TAi register while not counting, the set value is read.
Page 314 M16C/5L Group, M16C/56 Group 15. Timer A 15.5.5 Timer A (Pulse Width Modulation Mode) 15.5.5.1 Changing Operating Modes The IR bit becomes 1 when setting a timer operating mode with any of the following: • Selecting PWM mode or programmable output mode after reset •...
Page 315 M16C/5L Group, M16C/56 Group 15. Timer A 15.5.6 Timer A (Programmable Output Mode) 15.5.6.1 Changing the Operating Mode The IR bit becomes 1 when setting a timer operating mode with any of the following: • Selecting PWM mode or programmable output mode after reset •...
Page 316 M16C/5L Group, M16C/56 Group 16. Timer B 16. Timer B 16.1 Introduction Timer B consists of timers B0 to B2. Each timer operates independently of the others. Table 16.1 lists Timer B Specifications, Figure 16.1 shows Timer A and B Count Sources, Figure 16.2 shows the Timer B Configuration, Figure 16.3 shows the Timer B Block Diagram, and Table 16.2 lists the I/O Ports.
Page 317 M16C/5L Group, M16C/56 Group 16. Timer B fC32 fOCO-S fOCO-F f64TIMAB Timer B2 overflow or underflow (to timer A count source) f32TIMAB ↑ f8TIMAB f1TIMAB or f2TIMAB TCK1 to TCK0 TMOD1 to TMOD0 00: Timer mode, A/D trigger mode TCS3 10: Pulse width, pulse period measurement mode Timer B0 interrupt Timer B0...
Page 318 M16C/5L Group, M16C/56 Group 16. Timer B Data Bus PPWFS12 to PPWFS10 TBi1 register TBi register Clock source select f1TIMAB Reload register Reload register TCK1 to TCK0 TCS3 or TCS7 f2TIMAB 00: Timer mode, A/D trigger mode f8TIMAB TMOD1 to TMOD0 Seletor (Timer B0, Timer B1) f32TIMAB...
Page 319 M16C/5L Group, M16C/56 Group 16. Timer B 16.2 Registers Table 16.3 lists registers associated with timer B. Set the TCDIV00 bit in the TCKDIVC0 register before setting other registers associated with timer B. After changing the TCDIV00 bit, set other registers associated with timer B again. Refer to “registers and the setting”...
Page 320 M16C/5L Group, M16C/56 Group 16. Timer B 16.2.1 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register Symbol Address Reset Value b6 b5 b4 PCLKR 0012h 00000011b Bit Symbol Bit Name Function Timers A, B, S, multi-master I C-bus interface clock select bit 0: f2TIMAB/f2IIC PCLK0 (clock source for timers A , B, S,...
Page 321 M16C/5L Group, M16C/56 Group 16. Timer B 16.2.3 Timer Bi Register (TBi) (i = 0 to 2) Timer Bi Register (i = 0 to 2) (b15) (b8) Symbol Address Reset Value 0331h to 0330h XXXXh 0333h to 0332h XXXXh 0335h to 0334h XXXXh Mode Function...
Page 322 M16C/5L Group, M16C/56 Group 16. Timer B 16.2.4 Timer Bi-1 Register (TBi1) (i = 0 to 2) Timer Bi-1 Register (i = 0 to 2) (b15) (b8) Symbol Address Reset Value TB01 01C1h to 01C0h XXXXh TB11 01C3h to 01C2h XXXXh TB21 01C5h to 01C4h...
Page 323 M16C/5L Group, M16C/56 Group 16. Timer B 16.2.6 Timer B Count Source Select Register i (TBCSi) (i = 0 to 1) Timer B Count Source Select Register 0 Symbol Address Reset Value b7 b6 b5 b4 TBCS0 01C8h Bit Symbol Bit Name Function b2 b1 b0...
Page 324 M16C/5L Group, M16C/56 Group 16. Timer B 16.2.7 Timer AB Division Control Register 0 (TCKDIVC0) Timer AB Division Control Register 0 Symbol Address Reset Value b6 b5 b4 TCKDIVC0 0000 X000b 01CBh Bit Symbol Bit Name Function Clock select prior to timer AB 0 : f1 TCDIV00 1 : fOCO-F...
Page 325 M16C/5L Group, M16C/56 Group 16. Timer B 16.2.9 Timer Bi Mode Register (TBiMR) (i = 0 to 2) Timer Bi Mode Register (i = 0 to 2) Symbol Address Reset Value b7 b6 b5 b4 TB0MR to TB2MR 033Bh to 033Dh 00XX 0000b Bit Symbol Bit Name...
Page 326 M16C/5L Group, M16C/56 Group 16. Timer B 16.3 Operations 16.3.1 Common Operations 16.3.1.1 Operating Clock The count source for each timer acts as a clock, controlling such timer operations as counting and reloading. 16.3.1.2 Counter Reload Timing Timer Bi starts counting from the value (n) set in the TBi register. The TBi register consists of a counter and a reload register.
Page 327 M16C/5L Group, M16C/56 Group 16. Timer B 16.3.1.3 Count Source Internal clocks are counted in timer mode, pulse period measurement mode, and pulse width measurement mode. Refer to Figure 16.1 “Timer A and B Count Sources” for details. Table 16.4 lists Timer B Count Sources.
Page 328 M16C/5L Group, M16C/56 Group 16. Timer B 16.3.2 Timer Mode In timer mode, the timer counts an internally generated count source. Table 16.5 lists Timer Mode Specifications, Table 16.6 lists Registers and Setting in Timer Mode, and Figure 16.4 shows an Operation Example in Timer Mode.
Page 329 M16C/5L Group, M16C/56 Group 16. Timer B Timer Mode Timer Bi Mode Register (i = 0 to 2) Symbol Address Reset Value b6 b5 b4 TB0MR to TB2MR 033Bh to 033Dh 00XX 0000b Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 0 : Timer mode TMOD1...
Page 330 M16C/5L Group, M16C/56 Group 16. Timer B 16.3.3 Event Counter Mode In event counter mode, the timer counts pulses from an external device, or overflows and underflows of other timers. Table 16.7 lists Event Counter Mode Specifications, Table 16.8 lists Registers and Settings in Event Counter Mode, and Figure 16.5 shows an Operation Example in Event Counter Mode.
Page 331 M16C/5L Group, M16C/56 Group 16. Timer B Event Counter Mode Timer Bi Mode Register (i = 0 to 2) Symbol Address Reset Value b6 b5 b4 TB0MR to TB2MR 033Bh to 033Dh 00XX 0000b Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 1 : Event counter mode...
Page 332 M16C/5L Group, M16C/56 Group 16. Timer B TBiIN input Count stop by TBiS bit Count start Count operations 0000h Underflow and reload TBiS bit in the TABSR register IR bit in the TBiIC register Set to 0 by accepting an interrupt request, or by a program. i = 0 to 2 The above assumes the following: •...
Page 333 M16C/5L Group, M16C/56 Group 16. Timer B 16.3.4 Pulse Period/Pulse Width Measurement Modes In pulse period and pulse width measurement modes, the timer measures the pulse period or pulse width of an external signal. Table 16.9 lists Specifications of Pulse Period/Pulse Width Measurement Modes, Table 16.10 lists Registers and Settings in Pulse Period/Pulse Width Measurement Modes, Figure 16.6 shows Operation Example in Pulse Period Measurement Mode, and Figure 16.7 shows an Operation Example in Pulse Width Measurement Mode.
Page 334 M16C/5L Group, M16C/56 Group 16. Timer B Table 16.10 Registers and Settings in Pulse Period/Pulse Width Measurement Modes Register Function and Setting PCLKR PCLK0 Select the count source. CPSRF CPSR Write 1 to reset the clock prescaler. Measurement result can be read when the bits in the PPWFS1 TBi1 15 to 0 register corresponding to timer Bi are 1.
Page 335 M16C/5L Group, M16C/56 Group 16. Timer B Pulse Period/Pulse Width Measurement Modes Timer Bi Mode Register (i = 0 to 2) Symbol Address Reset Value b6 b5 b4 TB0MR to TB2MR 033Bh to 033Dh 00XX 0000b Bit Symbol Bit Name Function TMOD0 Operation mode select...
Page 336 M16C/5L Group, M16C/56 Group 16. Timer B Count source Transfer to the TBi register (Measured value 3) (Undefined Transfer to value) the TBi register Transfer to the TBi register (Measured value 4) (Measured value 1) (Undefined (Measured value) value 2) Count start 0000h...
Page 337 M16C/5L Group, M16C/56 Group 16. Timer B Count source FFFFh Transfer to (Undefined the TBi register value) Transfer to the TBi register (Measured value 3) (Measured value 1) (Undefined (Measured value) value 2) Count started 0000h Becomes 0000h Becomes 0000h TBiS bit in the TABSR register TBiIN input...
Page 338 M16C/5L Group, M16C/56 Group 16. Timer B 16.4 Interrupts Refer to individual operation examples for interrupt request generating timing. Refer to 12.7 “Interrupt Control” for details of interrupt control. Table 16.11 lists Timer B Interrupt Related Registers. Table 16.11 Timer B Interrupt Related Registers Address Register Symbol...
Page 339 M16C/5L Group, M16C/56 Group 16. Timer B 16.5 Notes on Timer B 16.5.1 Common Notes on Multiple Modes 16.5.1.1 Register Setting The timer is stopped after reset. Set the mode, count source, etc., using registers TBiMR, TBCS0 to TBCS1, TBi, PCLKR and PPWFS1 before setting the TBiS bit in the TABSR register to 1 (count started) (i = 0 to 2).
Page 340 M16C/5L Group, M16C/56 Group 16. Timer B 16.5.4 Timer B (Pulse Period/Pulse Width Measurement Modes) 16.5.4.1 MR3 Bit in the TBiMR Register To clear the MR3 bit to 0 by writing to the TBiMR register while the TBiS bit is 1 (count started), be sure to set the same value as previously set to bits TMOD0, TMOD1, MR0, MR1, TCK0, and TCK1, and set bit 4 to 0.
Page 341 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17. Three-Phase Motor Control Timer Function 17.1 Introduction Timers A1, A2, A4, and B2 can be used to output three-phase motor drive waveforms. Table 17.1 lists Three-Phase Motor Control Timer Function Specifications. Three-Phase Motor Control Timer Function Block Diagrams are shown in Figure 17.1 and Figure 17.2.
Page 342 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function Table 17.1 Three-Phase Motor Control Timer Function Specifications Item Specification • Triangular wave modulation three-phase mode 0 Three-phase PWM waveform of triangular wave modulation is output. Output data is updated every half cycle of the carrier wave, and an output waveform is generated.
Page 343 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function INV13 ICTB2 register n = 1 to 15 Circuit to set interrupt INV00 INV01 generation frequency INV11 Timer B2 Timer B2 Timer B2 underflow ICTB2 counter Reload interrupt n = 1 to 15 request bit PWCON PWCON...
Page 344 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function IVPCR1 Reset PD8_0 INV03 PFC0 Data bus INV04 INV05 INV14 P8_0 port latch U (pin) PDRT PDRU The above diagram shows an example of U-phase. IVPCR1 : Bit in the TB2SC register INV03 to INV05 : Bits in the INVC0 register PD8_0 : Bit in the PD8 register...
Page 345 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.2 Registers Refer to “registers and settings” in each mode for register and bit settings. Three-phase motor control timer function uses timers A1, A2, A4, and B2. For other registers related to timers A1, A2, A4, and B2, refer to 15.
Page 346 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.2.1 Timer B2 Register (TB2) Timer B2 Register (b15) (b8) Symbol Address Reset Value 0335h to 0334h Undefined Function Setting Range If the setting value is n, the counter frequency is n + 1 0000h to FFFFh Timers A1, A2, and A4 start each time an underflow occurs.
Page 347 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.2.3 Three-Phase PWM Control Register 0 (INVC0) Three-Phase PWM Control Register 0 b7 b6 b5 b4 Symbol Address Reset Value 0308h INVC0 Bit Symbol Bit Name Function INV00 Timer B2 underflow ICTB2 count condition select 0 : Timer B2 underflow when timer A1 reload control signal is 0...
Page 348 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function INV03 (Three-phase motor control timer output control bit) (b3) Conditions to become 0: • The INV04 bit is 1 (simultaneous turn-on disabled) and the INV05 bit is 1 (simultaneous turn-on detected).
Page 349 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.2.4 Three-Phase PWM Control Register 1 (INVC1) Three-Phase PWM Control Register 1 b7 b6 b5 b4 Symbol Address Reset Value INVC1 0309h Bit Symbol Bit Name Function 0 : Timer B2 underflow Timer A1, A2 and A4 start INV10 1 : Timer B2 underflow and write to the TB2...
Page 350 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function INV13 (Carrier wave rise/fall detect flag) (b3) The INV13 bit is enabled only when the INV06 bit is set to 0 (triangular wave modulation mode) and the INV11 bit to 1 (three-phase mode 1). INV16 (Dead time timer trigger select bit) (b6) If both of the following conditions are met, set the INV16 bit to 1 (rising edge of the three-phase output shift register output).
Page 351 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.2.5 Three-Phase Output Buffer Register i (IDBi) (i = 0, 1) Three-Phase Output Buffer Register i (i = 0, 1) b7 b6 b5 b4 Symbol Address Reset Value IDB0 030Ah XX11 1111b IDB1 030Bh...
Page 352 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.2.7 Timer B2 Interrupt Generation Frequency Set Counter (ICTB2) Timer B2 Interrupt Generation Frequency Set Counter Symbol Address Reset Value ICTB2 030Dh Undefined Function Setting Range When a setting value is n, timer B2 interrupt is generated every nth count timer B2 underflow meets the condition 1 to 15 selected by bits INV01 to INV00 in the INVC0 register.
Page 353 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.2.8 Timer B2 Special Mode Register (TB2SC) Timer B2 Special Mode Register b6 b5 b4 Symbol Address Reset Value TB2SC 033Eh X000 0000b Bit Symbol Bit Name Function 0 : Timer B2 underflow Timer B2 reload timing PWCON 1 : Timer A output at odd-numbered...
Page 354 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.2.9 Position-Data-Retain Function Control Register (PDRF) Position-Data-Retain Function Control Register b7 b6 b5 b4 Symbol Address Reset Value PDRF 030Eh XXXX 0000b Bit Symbol Bit Name Function Input level at IDW pin is retained. W-phase position data retain PDRW 0: Low level...
Page 355 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.2.10 Port Function Control Register (PFCR) Port Function Control Register b7 b6 b5 b4 Symbol Address Reset Value PFCR 0318h 0011 1111b Bit Symbol Bit Name Function 0: I/O port P8_0 Port P8_0 output function PFC0 1: Three-phase PWM output (U-phase...
Page 356 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3 Operations 17.3.1 Common Operations in Multiple Modes 17.3.1.1 Carrier Wave Cycle Control Timer B2 controls the cycle of the carrier wave. In triangular wave modulation mode, the cycle of the carrier wave is double the cycle of timer B2 underflow.
Page 357 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.1.2 Three-Phase PWM Wave Control Timer A4 controls U- and U -phase waveforms, timer A1 controls V- and V -phase waveforms, and timer A2 controls W- and W -phase waveforms. Timer Ai (i = 1, 2, 4) starts counting by a trigger selected by the INV10 bit in the INVC1 register, and generates a one-shot pulse (internal signal).
Page 358 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.1.5 Simultaneous Conduction Prevention This function prevents the upper and lower output signals from being active simultaneously due to program errors or unexpected program operation. When the high- and low-side output signals become active at the same time while the simultaneous conduction is disabled by the INV04 bit in the INVC0 register, the following occur: •...
Page 359 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.1.7 Three-Phase PWM Output Pin Select Pins U, U , V, V , W, and W output a three-phase PWM waveform when the PFCi bit (i = 0 to 5) in the PFCR register is 1 (three-phase PWM output).
Page 360 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.1.8 Three-Phase Output Forced Cutoff Function While the INV02 bit in the INVC0 register is 1 (three-phase motor control timer function) and the INV03 bit is 1 (three-phase motor control timer output enabled), when a low-level signal is applied to the SD pin, the INV03 bit in the INVC0 register becomes 0 (three-phase motor control timer output disabled), and pins corresponding to U, U , V, V , W and W outputs change concurrently as follows: •...
Page 361 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.1.9 Position-Data-Retain Function The position-data-retain function employs three position-data input pins: U-, V-, and W-phase. Input levels of IDU, IDV, and IDW inputs are retained. The falling edge or rising edge of the high-side output signal of each phase can be selected by setting the PDRT bit in the PDRF register as a position-data-retain trigger.
Page 362 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.2 Triangular Wave Modulation Three-Phase Mode 0 Triangular wave modulation uses the timer B2 cycle as a reference cycle. Table 17.8 lists Three-Phase Mode 0 Specifications, and Figure 17.6 shows Example of Three-Phase Mode 0 Operation. Table 17.8 Three-Phase Mode 0 Specifications Item...
Page 363 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function Table 17.9 Registers and Settings in Three-Phase Mode 0 (1/2) Register Function and Setting INV00 Disabled (Despite the setting, the ICTB2 register counts timer B2 underflow.) INV01 INV02 Set to 1 (three-phase motor control timer function used). INV03 Set to 1 (three-phase motor control timer output enabled).
Page 364 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function Table 17.10 Registers and Settings in Three-Phase Mode 0 (2/2) Register Function and Setting TA0S Not used for three-phase motor control timer. TA1S Set to 1 when starting counting, and to 0 when stopping counting. TA2S Set to 1 when starting counting, and to 0 when stopping counting.
Page 365 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function Triangular Waveform as a Carrier Wave Carrier wave Signal wave TB2S bit in the TABSR register Timer B2 Timer A1 reload control signal IR bit in the TB2IC register (timer B2 interrupt request) TA4 register a’...
Page 366 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.2.1 Three-Phase PWM Wave Output Timing Control In three-phase mode 0, when a start trigger for timers A1, A2, and A4 is generated, the counter starts counting the value of the TAi register (i = 1, 2, 4). 17.3.2.2 Three-Phase PWM Waveform Output Level Control In triangular wave modulation mode, the output levels set in registers IDB0 and IDB1 are transferred...
Page 367 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.3 Triangular Wave Modulation Three-Phase Mode 1 Triangular wave modulation uses twice the cycles of timer B2 as a reference cycle. Table 17.11 lists Three-Phase Mode 1 Specifications, and Figure 17.7 shows Example of Three-Phase Mode 1 Operation.
Page 368 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function Table 17.12 Registers and Settings in Three-Phase Mode 1 (1/2) Register Functions and Setting INV00 Select the timing that the ICTB2 register starts counting. INV01 INV02 Set to 1 (three-phase motor control timer function used). INV03 Set to 1 (three-phase motor control timer output enabled).
Page 369 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function Table 17.13 Registers and Settings in Three-Phase Mode 1 (2/2) Register Function and Setting TA1TGH to Se to 01b (when using V-phase output control circuit). TA1TGL TA2TGH to Set to 01b (when using W-phase output control circuit). TA2TGL TRGSR TA3TGH to...
Page 370 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function Triangular Waveform as a Carrier Wave Carrier wave Signal wave TB2S bit in the TABSR register Timer B2 Timer A1 reload control signal INV13 bit IR bit in the TB2IC register (timer B2 interrupt request) TA4 register TA41 register...
Page 371 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.3.1 INV13 Bit in the INVC1 Register In three-phase mode 1, the INV13 bit can be used to detect whether the cycle of the carrier wave is the first half or the last half. The INV13 bit is a flag which checks the state of timer A1 reload control signals.
Page 372 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.3.2 Three-Phase PWM Waveform Output Timing Control In three-phase mode 1, when a start trigger for timers A1, A2, and A4 is generated, the value set in the TAi1 register is counted first. Afterward, the values in registers TAi1 and TAi are alternately counted every time a start trigger for timers A1, A2, and A4 is generated.
Page 373 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.3.3 Carrier Wave Control In three-phase mode 1, the reload timing of the TB2 register can be selected by setting the PWCON bit in the TB2SC register. 17.3.3.4 Three-Phase PWM Waveform Output Level Control In triangular wave modulation mode, the output levels set in registers IDB0 and IDB1 are transferred to the three-phase output shift registers by a transfer trigger.
Page 374 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.4 Sawtooth Wave Modulation Mode In this mode, the sawtooth wave is modulated. Table 17.15 lists Sawtooth Wave Modulation Mode Specifications, and Figure 17.9 shows Example of Sawtooth Wave Modulation Mode Operation. Table 17.15 Sawtooth Wave Modulation Mode Specifications Item...
Page 375 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function Table 17.16 Registers and Settings in Sawtooth Wave Modulation Mode (1/2) Register Function and Setting INV00 Disabled (Despite the settings, the ICTB2 register counts timer B2 underflow.) INV01 INV02 Set to 1 (three-phase motor control timer function used). INV03 Set to 1 (three-phase motor control timer output enabled).
Page 376 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function Table 17.17 Registers and Settings in Sawtooth Wave Modulation Mode (2/2) Register Function and Setting TA1TGH to Set to 01b (when using V-phase output control circuit). TA1TGL TA2TGH to Set to 01b (when using W-phase output control circuit). TA2TGL TRGSR TA3TGH to...
Page 377 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function Sawtooth Waveform as a Carrier Wave Carrier wave Signal wave TB2S bit in the TABSR register Timer B2 IR bit in the TB2IC register (timer B2 interrupt request) Timer A4 start trigger signal Timer A4 one-shot pulse...
Page 378 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.3.4.1 Three-Phase PWM Waveform Output Timing Control In sawtooth wave modulation mode, when a start trigger for timers A1, A2, and A4 is generated, the counter starts counting the value in the TAi register (i = 1, 2, 4). 17.3.4.2 Three-Phase PWM Waveform Output Level Control In sawtooth wave modulation mode, the output levels set in registers IDB0 and IDB1 are transferred...
Page 379 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.4 Interrupts The timer B2 interrupt and timer A1, A2, and A4 interrupts can be used with the three-phase motor control timer. 17.4.1 Timer B2 Interrupt When the setting value in the ICTB2 register is n, a timer B2 interrupt request is generated at the timings below.
Page 380 M16C/5L Group, M16C/56 Group 17. Three-Phase Motor Control Timer Function 17.5 Notes on Three-Phase Motor Control Timer Function 17.5.1 Timer A and Timer B Refer to 15.5 “Notes on Timer A” and 16.5 “Notes on Timer B”. Influence of SD 17.5.2 When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three- phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance:...
Page 381 M16C/5L Group, M16C/56 Group 18. Timer S 18. Timer S 18.1 Introduction Timer S has an input capture/output compare function (IC/OC). The input capture (IC) is used for time measurement and the output compare (OC) is used for waveform generation. The IC/OC has one 16-bit free-running base timer and eight channels for time measurement and waveform generation.
Page 382 M16C/5L Group, M16C/56 Group 18. Timer S Clock stopped PCLK0 BCK1 to BCK0 f1TIMS f1TIMS or f2TIMS f2TIMS G1BT Two-phase Two-phase pulse clock INT1 TSUDA pulse input RST2 UD1 to UD0 TSUDB processor Base timer reset fBT1 Base timer overflow IC/OC base timer interrupt (n+1) divider Base timer...
Page 383 M16C/5L Group, M16C/56 Group 18. Timer S Continued from previous page fBT1 Base timer f1TIMS or f2TIMS Match Channel 4 interrupt request Time measurement function and waveform generation function for channels 4 and 5 OUTC1_4 INPC1_4 (The logic circuit for these channels is equivalent to the one for channels 0 and 1. OUTC1_5 INPC1_5 Names of registers, bits and signals for channels 0 and 1 are also applied to names...
Page 384 M16C/5L Group, M16C/56 Group 18. Timer S Table 18.2 I/O Pins Pin Name Function INPC1_0 Input INPC1_1 Input INPC1_2 Input INPC1_3 Input Input pins for the time measurement function INPC1_4 Input INPC1_5 Input INPC1_6 Input INPC1_7 Input OUTC1_0 Output OUTC1_1 Output OUTC1_2 Output...
Page 385 M16C/5L Group, M16C/56 Group 18. Timer S 18.2 Registers Table 18.3 Registers (1/2) Address Register Name Register Symbol Reset Value 02C0h Time Measurement Register 0, G1TM0, G1PO0 Waveform Generation Register 0 02C1h 02C2h Time Measurement Register 1, G1TM1, G1PO1 Waveform Generation Register 1 02C3h 02C4h Time Measurement Register 2,...
Page 386 M16C/5L Group, M16C/56 Group 18. Timer S Table 18.4 Registers (2/2) Address Register Name Register Symbol Reset Value 02EFh Timer S I/O Control Register 1 G1IOR1 02F0h Interrupt Request Register G1IR 02F1h Interrupt Enable Register 0 G1IE0 02F2h Interrupt Enable Register 1 G1IE1 R01UH0127EJ0110 Rev.1.10 Page 349 of 803...
Page 387 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.1 Time Measurement Register j (G1TMj) (j = 0 to 7) Time Measurement Register j (j = 0 to 7) Address (b7) (b0) b7 Symbol Reset Value 02C1h to 02C0h, 02C3h to 02C2h, 02C5h to 02C4h G1TM0 to G1TM2 XXXXh 02C7h to 02C6h, 02C9h to 02C8h, 02CBh to 02CAh...
Page 388 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.2 Waveform Generation Register j (G1POj) (j = 0 to 7) Waveform Generation Register j (j = 0 to 7) (b7) (b0) Reset Value Address Symbol XXXXh 02C1h to 02C0h, 02C3h to 02C2h, 02C5h to 02C4h G1PO0 to G1PO2 XXXXh 02C7h to 02C6h, 02C9h to 02C8h, 02CBh to 02CAh...
Page 389 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.3 Waveform Generation Control Register j (G1POCRj) (j = 0 to 7) Waveform Generation Control Register j (j = 0 to 7) b7 b6 b5 b4 Symbol Address Reset Value G1POCR0 to G1POCR3 02D0h, 02D1h, 02D2h, 02D3h 0X00 XX00b G1POCR4 to G1POCR7...
Page 390 M16C/5L Group, M16C/56 Group 18. Timer S RLD (G1POj register value reload timing select bit) (b5) For SR waveform output mode, set both even channels (channel j (j = 0, 2, 4, or 6)) and odd channels (channel j+1). When writing a value to the G1POj register (j = 0 to 7) while the BTS bit is 0 (base timer reset) and the RLD bit is 1 (reload the G1POj register when the base timer is reset), the written value will not be reloaded to a buffer.
Page 391 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.4 Time Measurement Control Register j (G1TMCRj) (j = 0 to 7) Time Measurement Control Register j (j = 0 to 7) Symbol Reset Value b7 b6 b5 b4 Address G1TMCR0 to G1TMCR3 02D8h, 02D9h, 02DAh, 02DBh G1TMCR4 to G1TMCR7 02DCh, 02DDh, 02DEh, 02DFh...
Page 392 M16C/5L Group, M16C/56 Group 18. Timer S GOC (Gate function release select bit) (b5) The GOC bit is only available in registers G1TMCR6 and G1TMCR7. Set bits 7 to 4 in registers G1MCR0 to G1TMCR5 to 0000b. The GOC bit is enabled only when the GT bit is 1. Refer to 18.2.2 “Waveform Generation Register j (G1POj) (j = 0 to 7)”...
Page 393 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.5 Base Timer Register (G1BT) Base Timer Register (b7) (b0) Address Reset Value Symbol 02E1h to 02E0h XXXXh G1BT Function - While the base timer is running (when the BTS bit in the G1BCR1 register is 1 and bits BCK1 and BCK0 in the G1BCR0 register are values other than 00b): When reading this register, the current base timer value is returned.
Page 394 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.6 Base Timer Control Register 0 (G1BCR0) Base Timer Control Register 0 b7 b6 b5 b4 Symbol Address Reset Value 0 0 0 G1BCR0 02E2h Bit Symbol Bit Name Function b1 b0 BCK0 0 0: Clock stopped Count source select bit 0 1: Do not set.
Page 395 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.7 Base Timer Control Register 1 (G1BCR1) Base Timer Control Register 1 b7 b6 b5 b4 Symbol Address Reset Value G1BCR1 02E3h Bit Symbol Bit Name Function — Reserved Set to 0. (b0) 0: The base timer is not reset when the base Base timer reset source select timer and G1PO0 register values match.
Page 396 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.8 Time Measurement Prescaler Register j (G1TPRj) (j = 6 and 7) Time Measurement Prescaler Register j (j = 6 and 7) Symbol Address Reset Value G1TPR6 02E4h G1TPR7 02E5h Function Set Value If the setting value is n, time measurement is performed every time a trigger 00h to FFh input is counted (n + 1) times.
Page 397 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.10 Function Select Register (G1FS) Function Select Register b7 b6 b5 b4 Symbol Address Reset Value G1FS 02E7h Bit Symbol Bit Name Function Channel 0 time measurement/ FSC0 waveform generation function select bit Channel 1 time measurement/ FSC1 waveform generation function...
Page 398 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.11 Base Timer Reset Register (G1BTRR) Base Timer Reset Register (b7) (b0) b7 Reset Value Symbol Address XXXXh G1BTRR 02E9h to 02E8h Function Setting Range When the RST4 bit in the G1BCR0 register is 1, the base timer is 0001h to FFFFh reset by matching the G1BTRR register value and base timer value.
Page 399 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.13 Waveform Output Master Enable Register (G1OER) Waveform Output Master Enable Register b7 b6 b5 b4 Symbol Address Reset Value G1OER 02ECh Bit Symbol Bit Name Function 0: Output enabled EOC0 OUTC1_0 output disable bit 1: Output disabled (OUTC1_0 pin is used as a programmable I/O port) 0: Output enabled...
Page 400 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.14 Timer S I/O Control Register 0 (G1IOR0) Timer S I/O Control Register 0 b7 b6 b5 b4 Symbol Address Reset Value G1IOR0 02EEh Bit Symbol Bit Name Function b1 b0 0 0: Outputs high or low, depending on the IO00 mode selected by bits MOD1 and MOD0 in the G1POCR0 register.
Page 401 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.15 Timer S I/O Control Register 1 (G1IOR1) Timer S I/O Control Register 1 b7 b6 b5 b4 Symbol Address Reset Value G1IOR1 02EFh Bit Symbol Bit Name Function b1 b0 0 0: Outputs high or low, depending on the IO40 mode selected by bits MOD1 and MOD0 in the G1POCR4 register.
Page 402 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.16 Interrupt Request Register (G1IR) Interrupt Request Register b7 b6 b5 b4 Address Reset Value Symbol 02F0h G1IR Bit Symbol Bit Name Function G1IR0 Channel 0 interrupt request bit G1IR1 Channel 1 interrupt request bit G1IR2 Channel 2 interrupt request bit G1IR3...
Page 403 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.17 Interrupt Enable Register 0 (G1IE0) Interrupt Enable Register 0 b7 b6 b5 b4 Symbol Address Reset Value G1IE0 02F1h Bit Symbol Bit Name Function G1IE00 Channel 0 interrupt enable 0 bit G1IE01 Channel 1 interrupt enable 0 bit G1IE02 Channel 2 interrupt enable 0 bit...
Page 404 M16C/5L Group, M16C/56 Group 18. Timer S 18.2.18 Interrupt Enable Register 1 (G1IE1) Interrupt Enable Register 1 b7 b6 b5 b4 Symbol Address Reset Value G1IE1 02F2h Bit Symbol Bit Name Function G1IE10 Channel 0 interrupt enable 1 bit G1IE11 Channel 1 interrupt enable 1 bit G1IE12 Channel 2 interrupt enable 1 bit...
Page 405 M16C/5L Group, M16C/56 Group 18. Timer S 18.3 Operations 18.3.1 Base Timer The base timer is a free-running counter which counts an internally generated count source. Table 18.5 lists the specifications of the base timer, Figure 18.3 shows the block diagram of the base timer, Table 18.6 lists the base timer associated registers and their settings, Figure 18.4 shows an op era t io n exam ple with incre me nting, F ig ure 1 8.5 sh ows an op era t ion exa mp le with incrementing/decrementing, and Figure 18.7 shows an operation example with two-phase pulse signal...
Page 406 M16C/5L Group, M16C/56 Group 18. Timer S G1BT register Base timer overflow G1DV register BCK1 and BCK0 Base timer f1TIMS or f2TIMS fBT1 (n+1) divider Two-phase TSUDA pulse input TSUDB processor Two-phase pulse clock BTS bit in the G1BCR1 register RST4 Match with the G1BTRR register RST1...
Page 407 M16C/5L Group, M16C/56 Group 18. Timer S 18.3.1.1 Increment The counter starts incrementing from 0000h to FFFFh, then returns back to 0000h, and continues to increment. FFFFh C000h Counter operation 8000h 4000h 0000h When the IT bit in the G1BCR0 register is 1 (IC/OC base timer interrupt generated by the overflow of bit 14) b14 of the base timer...
Page 408 M16C/5L Group, M16C/56 Group 18. Timer S 18.3.1.2 Increment/Decrement The counter starts incrementing from 0000h to FFFFh, then decrements from FFFFh to 0000h. When the counter reaches 0000h, the base timer increments again. FFFFh C000h Counter operation 8000h 4000h 0000h When the IT bit in the G1BCR0 register is 1 (IC/OC base timer interrupt is generated by an...
Page 409 M16C/5L Group, M16C/56 Group 18. Timer S 18.3.1.3 Two-Phase Pulse Signal Processing This count operation counts two-phase pulse input from pins TSUDA and TSUDB. Set the following bits as shown below for two-phase pulse signal processing. Bits BCK1 and BCK0 in the G1BCR0 register: 10b (two-phase pulse clock) RST2 bit in the G1BCR1 register: 1 (the base timer is reset when low is input to the INT1 pin.) Bits UD1 to UD0 in the G1BCR1 register (two-phase pulse signal processing) Figure 18.6 shows Two-Phase Pulse Signal Processing, and Figure 18.7 shows Two-Phase Pulse Signal...
Page 410 M16C/5L Group, M16C/56 Group 18. Timer S (1) The base timer is reset while it is incrementing. TSUDA (A-phase) Input waveform TSUDB (B-phase) fBT1 (Note 1) INT1 (Z-phase) Counter value m + 1 0000h 0001h 0002h Counter becomes 0000h at this timing. Counter becomes 0001h at this timing. (2) The base timer is reset while it is decrementing.
Page 411 M16C/5L Group, M16C/56 Group 18. Timer S 18.3.1.4 Base Timer Reset While the Base Timer is Counting The base timer is reset by one of the following conditions: • The G1BTRR register value matches the base timer value after setting the RST4 in the G1BCR0 register to 1 (the base timer is reset by matching with the G1BTRR register).
Page 412 M16C/5L Group, M16C/56 Group 18. Timer S RST2 bit in the G1BCR1 register Base timer m - 2 m - 1 m + 1 0000h 0001h (Note 1) INT1 The above assumes the following: Bits UD1 and UD0 in the G1BCR1 register are 00b (increment). Notes: 1.
Page 413 M16C/5L Group, M16C/56 Group 18. Timer S 18.3.2 Time Measurement Function The base timer value is stored in the G1TMj register (j = 0 to 7) using an external input as a trigger. Table 18.10 lists the specifications of the time measurement function. Table 18.11 lists the time measurement function associated registers and their settings.
Page 414 M16C/5L Group, M16C/56 Group 18. Timer S Table 18.11 Time Measurement Function Associated Registers Register Function G1TMj Time measurement result can be read. — CTS1 and CTS0 Select a time measurement trigger. G1TMCRj Select whether the digital filter function is used. If used, select a DF1 and DF0 sampling clock to use for the function.
Page 415 M16C/5L Group, M16C/56 Group 18. Timer S (1) The rising edge is selected as a time measurement trigger (bits CTS1 and CTS0 in the G1TMCRj register are 01b). fBT1 Base timer n+9 n+10 n+11 n+12 n+13 n+14 (Note 1) (Note 1) INPC1_ j pin input signals, or trigger signals after passing the digital filter...
Page 416 M16C/5L Group, M16C/56 Group 18. Timer S (1) Example using the prescaler function (G1TPRj register is 02h and the PR bit in the G1TMCRj register is 1) fBT1 n+9 n+10 n+11 n+12 n+13 n+14 Base timer INPC1_ j pin input signals, or trigger signals after passing the digital filter Internal time...
Page 417 M16C/5L Group, M16C/56 Group 18. Timer S 18.3.2.1 Gate Function (Channel 6 and 7) When the GT bit in the G1TMCRj register (j = 6 and 7) is 1 (gate function used), acceptance of trigger inputs is disabled after the time measurement by the first trigger input. When 1 is written to the GSC bit in the G1TMCRj register, acceptance of trigger inputs becomes enabled again.
Page 418 M16C/5L Group, M16C/56 Group 18. Timer S 18.3.3.1 Single-Phase Waveform Output Mode The OUTC1_j pin outputs high when the base timer value matches the G1POj register value (j = 0 to 7) and the INV bit in the G1POCRj register is 0 (output level is not inverted). The OUTC1_j pin outputs low when the base timer reaches 0000h.
Page 419 M16C/5L Group, M16C/56 Group 18. Timer S Table 18.13 Registers and Settings in Single-Phase Waveform Output Mode Register Function G1POj — Set the timing for an output level to become high. G1FS FSCj Set to 0 (waveform generation function selected). G1FE IFEj Set to 1 (channel j function enabled).
Page 420 M16C/5L Group, M16C/56 Group 18. Timer S (1) Free-running operation (when bits RST2 and RST1 in the G1BCR1 register and the RST4 bit in the G1BCR0 register are all 0). FFFFh Base timer 0000h 65536-m fBT1 fBT1 OUTC1_ j pin Output high Output high Output low...
Page 421 M16C/5L Group, M16C/56 Group 18. Timer S (3) Free-running operation (when bits RST2 and RST1 in the G1BCR1 register and the RST4 bit in the G1BCR0 register are all 0). FFFFh Base timer 0000h OUTC1_ j pin Output high by compare match when bits IOj1 and IOj0 are 10b.
Page 422 M16C/5L Group, M16C/56 Group 18. Timer S 18.3.3.2 Inverted Waveform Output Mode The output level at the OUTC1_j pin is inverted every time the base timer value matches the G1POj register value (j = 0 to 7). When bits MOD1 and MOD0 in the G1POCRj register are 10b (inverted waveform output mode), set bits UD1 and UD0 in the G1BCR1 register to 00b (increment) or 01b (increment/decrement).
Page 423 M16C/5L Group, M16C/56 Group 18. Timer S Table 18.15 Registers and Settings in Inverted Waveform Output Mode Register Function G1POj — Set the timing for the waveform to be inverted. G1FS FSCj Set to 0 (waveform generation function selected). G1FE IFEj Set to 1 (channel j function enabled).
Page 424 M16C/5L Group, M16C/56 Group 18. Timer S (1) Free-running operation (when bits RST2 and RST1 in the G1BCR1 register and the RST4 bit in the G1BCR0 register are all 0) FFFFh Base timer 0000h 65536 65536 fBT1 fBT1 Inverted OUTC1_ j pin Inverted 65536 x 2 To set this bit to 0,...
Page 425 M16C/5L Group, M16C/56 Group 18. Timer S (3) Free-running operation (when bits RST2 and RST1 in the G1BCR1 register and the RST4 bit in the G1BCR0 register are all 0): FFFFh Base timer 0000h OUTC1_ j pin Output high by compare match Inverted Inverted when bits IOj1 and IOj0 are 10b.
Page 426 M16C/5L Group, M16C/56 Group 18. Timer S 18.3.3.3 Set/Reset Waveform Output Mode (SR Waveform Output Mode) The OUTC1_j pin outputs high when the INV bit in the G1POCRj register (j = 0, 2, 4, 6) is 0 (output level is not inverted) and the base timer value matches the G1POj register value. When the base timer value matches the G1POk register value (k = j + 1), the OUTC1_j pin outputs low.
Page 427 M16C/5L Group, M16C/56 Group 18. Timer S Table 18.17 Registers and Settings in SR Waveform Output Mode Function Register Even channel (channel j) Odd channel (channel k) Set the timing for an output level to Set the timing for an output level to G1POj —...
Page 428 M16C/5L Group, M16C/56 Group 18. Timer S (1) Free-running operation (when bits RST2 and RST1 in the G1BCR1 register and the RST4 bit in the G1BCR0 register are all 0) FFFFh Base timer 0000h n - m 65536 - n + m fBT1 fBT1 Output low...
Page 429 M16C/5L Group, M16C/56 Group 18. Timer S 18.3.4 I/O Port Select Function The I/O direction of IC/OC pins is determined by registers G1FE, G1FS, and G1OER. In SR waveform output mode, an even channel and an odd channel are used for each output waveform, but a waveform is output only from the even channel.
Page 430 M16C/5L Group, M16C/56 Group 18. Timer S 18.4 Interrupts Refer to each operation example for interrupt request occurrence timings. Refer to 12.7 “Interrupt Control” for details on interrupt control. Table 18.19 lists Timer S Interrupt Associated Registers. Base timer reset request by matching the G1BTRR register and the base timer IC/OC base timer interrupt (IR bit in the BTIC register)
Page 431 M16C/5L Group, M16C/56 Group 18. Timer S Table 18.19 Timer S Interrupt Associated Registers Address Register Symbol Reset Value 0079h IC/OC Interrupt 0 Control Register ICOC0IC XXXX X000b 007Ah IC/OC Channel 0 Interrupt Control Register ICOCH0IC XXXX X000b 007Bh IC/OC Interrupt 1 Control Register ICOC1IC XXXX X000b 007Ch...
Page 432 M16C/5L Group, M16C/56 Group 18. Timer S 18.5 Notes on Timer S 18.5.1 Register Access The explanation for some bits and registers states, “the value written to this register or this bit is reflected to the internal circuit when the clock is synchronized with the base timer count source (fBT1)”. When writing these bits or registers, the written value is not reflected to the internal circuits immediately.
Page 433 M16C/5L Group, M16C/56 Group 18. Timer S IC/OC interrupt 0 processing Buffer ← G1IR register Store an interrupt request for each channel in the buffer on RAM. Wait for one fBT1 cycle since the bits in the G1IR register Wait for one fBT1 cycle cannot be set to 0 for this period.
Page 434 M16C/5L Group, M16C/56 Group 18. Timer S 18.5.3 Changing Registers ICOCiIC (i = 0, 1) While the G1IEij bit in the G1IEi register is 1 (IC/OC interrupt 1 request enabled), use the AND, OR, BCLR, or BSET instruction to change bits ILVL2 to ILVL0 in the ICOCiIC register at the point where a channel j interrupt request may be generated (j = 0 to 7).
Page 435 M16C/5L Group, M16C/56 Group 19. Task Monitor Timer 19. Task Monitor Timer 19.1 Introduction The task monitor timer has one 16-bit timer to count internal count sources. The TMOSPR register (task monitor timer protect register) has the ability to protect other task monitor timer associated registers. Table 19.1 Task Monitor Timer Specifications Item...
Page 436 M16C/5L Group, M16C/56 Group 19. Task Monitor Timer 19.2 Registers Table 19.2 Registers Address Register Name Register symbol Reset Value 01F0h Task Monitor Timer Register TMOS 01F1h 01F2h Task Monitor Timer Count Start Flag TMOSSR XXXX XXX0b Task Monitor Timer Count Source Select 01F3h TMOSCS XXXX 0000b...
Page 437 M16C/5L Group, M16C/56 Group 19. Task Monitor Timer 19.2.3 Task Monitor Timer Count Source Select Register (TMOSCS) Task Monitor Timer Count Source Select Register Symbol Address Reset Value b6 b5 b4 TMOSCS 01F3h XXXX 0000b Bit Symbol Bit Name Function b2 b1 b0 TMOS0CS 0 0 0: f1...
Page 438 M16C/5L Group, M16C/56 Group 19. Task Monitor Timer 19.3 Operation Figure 19.2 shows the Task Monitor Timer Operation. Start counting Counter value 0000h Underflow and reload TMOS0S bit in the TMOSSR register IR bit in the TMOSIC Set to 0 by accepting an interrupt request or by a program. The above assumes the following: -The TMOS register value (n) is 0004h.
Page 439 M16C/5L Group, M16C/56 Group 19. Task Monitor Timer 19.4 Interrupt Table 19.3 lists the Task Monitor Timer Interrupt Associated Register. Table 19.3 Task Monitor Timer Interrupt Associated Register Address Register Name Register Symbol Reset Value 004Ah Task Monitoring Timer Interrupt Control Register TMOSIC XXXX X000b Task monitor timer shares the interrupt vectors and interrupt control registers with other peripheral...
Page 440 M16C/5L Group, M16C/56 Group 19. Task Monitor Timer 19.5 Notes on Task Monitor Timer 19.5.1 Register Settings After reset, the task monitor timer counter is stopped. After setting the counter value and count source by setting registers TMOS register and TMOSCS, set the TMOS0S bit in the TMOSSR register to 1 (start counting).
Page 441 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20. Real-Time Clock 20.1 Introduction The real-time clock generates a 1-second signal from a count source and counts seconds, minutes, hours, a.m./p.m., a day, and a week. It also detects matches with specified seconds, minutes, and hours. Table 20.1 lists Real-Time Clock Specifications, Figure 20.1 shows a Real-Time Clock Block Diagram, and Table 20.2 lists the I/O Port.
Page 442 M16C/5L Group, M16C/56 Group 20. Real-Time Clock RTCCMP0 TOENA HRIE RTCCMP1 MNIE SEIE RTCOUT pin RTCCSEC RTCCMIN RTCCHR PMCMP Match Comparator Control RTC compare interrupt Circuit Match Comparator (IR bit in RTCCIC register) Match Comparator Match Comparator TSTART Initialize RTCCMP0 RTCCMP1 RTCCMP1 TCSTF...
Page 443 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.2 Registers Table 20.3 Registers Address Register Symbol Reset Value 0340h Real-Time Clock Second Data Register RTCSEC 0341h Real-Time Clock Minute Data Register RTCMIN X000 0000b 0342h Real-Time Clock Hour Data Register RTCHR XX00 0000b 0343h Real-Time Clock Day Data Register...
Page 444 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.2.1 Real-Time Clock Second Data Register (RTCSEC) Real-Time Clock Second Data Register Symbol Address Reset Value b7 b6 b5 b4 RTCSEC 0340h Setting Bit Symbol Bit Name Function Range SC00 SC01 Count 0 to 9 every second. When the digit increments, 1 First digit of second count bit 0 to 9...
Page 445 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.2.2 Real-Time Clock Minute Data Register (RTCMIN) Real-Time Clock Minute Data Register Symbol Address Reset Value b7 b6 b5 b4 RTCMIN 0341h X000 0000b Setting Bit Symbol Bit Name Function Range MN00 Count 0 to 9 every minute. MN01 When the digit increments, 1 First digit of minute count bit...
Page 446 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.2.3 Real-Time Clock Hour Data Register (RTCHR) Real-Time Clock Hour Data Register Symbol Address Reset Value b7 b6 b5 b4 RTCHR 0342h XX00 0000b Setting Bit Symbol Bit Name Function Range HR00 HR01 Count 0 to 9 every hour.
Page 447 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.2.4 Real-Time Clock Day Data Register (RTCWK) Real-Time Clock Day Data Register Symbol Address Reset Value b7 b6 b5 b4 RTCWK 0343h XXXX X000b Bit Symbol Bit Name Function b2 b1 b0 0 : Day 1 1 : Day 2 0 : Day 3 Day count bit...
Page 448 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.2.5 Real-Time Clock Control Register 1 (RTCCR1) Real-Time Clock Control Register 1 Symbol Address Reset Value b6 b5 b4 0000 X00Xb RTCCR1 0344h Bit Symbol Bit Name Function — Reserved bit Set to 0 (b0) Real-time clock count status 0 : Count stopped...
Page 449 M16C/5L Group, M16C/56 Group 20. Real-Time Clock RTCRST (Real-Time clock reset bit) (b4) When setting this bit to 0 after setting it to 1, the following are set automatically: • The values are reset in registers RTCSEC, RTCMIN, RTCHR, RTCWK, RTCCR2, RTCCSR, RTCCSEC, RTCCMIN, and RTCCHR.
Page 450 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.2.6 Real-Time Clock Control Register 2 (RTCCR2) Real-Time Clock Control Register 2 Symbol Address Reset Value b7 b6 b5 b4 RTCCR2 0345h X000 0000b Bit Symbol Bit Name Function 0 : Disable periodic interrupt triggered Periodic interrupt triggered every second SEIE...
Page 451 M16C/5L Group, M16C/56 Group 20. Real-Time Clock Table 20.4 Periodic Interrupt Sources Factor Interrupt Source Interrupt Enable Bit Periodic interrupt Value in RTCWK register is set to 000b (1-week period) WKIE triggered every week Periodic interrupt RTCWK register is updated (1-day period) DYIE triggered every day Periodic interrupt...
Page 452 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.2.7 Real-Time Clock Count Source Select Register (RTCCSR) Real-Time Clock Count Source Select Register Symbol Address Reset Value b6 b5 b4 XXX0 0000b RTCCSR 0346h Bit Symbol Bit Name Function b1 b0 RCS0 0 0 : f1 Count source select bit 0 1 : Do not set...
Page 453 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.2.8 Real-Time Clock Second Compare Data Register (RTCCSEC) Real-Time Clock Second Compare Data Register Symbol Address Reset Value b7 b6 b5 b4 X000 0000b RTCCSEC 0348h Setting Bit Symbol Bit Name Function Range SCMP00 SCMP01 First digit of second compare data bit...
Page 454 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.2.9 Real-Time Clock Minute Compare Data Register (RTCCMIN) Real-Time Clock Minute Compare Data Register Symbol Address Reset Value b7 b6 b5 b4 RTCCMIN 0349h X000 0000b Setting Bit Symbol Bit Name Function Range MCMP00 MCMP01 First digit of minute compare data bit...
Page 455 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.2.10 Real-Time Clock Hour Compare Data Register (RTCCHR) Real-Time Clock Hour Compare Data Register Symbol Address Reset Value b7 b6 b5 b4 X000 0000b RTCCHR 034Ah Setting Bit Symbol Bit Name Function Range HCMP00 HCMP01 Store compare data...
Page 456 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.3 Operations 20.3.1 Basic Operation The real-time clock generates a 1-second signal from the count source selected in the RTCCSR register and counts seconds, minutes, hours, a.m./p.m., a day, and a week. The day and time to start the count can be set using registers RTCSEC, RTCMIN, RTCHR, RTCWK, and the RTCPM bit in the RTCCR1 register.
Page 457 M16C/5L Group, M16C/56 Group 20. Real-Time Clock Time and day change TSTART bit in RTCCR1 register ← 0 Stop real-time clock operation (not necessary when count is stopped) (counting) TCSTF bit in RTCCR1 register = 0? Yes (count stopped) RTCTIC register ← 00h Disable real-time clock periodic interrupt RTCCIC register ←...
Page 458 M16C/5L Group, M16C/56 Group 20. Real-Time Clock Time and day change TSTART bit in RTCCR1 register ← 0 Stop real-time clock operation (not necessary when count is stopped or in compare mode 3) (counting) TCSTF bit in RTCCR1 register = 0? Yes (count stopped) RTCTIC register ←...
Page 459 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.3.2 Compare Mode In compare mode, time data and compare data are compared, and a compare match is detected. When a match is detected, the following occur: • Compare interrupt request Refer to 20.4 “Interrupts” for details. •...
Page 460 M16C/5L Group, M16C/56 Group 20. Real-Time Clock Figure 20.6 shows Difference between Compare Modes, Figure 20.7 shows Count Start/Stop Operating Example, Figure 20.8 shows Compare Mode 1 Operating Example, Figure 20.9 shows Compare Mode 2 Operating Example, and Figure 20.10 shows Compare Mode 3 Operating Example. RTCHR RTCPM RTCMIN...
Page 461 M16C/5L Group, M16C/56 Group 20. Real-Time Clock BSY bit Set to 1 by a program Set to 0 by a program TSTART bit in the Count RTCCR1 register started TCSTF bit in the Count stopped RTCCR1 register RTCSEC Undefined Undefined RTCMIN RTCHR RTCPM bit...
Page 462 M16C/5L Group, M16C/56 Group 20. Real-Time Clock BSY bit TCSTF bit in the RTCCR1 register Continue counting Compare match Undefined RTCSEC Continue using the count value Undefined RTCMIN RTCHR RTCPM bit Set to 0 by accepting an interrupt request, or by a program.
Page 463 M16C/5L Group, M16C/56 Group 20. Real-Time Clock BSY bit TCSTF bit in the RTCCR1 register 1 Compare match Continue counting RTCSEC defined Undefined Set back to the reset value RTCMIN Undefined RTCHR Undefined RTCPM bit Undefined IR bit bit in the RTCCIC register Set to 0 by accepting an interrupt request, or by a program.
Page 464 M16C/5L Group, M16C/56 Group 20. Real-Time Clock BSY bit TCSTF bit Count stopped in RTCCR1 register Compare match RTCSEC Undefined Set back to the reset value RTCMIN Undefined RTCHR Undefined RTCPM bit Undefined IR bit in RTCCIC register Set to 0 by accepting an interrupt request, or by a program.
Page 465 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.4 Interrupts The real-time clock generates two types of interrupt: • Periodic interrupts triggered every second, minute, hour, day, and week • Compare match interrupt See Table 20.4 Periodic Interrupt Sources for details on periodic interrupt sources, individual mode specifications and an operating example for the interrupt request generating timing.
Page 466 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.5 Notes on Real-Time Clock 20.5.1 Starting and Stopping the Count The real-time clock uses the TSTART bit for instructing the count to start or stop, and the TCSTF bit which indicates count started or stopped. Bits TSTART and TCSTF are in the RTCCR1 register. The real-time clock starts counting and the TCSTF bit becomes 1 (count started) when the TSTART bit is set to 1 (count started).
Page 467 M16C/5L Group, M16C/56 Group 20. Real-Time Clock 20.5.4 Time Reading Procedure in Real-Time Clock Mode In real-time clock mode, read time data bits when the BSY bit in the RTCSEC register is 0 (not while data is updated). When reading multiple registers, if data is rewritten between reading registers, an errant time will be read.
Page 468 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21. Serial Interface UARTi (i = 0 to 4) Note Pins CLK4, RXD4, and TXD4 do not exist in the 64-pin package. Do not access the UART4 associated registers.
Page 469 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) PCLK1 OCOSEL0 or OCOSEL1 f2SIO f1SIO or f2SIO f1SIO fOCO-F f8SIO f32SIO TXDi RXD polarity polarity RXDi switching switching circuit SMD2 to SMD0 UART reception circuit 100, 101, 110 Receive Transmit/ Reception...
Page 470 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) IOPOL Not inverted RXDi RXD data inverse circuit Inverted Clock sync type UART (7 bits) UART PRYE (8 bits) clock sync STPS UART (7 bits) type UARTi receive register disabled PAR enabled UART...
Page 471 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2 Registers Table 21.3 and Table 21.4 list registers associated with UART0 to UART4. Set the OCOSEL0 or OCOSEL1 bit in the UCLKSEL0 register before setting other registers associated with UART0 to UART4.
Page 472 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Table 21.4 Registers (2/2) Address Register Symbol Reset Value 026Dh UART2 Transmit/Receive Control Register 1 U2C1 0000 0010b 026Eh UART2 Receive Buffer Register U2RB 026Fh 0298h UART4 Transmit/Receive Mode Register U4MR 0299h UART4 Bit Rate Register...
Page 473 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2.1 UART Clock Select Register (UCLKSEL0) UART Clock Select Register Symbol Address Reset Value b6 b5 b4 UCLKSEL0 0252h Bit Symbol Bit Name Function — Reserved bits Set to 0 (b1-b0) UART0 to UART2 clock prior...
Page 474 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2.3 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 4) UARTi Transmit/Receive Mode Register (i = 0 to 4) Symbol Address Reset Value b7 b6 b5 b4 U0MR, U1MR, U2MR 0248h, 0258h, 0268h U4MR, U3MR...
Page 475 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2.4 UARTi Bit Rate Register (UiBRG) (i = 0 to 4) UARTi Bit Rate Register (i = 0 to 4) Symbol Address Reset Value U0BRG, U1BRG, U2BRG 0249h, 0259h, 0269h U4BRG, U3BRG 0299h, 02A9h...
Page 476 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2.6 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 4) UARTi Transmit/Receive Control Register 0 (i = 0 to 4) Symbol Address Reset Value b7 b6 b5 b4 U0C0, U1C0, U2C0 024Ch, 025Ch, 026Ch 0000 1000b...
Page 477 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) NCH (Data output select bit) (b5) When the clock synchronous serial I/O mode, the I C mode, or the UART mode is selected by setting the bits SMD2 to SMD0 in the UiMR register, the output method of pins TXDi/SDAi can be selected with the NCH bit.
Page 478 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2.7 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 to 4) UARTi Transmit/Receive Control Register 1 (i = 0 to 4) Symbol Address Reset Value b7 b6 b5 b4 U0C1, U1C1, U2C1 024Dh, 025Dh, 026Dh 0000 0010b...
Page 479 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2.8 UARTi Receive Buffer Register (UiRB) (i = 0 to 4) UARTi Receive Buffer Register (i = 0 to 4) (b15) (b8) Symbol Address Reset Value U0RB 024Fh to 024Eh XXXXh U1RB...
Page 480 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) FER (Framing error flag) (b13) The FER bit is disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode) or to 010b (I C mode).
Page 481 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2.9 UART2 Special Mode Register 4 (U2SMR4) UART2 Special Mode Register 4 Symbol b7 b6 b5 b4 Address Reset Value U2SMR4 0264h Bit Symbol Bit Name Function 0 : Clear STAREQ Start condition generate bit...
Page 482 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) ACKD (ACK data bit) (b4) ACKC (ACK data output enable bit) (b5) SWC9 (SCL wait auto insert bit 3) (b7) This bit is used in slave mode of I C mode.
Page 483 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2.10 UART2 Special Mode Register 3 (U2SMR3) UART2 Special Mode Register 3 Symbol Address Reset Value b7 b6 b5 b4 U2SMR3 0265h 000X 0X0Xb Bit Symbol Bit Name Function —...
Page 484 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2.11 UART2 Special Mode Register 2 (U2SMR2) UART2 Special Mode Register 2 Symbol Address Reset Value b7 b6 b5 b4 U2SMR2 0266h X000 0000b Bit Symbol Bit Name Function 0 : Use NACK/ACK interrupt IICM2...
Page 485 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2.12 UART2 Special Mode Register (U2SMR) UART2 Special Mode Register Symbol b6 b5 b4 Address Reset Value U2SMR 0267h X000 0000b Bit Symbol Bit Name Function 0 : Other than I C mode IICM C mode select bit...
Page 486 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.2.13 Pin Assignment Control Register (PACR) Pin Assignment Control Register b7 b6 b5 b4 Symbol Address Reset Value PACR 0370h 0XXXX000b Bit Symbol Bit Name Function PACR0 b2 b1 b0 0: 64-pin version 1: 80-pin version...
Page 487 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3 Operations 21.3.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transmit/receive clock to transmit/receive data. Table 21.5 lists the Clock Synchronous Serial I/O Mode Specifications. Table 21.5 Clock Synchronous Serial I/O Mode Specifications Item...
Page 488 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Table 21.6 lists Pin Functions in Clock Synchronous Serial I/O Mode. Note that for a period from when UARTi operating mode is selected to when transmission starts, the TXDi pin outputs a high-level signal.
Page 489 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Table 21.7 Registers Used and Settings in Clock Synchronous Serial I/O Mode Register Bits Function OCOSEL0 Select clock prior to division for UART0 to UART2. UCLKSEL0 OCOSEL1 Select clock prior to division for UART3 to UART4.
Page 490 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) (1) Example of Transmit Timing (Internal Clock Selected) Transmit/receive clock TE bit in the UiC1 register Set the data in the UiTB register. TI bit in the UiC1 register Data is transferred from the UiTB register to the UARTi transmit register.
Page 491 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.1.1 CLK Polarity Select Function Use the CKPOL bit in the UiC0 register (i = 0 to 4) to select the transmit/receive clock polarity. Figure 21.4 shows the Transmit/Receive Clock Polarity. (1) CKPOL bit in the UiC0 register is 0 (transmit data is output at the falling edge and the receive data is input at the rising edge of the transmit/receive clock) CLKi...
Page 492 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.1.2 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 4) to select the bit order. Figure 21.5 shows the Bit Order.
Page 493 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.1.4 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register (i = 0 to 4) is 1 (inverted), the data written to the UiTB register has its logic inverted before being transmitted.
Page 494 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) CTS/RTS Function 21.3.1.5 The CTS function is used to start transmit/receive operation when a low signal is applied to the CTSi / RTSi (i = 0 to 3) pin. Transmit/receive operation begins when input to the CTSi / RTSi pin becomes low.
Page 495 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows data to be transmitted/received after setting the desired bit rate and bit order. Table 21.8 lists the UART Mode Specifications. Table 21.8 UART Mode Specifications Item...
Page 496 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Table 21.9 lists I/O Pin Functions in UART Mode. Note that for a period from when the UARTi operating mode is selected to when transmission starts, the TXDi pin outputs a high-level signal. (If N-channel open drain output is selected, this pin becomes high-impedance.) Table 21.9 I/O Pin Functions in UART Mode...
Page 497 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Table 21.10 Registers Used and Settings in UART Mode Register Bits Function OCOSEL0 Select clock prior to division for UART0 to UART2. UCLKSEL0 OCOSEL1 Select clock prior to division for UART3 to UART4. PCLKR PCLK1 Select the count source for the UiBRG register.
Page 498 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) (1) 8-bit Data Transmit Timing (with a Parity Bit and 1 Stop Bit) The transmit/receive clock stops once because a high-level signal is applied to the CTS pin when the stop bit is verified. The transmit/receive clock resumes running as soon as a low-level signal is applied to the CTS pin.
Page 499 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Example of Receive Timing When Character Bit Length is 8 Bits (Parity Disabled, 1 Stop Bit) Clock divided by UiBRG RE bit in UiC1 register Stop bit Start bit RXDi Sampled as low...
Page 500 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.2.1 Bit Rate In UART mode, the frequency set by the UiBRG register (i = 0 to 4) divided by 16 becomes a bit rate. The setting value (n) of the UiBRG register is calculated by the following formula: ---------------------------------------------- - 1 –...
Page 501 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.2.2 LSB First/MSB First Select Function As shown in Figure 21.10, the bit order can be selected by setting the UFORM bit in the UiC0 register. This function is enabled when the character bit length is 8 bits. (1) UFORM bit in the UiC0 register = 0 (LSB first) CLKi TXDi...
Page 502 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.2.3 Serial Data Logic Switching Function The logic of the data written to the UiTB register is inverted and then transmitted. Similarly, the inverted logic of the received data is read when the UiRB register is read. (1) UiLCH bit in the UiC1 register = 0 (not inverted) Transmit/ High...
Page 503 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) CTS/RTS Function 21.3.2.5 The CTS function is used to start transmit operation when a low signal is applied to the CTSi / RTSi (i = 0 to 3) pin. Transmit operation begins when input to the CTSi / RTSi pin becomes low. If the input level is switched from low to high during transmit operation, the operation stops after the ongoing transmit/receive operation is completed.
Page 504 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.3 Special Mode 1 (I C Mode) (UART2) C mode is compatible with the simplified I C interface. Table 21.12 lists the I C Mode Specifications. Table 21.14 and Table 21.15 list the Registers Used and Settings in I C Mode.
Page 505 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) SDA2 Start and stop condition generation block STSPSEL = 1 DMA0 to DMA3 request SDA (STSP) Delay SCL (STSP) circuit STSPSEL = 0 IICM2 = 1 Transmission UART2 transmit, NACK register interrupt request...
Page 506 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Table 21.14 Registers Used and Settings in I C Mode (1/2) Function Register Bits Master Slave Select clock prior to division for UART0 to Select clock prior to division for UART0 to OCOSEL0 UCLKSEL0 UART2.
Page 507 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Table 21.15 Registers Used and Settings in I C Mode (2/2) Function Register Bits Master Slave IICM2 See Table 21.16 “I C Mode Functions”. See Table 21.16 “I C Mode Functions”.
Page 508 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) In I C mode, functions and timings vary depending on the IICM2 bit setting in the U2SMR2 register. Figure 21.15 shows Transfer to U2RB Register and Interrupt Timing. See Figure 21.15 for the timing of transferring data to the U2RB register, the bit position of the data stored in the U2RB register, types of interrupts, interrupt requests, and DMA request generation timing.
Page 509 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) (1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 1 (clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCL2...
Page 510 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.3.1 Detecting Start and Stop Conditions Start and stop conditions are detected by their respective detectors. Whether a start or a stop condition has been detected is determined. A start condition detect interrupt request is generated when the SDA2 pin changes state from high to low while the SCL2 pin is in the high state.
Page 511 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) (1) Slave mode STSPSEL bit BBS bit ACK/ NACK Start condition detection Stop condition detection interrupt request generated interrupt request generated (2) Master mode (when CKPH is 1) STAREQ bit STPREQ bit STSPSEL bit...
Page 512 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Start condition generation BBS bit in the U2SMR Wait for bus release. register is 1 ? (bus busy) 0 (bus free) U2SMR4 ← 70h Set the STSPSEL bit to 0. U2MR ←...
Page 513 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.3.3 Arbitration The MCU determines whether the transmit data matches data input to the SDA2 pin on the rising edge of SCL2. If it does not match the input data, arbitration takes place at the SDA2 pin by stopping data output.
Page 514 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) (1) SWC bit function SDA2 (master) SCL2 (master) SDA2 (slave) Address bit comparison, acknowledge generation SCL2 (slave) Clock line is Clock line is held low released (2) SWC9 bit function (SWC = 0) SDA2 (master) SCL2 (master)
Page 515 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) (1) Clock synchronization Clock output of other device SCL2 Internal clock Change the internal clock Resume Stop counting signal from high to low to counting start counting low period (2) Synchronization period Internal clock SCL2...
Page 516 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) To be compatible with SCL low hold from another device, the high time count starts after high is determined. 1 / (2f (theoretical value)) 1 / (2f (theoretical value)) SCL clock Noise filter width + 1 to 1.5 cycles...
Page 517 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.3.7 SDA Digital Delay When transferring data with the I 2 C-bus, change the data while the SCL clock is low. When SDA is changed while the SCL clock is a high, the change is recognized as one of the corresponding conditions (see 21.5.3.3 “Setup and Hold Times When Generating a Start/Stop Condition”).
Page 518 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) UART2 Transmit Buffer Register (UiTB) b8 b7 Set these bits to 1 to release the SDA2 pin 0: ACK generated 1: NACK generated Figure 21.25 UiTB Register Setting (SDA Input) - ACK (Receiver) Released (Hi-Z)
Page 519 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.4 Special Mode 2 (UART2) In special mode 2, the serial interface module allows serial communication between one master and multiple slaves. The transmit/receive clock polarity and phase are selectable. Table 21.18 lists Special Mode 2 Specifications.
Page 520 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) P1_3 P1_2 P7_2 (CLK2) P7_1 (RXD2) P7_0 (TXD2) MCU (master) MCU (slave) MCU (slave) Figure 21.27 Serial Bus Communication Control Example in Special Mode 2 Table 21.19 I/O Pin Functions in Special Mode 2 Pin Name Function...
Page 521 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Table 21.20 Registers Used and Settings in Special Mode 2 Register Bits Function UCLKSEL0 OCOSEL0 Select clock prior to division for UART0 to UART2. PCLKR PCLK1 Select the count source for the U2BRG register. 0 to 7 Set transmission data.
Page 522 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.4.1 Clock Phase Setting Function One of four combinations of transmit/receive clock phases and polarities can be selected using the CKPH bit in the U2SMR3 register and the CKPOL bit in the U2C0 register. Make sure the transmit/receive clock polarity and phase are the same for the master and slaves to be used for communication.
Page 523 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.5 Special Mode 3 (IE Mode) (UART2) In this mode, 1 bit of IEBus is approximated by 1 byte of UART mode waveform. Table 21.21 lists the Registers Used and Settings in IE Mode. Figure 21.29 shows the Bus Collision Detect Function-Related Bits.
Page 524 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) (1) The ABSCS Bit in the U2SMR Register (Bus collision detect sampling clock select) If the ABSCS bit is 0, bus collision is determined at the rising edge of the transmit/receive clock Transmit/ receive clock TXD2...
Page 525 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.6 Special Mode 4 (SIM Mode) (UART2) In this mode, the serial interface module allows SIM interface devices to communicate in UART mode. Both direct and inverted formats are available. The TXD2 pin outputs a low-level signal when a parity error is detected.
Page 526 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Table 21.23 Registers Used and Settings in SIM Mode Register Function 0 to 7 Set transmit data. U2TB 0 to 7 Received data can be read. U2RB OER, FER, PER, SUM Error flag U2BRG 0 to 7...
Page 527 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) (1) Transmit Timing Transmit/receive clock TE bit in U2C1 register Data is written to the U2TB register. (Note 1) TI bit in U2C1 register Data is transferred from the U2TB register to the UART2 transmit Stop Start...
Page 528 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Figure 21.31 shows the Example of SIM Interface Connection. Connect pins TXD2 and RXD2, and then place a pull-up resistance. SIM card TXD2 RXD2 Figure 21.31 Example of SIM Interface Connection 21.3.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 (error signal...
Page 529 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.3.6.2 Formats Two formats are available: direct format and inverse format. For direct format, set the PRYE bit in the U2MR register to 1 (parity enabled), the PRY bit to 1 (even parity), the UFORM bit in the U2C0 register to 0 (LSB first), and the U2LCH bit in the U2C1 register to 0 (not inverted).
Page 530 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.4 Interrupts UART0 to UART4 include interrupts by transmission, reception, ACK, NACK, start/stop condition detection, and bus collision detection. 21.4.1 Interrupt Related Registers Refer to operation examples in each mode for interrupt sources and interrupt request generation timing. For details of interrupt control, refer to 12.7 “Interrupt Control”.
Page 531 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) Some interrupts of UART0 to UART4 share interrupt vectors and interrupt control registers with other peripheral functions. When using these interrupts, select them by interrupt source select registers. Table 21.25 lists Interrupt Selection in UART0 to UART4.
Page 532 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.5 Notes on Serial Interface UARTi (i = 0 to 4) 21.5.1 Common Notes on Multiple Modes Influence of SD 21.5.1.1 When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three- phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance: P7_2/CLK2/TA1OUT/V/RXD1, P7_3/ CTS2 / RTS2 /TA1IN/ V /TXD1, P7_4/TA2OUT/W, P7_5/TA2IN/ W , P8_0/TA4OUT/U/TSUDA, P8_1/TA4IN/ U /TSUDB...
Page 533 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.5.2.3 Reception In clock synchronous serial I/O mode, a shift clock is generated by activating a transmitter. Set the UARTi-associated registers for a transmit operation even if the MCU is used for a receive operations only.
Page 534 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.5.3.3 Setup and Hold Times When Generating a Start/Stop Condition When generating a start condition, the hold time (t :STA) is a half cycle of the SCL clock. When generating a stop condition, the setup time (t :STO) is a half cycle of the SCL clock.
Page 535 M16C/5L Group, M16C/56 Group 21. Serial Interface UARTi (i = 0 to 4) 21.5.3.5 Restart Condition in Slave Mode When a restart condition is detected in slave mode, the successive processes may not be executed correctly. In slave mode, do not use a restart condition. 21.5.3.6 Requirements to Start Transmission/Reception in Slave Mode When transmission/reception is started in slave mode and the TXEPT bit in the UiC0 register is 1 (no...
Page 536 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22. Multi-master I C-bus Interface 22.1 Introduction The multi-master I C-bus interface (I C interface) is a serial communication circuit based on the I C-bus data transmit/receive format, and is equipped with arbitration lost detect and clock synchronous functions. Table 22.1 lists the Multi-master I C-bus Interface Specifications, Table 22.2 lists the I C Interface...
Page 537 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface Table 22.2 C Interface Detection Function Item Function A function to detect a slave address match when in slave transmission/reception. If slave address match is detected, an ACK is Slave address match returned.
Page 538 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface I2C0 control register 1 (S3D0) ICK1 ICK0 WIT SIM I2C0 address register 2 (S0D2) I2C0 address register 1 (S0D1) I2C0 status register 1 (S11) I2C0 address register 0 (S0D0) C-bus Interrupt interface SCL/SDA Address comparator...
Page 539 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.2 Registers Descriptions Table 22.4 lists registers associated with multi-master I C-bus interface. When the CM07 bit in the CM0 register is set to 1 (sub clock is CPU clock), registers listed in Table 22.4 should not be accessed. Set them after the CM07 bit is set to 0 (main clock, PLL clock, or on-chip oscillator clock).
Page 540 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.2.1 I2C0 Data Shift Register (S00) I2C0 Data Shift Register Symbol Address Reset Value 02B0h Function Transmit/receive data is stored. When the I C interface is a transmitter, write transmit data to the S00 register. When the I C interface is a receiver, received data can be read from the S00 register.
Page 541 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.2.2 I2C0 Address Register i (S0Di) (i = 0 to 2) I2C0 Address Register i (i = 0 to 2) b7 b6 b5 b4 Reset Value Symbol Address S0D0 02B2h 0000 000Xb 0000 000Xb S0D1 02BAh...
Page 542 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.2.3 I2C0 Control Register 0 (S1D0) I2C0 Control Register 0 Symbol Address Reset Value b7 b6 b5 b4 S1D0 02B3h Bit Symbol Bit Name Function b2 b1 b0 0 0 0: 8 0 0 1: 7 0 1 0: 6 Bit counter (number of...
Page 543 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface • Bits AAS2 to AAS0 in the S11 register: 0 (slave address not matches) • The TOF bit in the S4D0 register: 0 (timeout not detected) ALS (Data format select bit) (b4) The ALS bit is enabled in slave mode.
Page 544 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.2.4 I2C0 Clock Control Register (S20) I2C0 Clock Control Register Symbol Address Reset Value b7 b6 b5 b4 02B4h Bit Symbol Bit Name Function CCR0 CCR1 Refer to bits CCR4 to CCR0 (Bit Rate CCR2 Bit rate control bit Control Bit) (b4 to b0) in the next page.
Page 545 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface FASTMODE (SCL mode select bit) (b5) When using the fast-mode I C-bus standard (maximum 400 kbps), set the FASTMODE bit to 1 (fast- mode) and set fVIIC to 4 MHz or more. Rewrite the FASTMODE bit when the ES0 bit in the S1D0 register is 0 (disabled).
Page 546 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.2.5 I2C0 Start/Stop Condition Control Register (S2D0) I2C0 Start/Stop Condition Control Register Symbol Address Reset Value b7 b6 b5 b4 S2D0 02B5h 0001 1010b Bit Symbol Bit Name Function SSC0 SSC1 Refer to SSC4 to SSC0 (Start/Stop SSC2 Start/stop condition setting bit...
Page 547 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.2.6 I2C0 Control Register 1 (S3D0) I2C0 Control Register 1 Symbol Address Reset Value b6 b5 b4 0011 0000b S3D0 02B6h Bit Symbol Bit Name Function 0: I C-bus interrupt by stop condition detection Stop condition detect interrupt is disabled enable bit...
Page 548 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface WIT (Data receive interrupt enable bit) (b1) The WIT bit is enabled in master reception or slave reception. The WIT bit has two functions: • Selects the I C-bus interrupt timing when data is received. (write) •...
Page 549 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface When setting the WIT bit to 1 in receive mode, and the ACK clock is present: C-bus interrupt is enabled at eighth clock) SCLMM clock SDAMM ACKBIT bit in the Write by a program S20 register PIN bit in the S10 register Internal WAIT flag...
Page 550 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface ICK1 and ICK0 (I C-bus system clock select bit) (b7-b6) Rewrite these bits when the ES0 bit in the S1D0 register is 0 (I C interface disabled). fVIIC is selected by setting all the bits ICK1 to ICK0, bits ICK4 to ICK2 in the S4D0 register, and the PCLK0 bit in the PCLKR register.
Page 551 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.2.7 I2C0 Control Register 2 (S4D0) I2C0 Control Register 2 Symbol Address Reset Value b7 b6 b5 b4 S4D0 02B7h Bit Symbol Bit Name Function Timeout detect function 0: Disabled enable bit 1: Enabled 0: Not detected Timeout detect flag...
Page 552 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface TOSEL (Timeout detect time select bit) (b2) Set the TOSEL bit to select a timeout detection period. The TOSEL bit is enabled when the TOE bit is 1 (timeout detect function enabled). When long time is selected, the internal counter increments fVIIC as a 16-bit counter.
Page 553 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.2.8 I2C0 Status Register 0 (S10) I2C0 Status Register 0 Symbol Address Reset Value b7 b6 b5 b4 0001 000Xb 02B8h Bit Symbol Bit Name Function When read, 0: Last bit = 0 1: Last bit = 1 Last receive bit When write, see Table 22.9 “Functions...
Page 554 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface Table 22.9 lists Functions Enabled by Writing to the S10 Register. Only set the values listed in Table 22.9. If the values listed in Table 22.9 are written to the S10 register, the 6 lower bits in the S10 register will not be changed.
Page 555 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface AAS (Slave address compare flag) (b2) The AAS bit function in read access is described below. See Table 22.9 “Functions Enabled by Writing to the S10 Register” for the bit function in write access. Conditions to become 0: •...
Page 556 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface PIN (I C-bus interface interrupt request bit) (b4) The PIN bit function in read access is described below. See Table 22.9 “Functions Enabled by Writing to the S10 Register” for the bit function in write access. Conditions to become 0: •...
Page 557 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface TRX (Communication mode select bit 0) (b6) Set the TRX bit to select transmit mode or receive mode. Conditions to become 0: • The TRX bit is set to 0 by a program. •...
Page 558 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.2.9 I2C0 Status Register 1 (S11) I2C0 Status Register 1 Symbol Address Reset Value b7 b6 b5 b4 02B9h XXXX X000b Bit Symbol Bit Name Function 0: No address matched AAS0 Slave address 0 compare flag 1: Address matched 0: No address matched...
Page 559 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3 Operations 22.3.1 Clock Figure 22.5 shows the I C-bus Interface Clock. PCLKR register PCLK0 = 1 f1IIC System clock select fIIC circuit C-bus system clock f2IIC Divide-by-2 Divide-by-m fVIIC PCLK0 = 0 S20 register FASTMODE = 0 Divide-by-8...
Page 560 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.1.2 Bit Rate and Duty Cycle Bit rate is determined by a combination of fVIIC, the FASTMODE bit in the S20 register, and bits CCR4 to CCR0 in the S20 register. Table 22.10 lists the Bit Rate of Internal SCL Output and Duty Cycle.
Page 561 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.1.3 Receiving a Slave Address in Wait Mode and Stop Mode When the CM02 bit in the CM0 register is set to 0 (peripheral clock f1 does not stop in wait mode) and transition is made to wait mode, the I C interface can receive the slave address even in wait mode.
Page 562 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.2 Generating a Start Condition Follow the procedure below when the ES0 bit in the S1D0 register is 1 (I C interface enabled) and the BB bit in the S10 register is set to 0 (bus free). Figure 22.6 shows the Procedure to Generate a Start Condition.
Page 563 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface The start condition generation timing depends on the modes - standard clock mode or fast-mode. Figure 22.7 shows the Start Condition Generation Timing. Table 22.12 lists the Setup/Hold Time for Generating a Start/Stop Condition. Write signal to the S00 register SCLMM Setup...
Page 564 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.3 Generating a Stop Condition Use the following procedure when the ES0 bit in the S1D0 register is 1 (I C interface enabled). (1) Write C0h to the S10 register. The I C interface enters the stop condition standby state and the SDAMM pin is driven low.
Page 565 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.4 Generating a Restart Condition Use the following procedure to generate a restart condition when 1-byte data is transmitted/received. (1) Write E0h to the S10 register. (Start condition standby state. The SDAMM pin released.) (2) Wait until the SDAMM pin level becomes high.
Page 566 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.5 Start Condition Overlap Protect The I C interface generates a start condition by setting registers S10 and S00 by a program. The bus system must be free before setting these registers. Check whether the bus is free with the BB bit in the S10 register by a program before setting the registers.
Page 567 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface The start condition overlap protect is enabled from the falling edge of SDAMM (start condition) to the completion of the slave address receive. If data is written to registers S10 and S00 during that period, the above operation is performed.
Page 568 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.6 Arbitration Lost When all of the conditions below are met, the SDAMM pin signal level becomes low by an external device and the I C interface determines that it has lost arbitration. (a) Transmit/receive (one of the following) •...
Page 569 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface When arbitration lost is detected: • The AL bit in the S10 register becomes 1 (arbitration lost detected) • Internal SDA output becomes high. (SDAMM released) • The I C interface enters the slave receive mode The TRX bit in the S10 register is 0 (receive mode).
Page 570 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.7 Detecting Start/Stop Conditions Figure 22.13 shows Start Condition Detection, Figure 22.14 shows Stop Condition Detection, and Table 22.13 lists Conditions to Detect Start/Stop Condition. A start/stop condition can be detected only when the start/stop condition detect parameters are selected by setting bits SSC4 to SSC0 in the S2D0 register, and the signals input to pins SCLMM and SDAMM meet all three conditions (SCLMM release time, setup time, and hold time) listed in Table 22.13.
Page 571 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface Table 22.13 Conditions to Detect Start/Stop Condition Standard Clock Mode Fast-Mode SCLMM open time SSC value + 1 cycle 4 cycles SSC value 1 cycle --------------------------- - Setup time 2 cycles SSC value Hold time 2 cycles...
Page 572 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.8 Operation after Transmitting/Receiving a Slave Address or Data After a slave address or 1-byte data has been transmitted/received, the PIN bit in the S10 register becomes 0 (interrupt requested) at the falling edge of the ACK clock. The IR bit in the IICIC register becomes 1 (interrupt requested) at the same time.
Page 573 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.9 Timeout Detection When the SCL clock is stopped during transmission/reception, each device stops operating, keeping the communication state. To avoid this, the I C interface incorporates a function to detect timeouts and generate an I C-bus interrupt request when the SCLMM pin is driven high for more than the selected timeout detection period during transmission/reception.
Page 574 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.10 Data Transmit/Receive Examples The data transmit/receive examples are described in this section. The conditions for the examples are as follows: • Slave address: 7 bits • Data: 8 bits • ACK clock •...
Page 575 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.10.2 Master Transmission Master transmission is described in this section. The initial settings described in 22.3.10.1 “Initial Settings” are assumed to be completed. Figure 21.17 shows master transmission operation. The following programs (A) to (C) are executed at (A) to (C) in Figure 22.17, respectively. S: Start condition A: ACK R: Read...
Page 576 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.10.3 Master Reception Master reception is described in this section. The initial settings described in 22.3.10.1 “Initial Settings” are assumed to be completed. Figure 22.18 shows the operation example of master reception.
Page 577 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.10.4 Slave Reception The slave reception is described in this section. The initial settings described in 222.3.10.1 “Initial Settings” are assumed to be completed. Figure 22.19 shows the example of slave reception. The following programs (A) to (C) are executed at (A) to (C) in Figure 22.19, respectively.
Page 578 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.3.10.5 Slave Transmission Slave transmission is described in this section. The initial settings described in 22.3.10.1 “Initial Settings” are assumed to be completed. Figure 22.20 shows the example of slave transmission. The following programs (A) to (B) are executed at (A) and (B) in Figure 22.20, respectively.
Page 579 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.4 Interrupts The I C interface generates interrupt requests. Figure 22.21 shows I C Interface Interrupts, and Table 22.15 lists I C-bus Interrupts. C-bus Interrupt ACKCLK bit in the S20 register Falling edge of the last bit clock (Data transmit/receive of transmit/receive data detected...
Page 580 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface Table 22.15 C-bus Interrupts Associated Bits (Register) Interrupt Interrupt Interrupt Source Control Interrupt Interrupt Register enabled request Completion of data transmit/receive When the ACKCLK bit in the S20 register is 0: Detection of the falling edge of the last clock of transmit/receive data through the SCLMM pin —...
Page 581 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface Table 22.16 Registers Associated with I C Interface Interrupts Address Register Symbol Reset Value I2C-bus Interface Interrupt Control 007Bh IICIC XXXX X000b Register 007Ch SCL/SDA Interrupt Control Register SCLDAIC XXXX X000b 0206h Interrupt Source Select Register 2 IFSR2A...
Page 582 M16C/5L Group, M16C/56 Group 22. Multi-master I C-bus Interface 22.5 Notes on Multi-master I C-bus Interface 22.5.1 Limitation on CPU Clock When the CM07 bit in the CM0 register is 1 (CPU clock is a sub clock), do not access the registers listed in Table 22.4 “Registers”.
Page 583 M16C/5L Group, M16C/56 Group 23. CAN Module 23. CAN Module Note Do not use CAN function in the M16C/56 Group. The M16C/5L Group implements one channel (referred to as CAN0) of the Controller Area Network (CAN) module that complies with the ISO11898-1 Specifications. The CAN module transmits and receives both formats of messages, namely the standard identifier (11 bits) (identifier hereafter referred to as ID) and extended ID (29 bits).
Page 584 M16C/5L Group, M16C/56 Group 23. CAN Module Table 23.2 CAN Module Specifications (2) Item Specification • CAN bus errors (stuff error, form error, ACK error, CRC error, bit error, and ACK delimiter error) can be monitored. Error status monitoring • Transition to error states can be detected (error-warning, error-passive, bus-off entry, and bus-off recovery).
Page 585 M16C/5L Group, M16C/56 Group 23. CAN Module Peripheral bus CAN SFRs CRX0 Acceptance filter Protocol controller ID priority transmit CTX0 Message box controller fCANCLK Timer Baud rate prescaler (BRP) BCLK CAN0 wake-up interrupt CCLKS fCAN CAN0 reception complete interrupt CAN0 transmission complete interrupt Main clock Interrupt CAN0 receive FIFO interrupt...
Page 586 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1 CAN SFRs The CAN-associated registers are shown in Figures 23.2 to 23.11, 23.13, 23.14, 23.16 to 23.20, 23.22, and 23.24 to 23.30. R01UH0127EJ0110 Rev.1.10 Page 549 of 803 Sep 01, 2011...
Page 587 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.1 CAN0 Control Register (C0CTLR) CAN0 Control Register Symbol Address Reset Value C0CTLR D7C1h-D7C0h 0000 0000 0000 0101b Bit Symbol Bit Name Function b1 b0 0 0 : CAN operation mode CAN Operating Mode CANM 0 1 : CAN reset mode Select Bit...
Page 588 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.1.1 CANM Bit The CANM bit selects one of the following modes for the CAN module: CAN operation mode, CAN reset mode, or CAN halt mode. Refer to 23.2 “Operating Mode” for details. CAN sleep mode is set by the SLPM bit.
Page 589 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.1.5 CPE Bit When the CPE bit is set to 1, the function of the CAN I/O pins (CRX0 and CTR0) is enabled. To use the CAN module, set this bit to 1. To set the CPE bit to 1, set the port direction bit corresponding to the CRX0 pin to 0.
Page 590 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.1.8 MLM Bit The MLM bit specifies the operation when a new message is captured in the unread mailbox. Overwrite mode or overrun mode can be selected. All mailboxes (including the receive FIFO) are set to either overwrite mode or overrun mode.
Page 591 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.2 CAN0 Clock Select Register (C0CLKR) CAN0 Clock Select Register b7 b6 b5 b4 Symbol Address Reset Value C0CLKR D7C7h Bit Symbol Bit Name Function CAN Clock Source 0: BCLK CCLKS Select Bit 1: Main clock —...
Page 592 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.3 CAN0 Bit Configuration Register (C0BCR) CAN0 Bit Configuration Register (1, 2) b16b15 Symbol Address Reset Value C0BCR D7C6h-D7C4h 00 0000h Bit Symbol Bit Name Function If the setting value is P (0 to 1023), Prescaler Division Ratio the baud rate prescaler divides fCAN Set Bit (10 bits)
Page 593 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.3.1 BRP Bit The BRP bit is used to set the frequency of the CAN communication clock (fCANCLK). The cycle of fCANCLK is set to be 1 Time Quantum (Tq). 23.1.3.2 TSEG1 Bit The TSEG1 bit is used to specify the total length of the propagation time segment (PROP_SEG) and phase buffer segment 1 (PHASE_SEG1) with the value of Tq.
Page 594 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.4 CAN0 Mask Register k (C0MKRk) (k = 0 to 7) CAN0 Mask Register k (k = 0 to 7) b31b28 b18b17 Symbol Address Reset Value 0 0 0 C0MKR0, C0MKR1 D703h-D700h, D707h-D704h Undefined C0MKR2, C0MKR3 D70Bh-D708h, D70Fh-D70Ch...
Page 595 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.5 CAN0 FIFO Received ID Compare Register n (C0FIDCR0 to C0FIDCR1) (n = 0, 1) CAN0 FIFO Received ID Compare Register n (n = 0, 1) Symbol Address Reset Value b31b28 b18b17 C0FIDCR0 D723h-D720h Undefined C0FIDCR1...
Page 596 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.5.3 RTR Bit The RTR bit sets the specified frame format of data frames or remote frames. This bit specifies the following operation: • When both RTR bits in registers C0FIDCR0 and C0FIDCR1 are set to 0, only data frames can be received.
Page 597 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.6 CAN0 Mask Invalid Register (C0MKIVLR) CAN0 Mask Invalid Register Normal mailbox mode Symbol Address Reset Value C0MKIVLR D72Bh-D728h Undefined Bit Symbol Bit Name Bit Name Function — 0: Mask valid Mask Invalid Bit (b31-b0) 1: Mask invalid FIFO mailbox mode...
Page 598 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.7 CAN0 Mailbox Register j (C0MBj) (j = 0 to 31) Table 23.4 lists the CAN0 mailbox memory mapping, and Table 23.5 lists the CAN data frame structure. The value after reset of CAN0 mailbox is undefined. Table 23.4 CAN0 Mailbox Memory Mapping Address...
Page 599 M16C/5L Group, M16C/56 Group 23. CAN Module CAN0 Mailbox Register j (j = 0 to 31) Symbol Address Reset Value C0MB0 to C0MB31 D500h to D6FFh Undefined Bit Symbol Bit Name Function 0: Corresponding EID bit is 0 Extended ID 1: Corresponding EID bit is 1 0: Corresponding SID bit is 0 Standard ID...
Page 600 M16C/5L Group, M16C/56 Group 23. CAN Module The previous value of each mailbox is retained unless a new message is received. 23.1.7.1 EID Bit The EID bit sets the extended ID of data frames and remote frames. This bit is used to transmit or receive extended ID messages.
Page 601 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.7.5 DLC (Data Length Code) The DLC is used to set the number of data bytes to be transmitted in a data frame. When data is requested using a remote frame, the number of data bytes to be requested is set. When a data frame is received, the number of received data bytes is stored.
Page 602 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.8 CAN0 Mailbox Interrupt Enable Register (C0MIER) CAN0 Mailbox Interrupt Enable Register (1, 2) Normal mailbox mode Symbol Address Reset Value C0MIER D72Fh-D72Ch Undefined Bit Symbol Bit Name Bit Name Function — 0: Interrupt disabled Interrupt Enable Bit (b31-b0) 1: Interrupt enabled...
Page 603 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.9 CAN0 Message Control Register (C0MCTLj) (j = 0 to 31) CAN0 Message Control Register j (1, 2) (j = 0 to 31) b7 b6 b5 b4 Symbol Address Reset Value C0MCTL0 to C0MCTL31 D7A0h to D7BFh Bit Symbol Bit Name...
Page 604 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.9.1 NEWDATA Bit The NEWDATA bit is set to 1 when a new message is being stored or has been stored to the mailbox. The timing for setting this bit to 1 is simultaneous with the INVALDATA bit. The NEWDATA bit is set to 0 by writing 0 by a program.
Page 605 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.9.7 ONESHOT Bit The ONESHOT bit can be used in the following two ways, receive mode and transmit mode: (1) One-Shot Receive Mode When the ONESHOT bit is set to 1 in receive mode (RECREQ bit = 1 and TRMREQ bit = 0), the mailbox receives a message only one time.
Page 606 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.9.9 TRMREQ Bit The TRMREQ bit selects transmit modes shown in Table 23.11. When this bit is set to 1, the corresponding mailbox is configured for transmission of a data frame or a remote frame.
Page 607 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.10 CAN0 Receive FIFO Control Register (C0RFCR) CAN0 Receive FIFO Control Register b7 b6 b5 b4 Symbol Address Reset Value C0RFCR D7C8h 1000 0000b Bit Symbol Bit Name Function Receive FIFO 0: Receive FIFO disabled Enable Bit 1: Receive FIFO enabled b3 b2 b1...
Page 608 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.10.1 RFE Bit When the RFE bit is set to 1, the receive FIFO is enabled. When this bit is set to 0, the receive FIFO is disabled for reception and becomes empty (RFEST bit = Do not set this bit to 1 in normal mailbox mode (MBM bit in the C0CTLR register = 0).
Page 609 M16C/5L Group, M16C/56 Group 23. CAN Module Receive FIFO mailbox Frame 1 Frame 2 Frame 3 Frame 4 CAN bus Frame Frame Frame Frame Internal bus Frame Frame Frame Frame RFEST RFWST RFFST CAN0 receive FIFO interrupt Bits 29 to 28 in the C0MIER register = 01b CAN0 receive FIFO interrupt Bits 29 to 28 in the C0MIER register = 11b C0RFPCR register...
Page 610 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.11 CAN0 Receive FIFO Pointer Control Register (C0RFPCR) CAN0 Receive FIFO Pointer Control Register Symbol Address Reset Value C0RFPCR D7C9h Undefined Function Setting Value The CPU-side pointer for the receive FIFO is incremented by writing FFh Figure 23.13 C0RFPCR Register When the receive FIFO is not empty, write FFh to the C0RFPCR register by a program to increment the...
Page 611 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.12 CAN0 Transmit FIFO Control Register (C0TFCR) CAN0 Transmit FIFO Control Register b7 b6 b5 b4 Symbol Address Reset Value C0TFCR D7CAh 1000 0000b Bit Symbol Bit Name Function Transmit FIFO 0: Transmit FIFO disabled Enable Bit 1: Transmit FIFO enabled b3 b2 b1...
Page 612 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.12.3 TFFST Bit The TFFST bit is set to 1 (transmit FIFO is full) when the number of unsent messages in the transmit FIFO is 4. This bit is set to 0 (transmit FIFO is not full) when the number of unsent messages in the transmit FIFO is less than 4.
Page 613 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.13 CAN0 Transmit FIFO Pointer Control Register (C0TFPCR) CAN0 Transmit FIFO Pointer Control Register Symbol Address Reset Value C0TFPCR D7CBh Undefined Function Setting Value The CPU-side pointer for the transmit FIFO is incremented by writing FFh Figure 23.16 C0TFPCR Register When the transmit FIFO is not full, write FFh to the C0TFPCR register by a program to increment the...
Page 614 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.14 CAN0 Status Register (C0STR) CAN0 Status Register Symbol Address Reset Value C0STR D7C3h-D7C2h 0000 0000 0000 0101b Bit Symbol Bit Name Function 0: Not in CAN reset mode RSTST CAN Reset Status Flag 1: In CAN reset mode 0: Not in CAN halt mode HLTST...
Page 615 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.14.1 RSTST Bit The RSTST bit is set to 1 when the CAN module is in CAN reset mode. This bit is set to 0 when the CAN module is not in CAN reset mode. Even when the state is changed from CAN reset mode to CAN sleep mode, the RSTST bit remains 1.
Page 616 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.14.9 SDST Bit The SDST bit is set to 1 when at least one SENTDATA bit in the C0MCTLj register (j = 0 to 31) is 1 regardless of the value of the C0MIER register. The SDST bit is set to 0 when all SENTDATA bits are 0.
Page 617 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.15 CAN0 Mailbox Search Mode Register (C0MSMR) CAN0 Mailbox Search Mode Register (b15) (b8) b7 b6 b5 b4 Symbol Address Reset Value C0MSMR D7D3h 0000 0000b Bit Symbol Bit Name Function b1 b0 0 0 : Receive mailbox search mode Mailbox Search Mode MBSM...
Page 618 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.16 CAN0 Mailbox Search Status Register (C0MSSR) CAN0 Mailbox Search Status Register b7 b6 b5 b4 Symbol Address Reset Value C0MSSR D7D2h 1000 0000b Bit Symbol Bit Name Function Output of search result in each search Search Result Mailbox MBNST mode...
Page 619 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.16.1 MBNST Bit The MBNST bit outputs the smallest mailbox number that is searched in each mode of the C0MSMR register. In receive mailbox, transmit mailbox, and message lost search modes, the value of the mailbox i.e.,the search result to be output, is updated as described below: •...
Page 620 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.17 CAN0 Channel Search Support Register (C0CSSR) CAN0 Channel Search Support Register (1, 2) Symbol Address Reset Value C0CSSR D7D1h Undefined Function Setting Value When the value of the channel search is input, the channel Channel value number is output to the CiMSSR register Notes:...
Page 621 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.18 CAN0 Acceptance Filter Support Register (C0AFSR) CAN0 Acceptance Filter Support Register Symbol Address Reset Value C0AFSR D7D7h-D7D6h Undefined Function Setting Value After the standard ID of a received message is written, Standard ID/ the value converted for data table search can be read converted value Note:...
Page 622 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.19 CAN0 Error Interrupt Enable Register (C0EIER) CAN0 Error Interrupt Enable Register b7 b6 b5 b4 Symbol Address Reset Value C0EIER D7CCh Bit Symbol Bit Name Function Bus Error Interrupt 0: Bus error interrupt disabled BEIE Enable Bit 1: Bus error interrupt enabled...
Page 623 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.19.1 BEIE Bit When the BEIE bit is 0, no error interrupt request is generated even if the BEIF bit in the C0EIFR register is set to 1. When the BEIE bit is 1, an error interrupt request is generated if the BEIF bit is set to 1. 23.1.19.2 EWIE Bit When the EWIE bit is 0, no error interrupt request is generated even if the EWIF bit in the C0EIFR register is set to 1.
Page 624 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.20 CAN0 Error Interrupt Factor Judge Register (C0EIFR) CAN0 Error Interrupt Factor Judge Register b7 b6 b5 b4 Symbol Address Reset Value C0EIFR D7CDh Bit Symbol Bit Name Function Bus Error 0: No bus error detected BEIF Detect Flag 1: Bus error detected...
Page 625 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.20.3 EPIF Bit The EPIF bit is set to 1 when the CAN error state becomes error-passive (the REC or TEC value exceeds 127). This bit is set to 1 only when the REC or TEC initially exceeds 127. Thus, if 0 is written by a program while the REC or TEC remains greater than 127, this bit is not set to 1 until the REC and the TEC go below 127 and then exceed 127 again.
Page 626 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.20.7 OLIF Bit The OLIF bit is set to 1 if the transmitting condition of an overload frame is detected when the CAN module performs transmission or reception. 23.1.20.8 BLIF Bit The BLIF bit is set to 1 if 32 consecutive dominant bits are detected on the CAN bus while the CAN module is in CAN operation mode.
Page 627 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.21 CAN0 Receive Error Count Register (C0RECR) CAN0 Receive Error Count Register Symbol Address Reset Value C0RECR D7CEh Function Counter Value Receive error count function The C0RECR register increments or decrements the counter 00h to FFh value according to the error status of the CAN module during reception...
Page 628 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.22 CAN0 Transmit Error Count Register (C0TECR) CAN0 Transmit Error Count Register Symbol Address Reset Value C0TECR D7CFh Function Counter Value Transmit error count function The C0TECR register increments or decrements the counter 00h to FFh value according to the error status of the CAN module during transmission...
Page 629 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.23 CAN0 Error Code Store Register (C0ECSR) CAN0 Error Code Store Register b7 b6 b5 b4 Symbol Address Reset Value C0ECSR D7D0h Bit Symbol Bit Name Function 0: No stuff error detected (1, 2) Stuff Error Flag 1: Stuff error detected 0: No form error detected...
Page 630 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.23.4 CEF Bit The CEF bit is set to 1 when a CRC error is detected. 23.1.23.5 BE1F Bit The BE1F bit is set to 1 when a recessive bit error is detected. 23.1.23.6 BE0F Bit The BE0F bit is set to 1 when a dominant bit error is detected.
Page 631 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.24 CAN0 Time Stamp Register (C0TSR) CAN0 Time Stamp Register Symbol Address Reset Value C0TSR D7D5h-D7D4h 0000h Function Counter Value Free-running counter value for the time stamp function 0000h to FFFFh Note: 1. Read the C0TSR register in 16-bit units. Figure 23.29 C0TSR Register When the C0TSR register is read, the value of the time stamp counter (16-bit free-running counter) at that moment is read.
Page 632 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.25 CAN0 Test Control Register (C0TCR) CAN0 Test Control Register b7 b6 b5 b4 Symbol Address Reset Value 0 0 0 C0TCR D7D8h Bit Symbol Bit Name Function 0: CAN test mode disabled TSTE CAN Test Mode Enable Bit 1: CAN test mode enabled...
Page 633 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.25.3 Listen-Only Mode The ISO 11898-1 recommends an optional bus monitoring mode. In listen-only mode, the CAN node is able to receive valid data frames and valid remote frames. It sends only recessive bits on the CAN bus and the protocol controller is not required to send the ACK bit, overload flag, or active error flag.
Page 634 M16C/5L Group, M16C/56 Group 23. CAN Module 23.1.25.5 Self-Test Mode 1 (Internal Loop Back) Self-test mode 1 is provided for self-test functions. In this mode, the protocol controller treats its transmitted messages as received messages and stores them into the receive mailbox. To be independent from external stimulation, the protocol controller generates the ACK bit.
Page 635 M16C/5L Group, M16C/56 Group 23. CAN Module 23.2 Operating Mode The CAN module has the following four operating modes: • CAN reset mode • CAN halt mode • CAN operation mode • CAN sleep mode Figure 23.34 shows the transition between CAN operating modes. CPU reset SLPM = 0 when CANM = 00b...
Page 636 M16C/5L Group, M16C/56 Group 23. CAN Module 23.2.1 CAN Reset Mode CAN reset mode is provided for CAN communication configuration. When the CANM bit in the C0CTLR register is set to 01b, the CAN module enters CAN reset. Then the RSTST bit in the C0STR register is set to 1.
Page 637 M16C/5L Group, M16C/56 Group 23. CAN Module 23.2.2 CAN Halt Mode CAN halt mode is used for mailbox configuration and test mode setting. When the CANM bit in the C0CTLR register is set to 10b, CAN halt mode is selected. Then the HLTST bit in the C0STR register is set to 1.
Page 638 M16C/5L Group, M16C/56 Group 23. CAN Module 23.2.3 CAN Sleep Mode CAN sleep mode is used for reducing current consumption by stopping the clock supply to the CAN module. After MCU hardware reset or software reset, the CAN module starts from CAN sleep mode. When the SLPM bit in the C0CTLR register is set to 1, the CAN module enters CAN sleep mode.
Page 639 M16C/5L Group, M16C/56 Group 23. CAN Module 23.2.4 CAN Operation Mode (Excluding Bus-Off State) CAN operation mode is used for CAN communication. When the CANM bit in the C0CTLR register is set to 00b, the CAN module enters CAN operation mode. Then bits RSTST and HLTST in the C0STR register are set to 0.
Page 640 M16C/5L Group, M16C/56 Group 23. CAN Module 23.2.5 CAN Operation Mode (Bus-Off State) The CAN module enters the bus-off state according to the increment/decrement rules for the transmit/error counters in the CAN Specifications. The following cases apply when recovering from the bus-off state. When the CAN module is in bus-off state, the values of the associated registers, except registers C0STR, C0EIFR, C0RECR, C0TECR and C0TSR, remain unchanged.
Page 641 M16C/5L Group, M16C/56 Group 23. CAN Module 23.3 CAN Communication Speed Configuration The following description explains about the CAN communication speed configuration. 23.3.1 CAN Clock Configuration This group has a CAN clock selector. The CAN clock can be configured by setting the CCLKS bit in the C0CLKR register and the BRP bit in the C0BCR register.
Page 642 M16C/5L Group, M16C/56 Group 23. CAN Module 23.3.3 Bit rate The bit rate depends on the CAN clock (fCAN), the division value of the baud rate prescaler, and the number of Tq of 1-bit time. fCAN fCANCLK Bit rate bps ------------------------------------------------------------------------------------------------------------------------------------------------------------------ - ------------------------------------------------------------------ - Baud rate prescaler division value 1 ( ) number of Tq of 1 bit time...
Page 643 M16C/5L Group, M16C/56 Group 23. CAN Module 23.4 Mailbox and Mask Register Structure There are 32 mailboxes with the same structure. Figure 23.38 shows the structure of C0MBj register (j = 0 to 31). Address CAN0 EID7 EID6 EID5 EID4 EID3 EID2 EID1...
Page 644 M16C/5L Group, M16C/56 Group 23. CAN Module There are 2 FIFO received ID compare registers with the same structure. Figure 23.40 shows the structure of C0FIDCRn Register (n = 0, 1). Address CAN0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 D720h + n ×...
Page 645 M16C/5L Group, M16C/56 Group 23. CAN Module 23.5 Acceptance Filtering and Masking Function Acceptance filtering allows the user to receive messages with a specified range of multiple IDs for mailboxes. Registers C0MKR0 to C0MKR7 can perform masking of the standard ID and the extended ID of 29 bits. •...
Page 646 M16C/5L Group, M16C/56 Group 23. CAN Module Normal Mailbox Mode FIFO Mailbox Mode Mailbox [0] Mailbox [0] Mailbox [1] Mailbox [1] C0MKR0 register C0MKR0 register Mailbox [2] Mailbox [2] Mailbox [3] Mailbox [3] Mailbox [4] Mailbox [4] Mailbox [5] Mailbox [5] C0MKR1 register C0MKR1 register Mailbox [6]...
Page 647 M16C/5L Group, M16C/56 Group 23. CAN Module Mask bit values Setting value of ID setting value of 0: IDs not compared C0MKIVLR register C0MBj (j = 0 to 31) 1: IDs compared Setting value of ID value of C0MKRk register received message (k = 0 to 7) Acceptance judge signal...
Page 648 M16C/5L Group, M16C/56 Group 23. CAN Module 23.6 Reception and Transmission Table 23.11 list the CAN communication mode configuration. Table 23.11 Configuration for CAN Reception Mode and Transmission Mode TRMREQ RECREQ ONESHOT Communication Mode of Mailbox Mailbox disabled or transmission being aborted. Configurable only when transmission or reception from a mailbox (programmed in one-shot mode) is aborted.
Page 649 M16C/5L Group, M16C/56 Group 23. CAN Module 23.6.1 Reception Figure 23.43 shows an operation example of data frame reception in overwrite mode. This example shows the operation of overwriting the first message when the CAN module receives two consecutive CAN messages that matches the receiving conditions of the C0MCTL0 register. Receive message in mailbox 0 Receive message in mailbox 0 IFS SOF...
Page 650 M16C/5L Group, M16C/56 Group 23. CAN Module Figure 23.44 shows the operational example of data frame reception in overrun mode. This example shows the operation of overrunning the second message when the CAN module receives two consecutive CAN messages that matches the receiving conditions of the C0MCTL0 register. Receive message in mailbox 0 Receive message in mailbox 0 IFS SOF...
Page 651 M16C/5L Group, M16C/56 Group 23. CAN Module 23.6.2 Transmission Figure 23.45 shows an operation example of data frame transmission. This example shows the operation of transmitting messages that has been set in registers C0MCTL0 and C0MCTL1. Transmit message in mailbox 0 Transmit message in mailbox 1 IFS SOF delimiter...
Page 652 M16C/5L Group, M16C/56 Group 23. CAN Module 23.7 CAN Interrupt The CAN module provides the following CAN interrupts: • CAN0 reception complete interrupt • CAN0 transmission complete interrupt • CAN0 receive FIFO interrupt • CAN0 transmit FIFO interrupt • CAN0 error interrupt There are eight types of interrupt sources for the CAN0 error interrupts.
Page 653 M16C/5L Group, M16C/56 Group 24. A/D Converter 24. A/D Converter Note The 64-pin package has no AN0_4 to AN0_7 (P0_4 to P0_7), AN2_0 to AN2_3 (P1_0 to P1_3), AN2_5 to AN2_7 (P9_5 to P9_7). 24.1 Introduction The A/D converter consists of one 10-bit successive approximation A/D converter. Table 24.1 lists the A/D Converter Specifications and Figure 24.1 shows an A/D Converter Block Diagram.
Page 654 M16C/5L Group, M16C/56 Group 24. A/D Converter VREF Analog circuit AVSS ADSTBY Successive conversion register ADCON1 register ADCON0 register AD0 register (16 bits) AD1 register (16 bits) AD2 register (16 bits) AD3 register (16 bits) Decoder for register AD4 register (16 bits) AD5 register (16 bits) AD6 register (16 bits) AD7 register (16 bits)
Page 655 M16C/5L Group, M16C/56 Group 24. A/D Converter Table 24.2 I/O Ports Pin Name Function AN0 to AN7 Input Analog input AN0_0 to AN0_7 Input Analog input AN2_0 to AN2_7 Input Analog input Analog input AN3_0 to AN3_2 Input ADTRG Input Trigger input Note: Set the direction bit of the ports sharing a port to 0 (input mode).
Page 656 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.2.1 Open-Circuit Detection Assist Function Register (AINRST) Open-Circuit Detection Assist Function Register Symbol Address Reset Value b7 b6 b5 b4 AINRST XX00 XXXXb 03A2h Bit Symbol Bit Name Function — No register bits. If necessary, set to 0. The read value is undefined. —...
Page 657 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.2.2 A/D Register i (ADi) (i = 0 to 7) A/D Register i (i = 0 to 7) Symbol Address Reset Value (b15) (b8) 03C1h to 03C0h 0000 00XX XXXX XXXXb 03C3h to 03C2h 0000 00XX XXXX XXXXb 03C5h to 03C4h 0000 00XX XXXX XXXXb...
Page 658 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.2.3 A/D Control Register 2 (ADCON2) A/D Control Register 2 b6 b5 b4 Symbol Address Reset Value ADCON2 0000 X00Xb 03D4h Bit Symbol Bit Name Function — — No register bit. If necessary, set to 0. The read value is undefined. (b0) ADGSEL0 0 : AN0 to AN7...
Page 659 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.2.4 A/D Control Register 0 (ADCON0) A/D Control Register 0 b7 b6 b5 b4 Symbol Address Reset Value ADCON0 03D6h 0000 0XXXb Bit Symbol Bit Name Function In one-shot mode or repeat mode 0 : AN0 1 : AN1 0 : AN2...
Page 660 M16C/5L Group, M16C/56 Group 24. A/D Converter CKS0 (Frequency select bit 0) (b7) φ AD frequency is selected by a combination of the CKS0 bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and bits CKS3 and CKS2 in the ADCON2 register. Select bits CKS2 to CKS0 after setting the CKS3 bit in the ADCON2 register.
Page 661 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.2.5 A/D Control Register 1 (ADCON1) A/D Control Register 1 Symbol Address Reset Value b6 b5 b4 0000 X000b ADCON1 03D7h Bit Name Function Bit Symbol SCAN0 0: AN0 to AN1 (2 pins) 1: AN0 to AN3 (4 pins) A/D sweep pin select bit 0: AN0 to AN5 (6 pins)
Page 662 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.3 Operations 24.3.1 A/D Conversion Cycle A/D conversion cycle is based on fAD and φ AD. Divide fAD so φ AD conforms the standard frequency. Figure 24.2 shows fAD and φ AD. CKS1 Select A/D conversion speed CKS2 φAD...
Page 663 M16C/5L Group, M16C/56 Group 24. A/D Converter Table 24.6 lists Cycles of A/D Conversion Item. A/D conversion time is described below. Start processing time depends on which φ AD is selected. A/D conversion starts after the start processing time elapses by setting the ADST bit in the ADCON0 register to 1 (A/D conversion start).
Page 664 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.3.2 A/D Conversion Start Conditions An A/D conversion start trigger has a software trigger and an external trigger. Figure 24.4 shows A/D Conversion Start Trigger. ADST A/D conversion start trigger ADTRG pin ADST, TRG: Bits in the ADCON0 register Figure 24.4 A/D Conversion Start Trigger 24.3.2.1...
Page 665 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.3.3 A/D Conversion Result When reading the ADi register before A/D conversion is completed, the undefined value is read. Read the ADi register after completing A/D conversion. Use the following procedure to detect the completion of A/D conversion.
Page 666 M16C/5L Group, M16C/56 Group 24. A/D Converter Charge control signal Charge External circuit example Discharge AINRST0 = 1 control signal Analog input Sampling capacitor Open-circuit ANi: ANi (i = 0 to 7), AN0-i, AN2-i, AN3_0 to AN3_2 AINRST0: Bit in the AINRST register Figure 24.6 A/D Open-Circuit Detection Example on AVCC (Preconversion Charge) Charge...
Page 667 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.4 Operational Modes 24.4.1 One-Shot Mode In one-shot mode, the analog voltage applied to a selected pin is converted to a digital code once. Table 24.7 lists One-Shot Mode Specifications. Table 24.7 One-Shot Mode Specifications Item Specification Bits CH2 to CH0 in the ADCON0 register and bits ADGSEL1 to ADGSEL0...
Page 668 M16C/5L Group, M16C/56 Group 24. A/D Converter Table 24.8 Registers and Settings in One-Shot Mode Register Setting AINRST AINRST1, AINRST0 Select whether open-circuit detection assist function is used or not. AD0 to AD7 b9 to b0 A/D conversion result can be read. ADGSEL1, ADGSEL0 Select analog input pin group.
Page 669 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.4.2 Repeat Mode In repeat mode, the analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 24.9 lists Repeat Mode Specifications. Table 24.9 Repeat Mode Specifications Item Specification Bits CH2 to CH0 in the ADCON0 register and bits ADGSEL1 to ADGSEL0 Function...
Page 670 M16C/5L Group, M16C/56 Group 24. A/D Converter Table 24.10 Registers and Settings in Repeat Mode Register Setting AINRST1, Select whether open-circuit detection assist function is used or AINRST AINRST0 not. AD0 to AD7 b9 to b0 A/D conversion result can be read. ADGSEL1, Select analog input pin group.
Page 671 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.4.3 Single Sweep Mode In single sweep mode, the analog voltage applied to selected pins is converted one-by-one to a digital code. Table 24.11 lists the Single Sweep Mode Specifications. Table 24.11 Single Sweep Mode Specifications Item Specification Bits SCAN1 to SCAN0 in the ADCON1 register and bits ADGSEL1 to...
Page 672 M16C/5L Group, M16C/56 Group 24. A/D Converter Table 24.12 Registers and Settings in Single Sweep Mode Register Setting AINRST1, Select whether open-circuit detection assist function is used or AINRST AINRST0 not. AD0 to AD7 b9 to b0 A/D conversion result can be read. ADGSEL1, Select analog input pin group.
Page 673 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.4.4 Repeat Sweep Mode 0 In repeat sweep mode 0, the analog voltage applied to selected pins is repeatedly converted to a digital code. Table 24.13 lists the Repeat Sweep Mode 0 Specifications. Table 24.13 Repeat Sweep Mode 0 Specifications Item...
Page 674 M16C/5L Group, M16C/56 Group 24. A/D Converter Table 24.14 Registers and Settings in Repeat Sweep Mode 0 Register Setting AINRST1, Select whether open-circuit detection assist function is used or AINRST AINRST0 not. AD0 to AD7 b9 to b0 A/D conversion result can be read. ADGSEL1, Select analog input pin group.
Page 675 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.5 External Sensor To perform A/D conversion accurately, charging the internal capacitor C shown in Figure 24.12 must be completed within a specified period of time. T: Specified period of time (sampling time) R0: Output impedance of sensor equivalent circuit R: Internal resistance of the MCU X: Precision (error) of the A/D converter...
Page 676 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.6 Interrupt Refer to the operation examples for timing of generating interrupt requests. Also, refer to 12.7 “Interrupt Control” for details. Table 24.15 lists Registers Associated with A/D Converter Interrupt. Table 24.15 Registers Associated with A/D Converter Interrupt Address Register Symbol...
Page 677 M16C/5L Group, M16C/56 Group 24. A/D Converter 24.7 Notes on A/D Converter 24.7.1 Analog Input Pin Do not use any pin from AN4 to AN7 as analog input pin if any pin from KI0 to KI3 is used as a key input interrupt.
Page 678 M16C/5L Group, M16C/56 Group 24. A/D Converter (i = 0 to 7) may also become undefined. Do not use any value in ADi registers when setting the ADST bit to 0 by a program during A/D conversion. 24.7.7 A/D Open-Circuit Detection Assist Function The conversion result in open-circuit depends on the external circuit.
Page 679 M16C/5L Group, M16C/56 Group 25. CRC Calculator 25. CRC Calculator 25.1 Introduction The cyclic redundancy check (CRC) calculator detects errors in data blocks. This CRC calculator is enhanced by an additional feature, the CRC snoop, in order to monitor reads from and writes to a certain SFR address, and perform CRC calculations automatically on the data read from and data written to the aforementioned SFR address.
Page 680 M16C/5L Group, M16C/56 Group 25. CRC Calculator 25.2 Registers Table 25.2 Registers Address Register Symbol Reset Value 03B4h XXXX XXXXb SFR Snoop Address Register CRCSAR 03B5h 00XX XXXXb 03B6h CRC Mode Register CRCMR 0XXX XXX0b 03BCh CRC Data Register CRCD 03BDh 03BEh CRC Input Register...
Page 681 M16C/5L Group, M16C/56 Group 25. CRC Calculator 25.2.2 CRC Mode Register (CRCMR) CRC Mode Register b7 b6 b5 b4 Symbol Address Reset Value CRCMR 03B6h 0XXX XXX0b Bit Symbol Bit Name Function CRC polynomial select 0: X + 1 (CRC-CCITT) CRCPS 1: X + 1 (CRC-16)
Page 682 M16C/5L Group, M16C/56 Group 25. CRC Calculator 25.3 Operations 25.3.1 Basic Operation The CRC (Cyclic Redundancy Check) calculator detects errors in data blocks. The MCU uses two generator polynomials to generate CRC: CRC-CCITT (X + 1) and CRC-16 (X + 1). The CRC code is 16-bit code generated for a given length of a data block in 8-bit units.
Page 683 M16C/5L Group, M16C/56 Group 25. CRC Calculator CRC calculation and setting procedure to generate CRC, 80C4h, with CRC-CCITT (LSB first selected) • CRC calculator specification inverted value of the CRCIN register CRC: remainder of a division, generator polynomial Generator polynomial: X + 1 (1 0001 0000 0010 0001b) •...
Page 684 M16C/5L Group, M16C/56 Group 25. CRC Calculator CRC calculation and setting procedure to generate CRC, 80C4h with CRC-16 (MSB first selected) • CRC operation specification the CRCIN register CRC: remainder of a division, generator polynomial Generator polynomial: X + 1 (1 1000 0000 0000 0101b) •...
Page 685 M16C/5L Group, M16C/56 Group 26. Flash Memory 26. Flash Memory Note Pins P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P9_5 to P9_7 cannot be used in the 64-pin package. For the 64-pin package, do not use these pins for the entry of user boot function. 26.1 Introduction This product uses flash memory as ROM.
Page 686 M16C/5L Group, M16C/56 Group 26. Flash Memory Table 26.2 Flash Memory Rewrite Modes Overview Flash Memory CPU Rewrite Mode Standard Serial I/O Mode Parallel I/O Mode Rewrite Mode The flash memory is rewritten The flash memory is rewritten using a dedicated serial when the CPU executes software programmer.
Page 687 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.2 Memory Map The flash memory is used as ROM in this product. The flash memory is comprised of program ROM 1, program ROM 2, and data flash. Figure 26.1 shows the Flash Memory Block Diagram. The flash memory is divided into several blocks, each of which can be protected (locked) from being programmed or erased.
Page 688 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.3 Registers Table 26.4 Registers Address Register Symbol Reset Value 0000 0001b (Other than user boot mode) 0220h Flash Memory Control Register 0 FMR0 0010 0001b (User boot mode) 0221h Flash Memory Control Register 1 FMR1 00X0 XX0Xb 0222h...
Page 689 M16C/5L Group, M16C/56 Group 26. Flash Memory FMR01 (CPU rewrite mode select bit) (b1) Commands can be accepted by setting the FMR01 bit to 1 (CPU rewrite mode enabled). To set the FMR01 bit to 1, write 0 and then 1 in succession. Do not generate any interrupts or DMA transfers between setting 0 and 1.
Page 690 M16C/5L Group, M16C/56 Group 26. Flash Memory FMR06 (Program status flag) (b6) This bit indicates the auto-program operation state. Condition to become 0: • Execute the clear status command. Condition to become 1: • Refer to 26.8.7.1 “Full Status Check”. Do not execute the following commands when the FMR06 bit is 1: Program, block erase, lock bit program, and block blank check.
Page 691 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.3.2 Flash Memory Control Register 1 (FMR1) Flash Memory Control Register 1 b6 b5 b4 Symbol Address Reset Value FMR1 00X0 XX0Xb 0221h Bit Symbol Bit Name Function — Reserved bit The read value is undefined. (b0) Write to FMR6 register 0 : Disabled...
Page 692 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.3.3 Flash Memory Control Register 2 (FMR2) Flash Memory Control Register 2 b6 b5 b4 Symbol Address Reset Value FMR2 XXXX 0000b 0222h Bit Name Function Bit Symbol — Set to 0 Reserved bits (b1-b0) Slow read mode enable 0 : Disabled...
Page 693 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.3.4 Flash Memory Control Register 3 (FMR3) Flash Memory Control Register 3 b7 b6 b5 b4 Symbol Address Reset Value FMR3 XXXX 0000b 0223h Bit Symbol Bit Name Function Suspend function enable 0 : Disabled FMR30 1 : Enabled 0 : Command restart...
Page 694 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.3.5 Flash Memory Control Register 6 (FMR6) Flash Memory Control Register 6 b6 b5 b4 Symbol Address Reset Value FMR6 XX0X XX00b 0230h Bit Symbol Bit Name Function 0 : EW0 mode FMR60 EW1 mode select bit 1 : EW1 mode Reserved bit...
Page 695 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.4 Optional Function Select Area In an option function select area, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected. The option function select area is not an SFR, and therefore cannot be rewritten by a program. Set an appropriate value when writing a program to the flash memory.
Page 696 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.4.1 Optional Function Select Address 1 (OFS1) Optional Function Select Address 1 Symbol Address b6 b5 b4 OFS1 FFFFFh Bit Symbol Bit Name Function 0 : Watchdog timer starts automatically after reset. WDTON Watchdog timer start select bit 1 : Watchdog timer is in a stopped state after reset.
Page 697 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.4.2 Optional Function Select Address 2 (OFS2) Optional Function Select Address 2 b6 b5 b4 Symbol Address OFS2 FFFDBh Bit Symbol Bit Name Function b1 b0 WDTUFS0 0 0: 03FFh Watchdog timer initial setting bit 0 1: 0FFFh 1 0: 1FFFh WDTUFS1...
Page 698 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.5 Flash Memory Rewrite Disable Function This function disables the flash memory from being read, written, and erased. The following are details for each mode: Parallel I/O mode ROM code protect function Standard serial I/O mode ID code check function, forced erase function, and standard serial I/O mode disable function 26.6 Boot Mode...
Page 699 M16C/5L Group, M16C/56 Group 26. Flash Memory Program ROM 2 User Boot Code Area 10000h 13FF0h Boot code User boot start address 13FF8h Address Port information for entry 13FFAh 13FFBh Start level select 13000h 13FFCh On-chip debugger monitor area Reserved space 13FF0h 13FFFh User boot code area...
Page 700 M16C/5L Group, M16C/56 Group 26. Flash Memory Table 26.9 Addresses of Selectable Ports for Entry Address Port 13FF9h 13FF8h Table 26.10 Example Settings of User Boot Code Area When starting up in user boot mode while input level of the port P1_5 is low: Address Setting Value Meaning...
Page 701 M16C/5L Group, M16C/56 Group 26. Flash Memory When the RESET pin changes from low to high, CNVSS = VSS CNVSS = VCC Boot mode Single-chip mode Meets the condition of user Does not meet the condition boot code area of user boot code area Standard serial I/O User boot mode mode...
Page 702 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8 CPU Rewrite Mode In CPU rewrite mode, the flash memory can be rewritten when the CPU executes software commands. Program ROM 1, program ROM 2, and data flash can be rewritten with the MCU mounted on the board and without using a ROM programmer.
Page 703 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.1 EW0 Mode The MCU enters CPU rewrite mode when the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR60 bit in the FMR6 register to 0.
Page 704 M16C/5L Group, M16C/56 Group 26. Flash Memory Table 26.12 Modes after Executing Commands (in EW0 Mode) Command Mode after Executing Command Read array Read array mode Clear status register Read array mode Program Block erase Read status register mode Lock bit program Read lock bit status Read lock bit status mode Block blank check...
Page 705 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.1.1 Suspend Function (EW0 Mode) When using suspend function in EW0 mode, check the status of the flash memory in the interrupt routine and enter suspend mode. Program suspend or erase suspend is not accepted until td(SR- SUS) elapses after the FMR31 bit is set to 1.
Page 706 M16C/5L Group, M16C/56 Group 26. Flash Memory Start Maskable interrupt Interrupt I flag ← 0 disabled FMR00 = 0 ? Write 0 and then 1 Suspend to the FMR30 bit enabled Suspend FMR31 ← 1 request Write command code xx20h to X address FMR00 = 1 ? Write xxD0h to BA address...
Page 707 M16C/5L Group, M16C/56 Group 26. Flash Memory Start Maskable interrupt Interrupt I flag ← 0 disabled FMR00 = 0 ? Write 0 and then 1 Suspend to the FMR30 bit request Suspend FMR31 ← 1 request Write command code xx77h to BA address FMR00 = 1 ? Write xxD0h to BA address...
Page 708 M16C/5L Group, M16C/56 Group 26. Flash Memory Program Suspend Program command or Program completed lock bit program command issued Programming Programming FMR00 bit Set to 1 by a program Set to 0 by a program FMR31 bit FMR33 bit td(SR-SUS) Program suspend Erase Suspend Program command issued...
Page 709 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.2 EW1 Mode EW1 mode is selected by setting the FMR60 bit in the FMR6 register to 1 after setting the FMR01 bit in the FMR0 register to 1. Figure 26.10 shows Setting and Resetting of EW1 Mode. When a program or erase operation is initiated, the CPU halts all program execution until the operation is completed.
Page 710 M16C/5L Group, M16C/56 Group 26. Flash Memory Table 26.13 Modes after Executing Commands (in EW1 Mode) Command Mode after Executing Command Read array Clear status register Program Block erase Read array mode Lock bit program Read lock bit status Block blank check R01UH0127EJ0110 Rev.1.10 Page 673 of 803 Sep 01, 2011...
Page 711 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.2.1 Suspend Function (EW1 Mode) When using suspend function in EW1 mode, an interrupt request is not accepted until td(SR-SUS) elapses after the interrupt request is generated. When the interrupt request is accepted, the flash memory enters erase suspend or program suspend.
Page 712 M16C/5L Group, M16C/56 Group 26. Flash Memory Start Maskable interrupt Interrupt I flag ← 0 Access flash memory disabled Suspend Write 0 and then 1 REIT enabled to the FMR30 bit Write command code xx20h to X address Write xxD0h to BA address Interrupt I flag ←...
Page 713 M16C/5L Group, M16C/56 Group 26. Flash Memory Start Maskable interrupt Interrupt I flag ← 0 Access flash memory disabled Suspend Write 0 and then 1 REIT enabled to the FMR30 bit Write the command code XX77h to BA address Write XXD0h to BA address Interrupt I flag ←...
Page 714 M16C/5L Group, M16C/56 Group 26. Flash Memory Program Suspend Program command or Program completed lock bit program command issued Programming Programming FMR00 bit Set to 0 by a program Set to 1 by an interrupt request FMR31 bit FMR33 bit Interrupt request IR bit accepted...
Page 715 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.3 Operating Speed Select a CPU clock frequency of 16 MHz or less by setting the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to 1 (wait state).
Page 716 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.5 Suspend Function The suspend function suspends automatic programming and erasure. It can be used for an interrupt operation because program ROM 1, program ROM 2, and data flash can be read while automatic programming or erasure is suspended.
Page 717 M16C/5L Group, M16C/56 Group 26. Flash Memory Erase command is executed Erasing Erasing 150 μs or more 150 μs or more Erase suspend FMR31 bit in the FMR3 register Wait for 150 μs or more after command execution or suspend, and then request a suspend. Figure 26.15 Suspend Request R01UH0127EJ0110 Rev.1.10 Page 680 of 803...
Page 718 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.6 Software Commands Table 26.16 list Software Commands. Read or write commands and data in 16-bit units. When command code is written, the upper 8 bits (D15 to D8) are ignored. Table 26.16 Software Commands First Bus Cycle Second Bus Cycle...
Page 719 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.6.2 Read Status Register Command The read status register command is used to read the status register. By writing the command code xx70h in the first bus cycle, the status register can be read in the second bus cycle.
Page 720 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.6.4 Program Command The program command is used to write 2 words (4 bytes) of data to the flash memory. By writing xx41h in the first bus cycle and data to the write address in the second and third bus cycles, an auto-program operation (data program and verify) is started.
Page 721 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.6.5 Block Erase Command By writing xx20h in the first bus cycle and xxD0h to the highest even address of a block in the second bus cycle, an auto-erase operation (erase and verify) is started on the specified block. The FMR00 bit in the FMR0 register indicates whether the auto-erase operation has been completed.
Page 722 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.6.6 Lock Bit Program Command The lock bit program command is used to set the lock bit for a specified block to 0 (locked). By writing xx77h in the first bus cycle and xxD0h to the highest even address of a block in the second bus cycle, the lock bit for the specified block is set to 0.
Page 723 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.6.7 Read Lock Bit Status The read lock bit status command is used to read the lock bit state of a specified block. By writing xx71h in the first bus cycle and xxD0h to the highest even address of a block in the second bus cycle, the FMR16 bit in the FMR1 register stores information on the lock bit status of a specified block.
Page 724 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.6.8 Block Blank Check Command The block blank check command is used to check whether or not a specified block is blank (state after erase). By writing xx25h in the first bus cycle and xxD0h in the second bus cycle to the highest even address of a block, the check result is stored in the FMR07 bit in the FMR0 register.
Page 725 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.7 Status Register The status register indicates flash memory operating state and whether or not an erase or program operation has been completed as expected. Bits FMR00, FMR06, and FMR07 in the FMR0 register indicate status register states. Refer to 26.3.1 “Flash Memory Control Register 0 (FMR0)”...
Page 726 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.7.1 Full Status Check If an error occurs, bits FMR06 and FMR07 in the FMR0 register become 1, indicating the occurrence of an error. Therefore, the execution results can be confirmed by checking these status bits (full status check).
Page 727 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.8.7.2 Handling Procedure for Errors When errors occur, follow the procedures below. Do not execute the program, block erase, lock bit program, and block blank check commands when either FMR06 or FMR07 bit is 1 (completed in error). Execute each command after executing the clear status register command.
Page 728 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.9 Standard Serial I/O Mode In standard serial I/O mode, a serial programmer supporting the M16C/5L Group, M16C/56 Group can be used to rewrite program ROM 1, program ROM 2, and data flash while the MCU is mounted on a board. Standard serial I/O mode has following modes: •...
Page 729 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.9.1 ID Code Check Function Use the ID code check function in standard serial I/O mode. This function determines whether the ID codes sent from the serial programmer match those written in the flash memory. If the ID codes do not match, commands sent from the serial programmer are not accepted.
Page 730 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.9.2 Forced Erase Function Use the forced erase function in standard serial I/O mode. When the reserved word, “ALeRASE” in ASCII code, is sent from the serial programmer as an ID code, the contents of program ROM 1 and program ROM 2 will all be erased.
Page 731 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.9.4 Standard Serial I/O Mode 1 In standard serial I/O mode 1, a serial programmer is connected to the MCU using clock synchronous serial I/O. Table 26.22 Pin Functions (Flash Memory Standard Serial I/O Mode 1) Name Description Apply the flash memory program and erase voltage to the VCC...
Page 732 M16C/5L Group, M16C/56 Group 26. Flash Memory Table 26.23 Setting of Standard Serial I/O Mode 1 Signal Input Level CNVSS RESET VSS → VCC SCLK SCLK input P6_5/CLK1 TXD output P6_7/TXD1 BUSY output P6_4/RTS1 CNVSS RXD input P6_6/RXD1 Reset input RESET User reset signal Notes:...
Page 733 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.9.5 Standard Serial I/O Mode 2 In standard serial I/O mode 2, a serial programmer is connected to the MCU by using 2-wire clock asynchronous serial I/O. The main clock is used. Table 26.24 Pin Functions (Flash Memory Standard Serial I/O Mode 2) Name Description...
Page 734 M16C/5L Group, M16C/56 Group 26. Flash Memory Table 26.25 Setting of Standard Serial I/O Mode 2 Signal Input Level CNVSS RESET VSS → VCC P6_5/CLK1 TXD output P6_7/TXD1 P6_4/RTS1 Monitor output CNVSS RXD intput P6_6/RXD1 Reset input P6_5/CLK1 RESET User reset signal Notes: 1.
Page 735 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.11 Notes on Flash Memory 26.11.1 OFS1 Address, OFS2 Address, and ID Code Storage Address The OFS1 address, OFS2 address, and ID code storage address are part of flash memory. When writing a program to flash memory, write an appropriate value to those addresses simultaneously. In the OFS1 address, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected.
Page 736 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.11.3 CPU Rewrite Mode 26.11.3.1 Operating Speed Select a CPU clock frequency of 16 MHz or less by setting the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to 1 (wait state).
Page 737 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.11.3.10 Software Command Observe the notes below when using the following commands. • Program • Block erase • Lock bit program • Read lock bit status • Block blank check (a) The FMR00 bit in the FMR0 register indicates the status while executing these commands. Do not execute other commands while the FMR00 bit is 0 (busy).
Page 738 M16C/5L Group, M16C/56 Group 26. Flash Memory 26.11.4 User Boot 26.11.4.1 User Boot Mode Program Note the following when using user boot mode: • When using user boot mode, make sure to allocate the program to be executed to program ROM 2. •...
Page 739 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics 27. Electrical Characteristics J-Version 27.1 Electrical Characteristics (J-Version, Common to 3 V and 5 V) 27.1.1 Absolute Maximum Rating Table 27.1 Absolute Maximum Ratings Symbol Characteristic Condition Rated Value Unit Supply voltage = AV -0.3 to 6.5 Analog supply voltage = AV...
Page 740 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version 27.1.2 Recommended Operating Conditions Table 27.2 Operating Conditions (1) = 3.0 V to 5.5 V, T = -40°C to 85°C unless otherwise specified. Standard Symbol Characteristic Unit Min. Typ. Max. Supply voltage Analog supply voltage Ground voltage Analog ground voltage...
Page 741 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version Main clock input oscillation frequency PLL clock oscillation frequency 32.0 20.0 MHz 32.0 MHz 20.0 10.0 10.0 Vcc [V] (main clock: no division) Vcc [V] (PLL clock oscillation) Figure 27.1 Main Clock Input Oscillation Frequency, PLL Clock Oscillation Frequency Table 27.3 Recommended Operating Conditions (2/2) = 3.0 to 5.5 V, V...
Page 742 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version 27.1.3 A/D Conversion Characteristics Table 27.4 A/D Conversion Characteristics = -40 ° C to 85°C unless otherwise specified. = AV = 3.0 to 5.5 V, V = AV = 0 V at T Standard Symbol Parameter...
Page 743 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version 27.1.4 Flash Memory Electrical Characteristics Table 27.5 CPU Clock When Operating Flash Memory (f (BCLK) = -40 ° C to 85 ° C, unless otherwise specified. = 3.0 to 5.5 V at T Standard Symbol Parameter...
Page 744 Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office. The data hold time includes time that the power supply is off or the clock is not supplied.
Page 745 Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office. The data hold time includes time that the power supply is off or the clock is not supplied.
Page 746 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version 27.1.5 Voltage Detector and Power Supply Circuit Electrical Characteristics Table 27.8 Voltage Detector 0 Electrical Characteristics = -40 ° C to 85 ° C, unless otherwise specified. The measurement condition is V = 3.0 to 5.5 V, T Standard Symbol...
Page 747 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version Table 27.10 Power-On Reset Circuit = -40 ° C to 85 ° C, unless otherwise specified. The measurement condition is T Standard Symbol Parameter Condition Unit Min. Typ. Max. External power V rise gradient 50000 mV/ms External power V...
Page 748 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version Recommended operating voltage d(P-R) Time to stabilize internal supply voltage during powering-on d(P-R) CPU clock (a) Interrupt to exit from stop mode (b) Interrupt to exit from wait mode d(R-S) STOP release time d(W-S) Low power consumption mode wait mode exit time...
Page 749 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics 27.2 Electrical Characteristics (J-Version, V = 5 V) 27.2.1 Electrical Characteristics J-Version, V = 5 V Table 27.13 Electrical Characteristics (1) = 4.2 to 5.5 V, V = 0 V at T = -40°C to 85°C, f = 32 MHz unless otherwise specified.
Page 750 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 5 V Table 27.14 Electrical Characteristics (2) = − 40 to 85 ° C unless otherwise specified. °C Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. = 32 MHz, (BCLK) XIN = 8 MHz (square wave), PLL multiply-by-8 125 kHz on-chip oscillator operating...
Page 751 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 5 V 27.2.2 Timing Requirements (Peripheral Functions and Others) = - 40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.2.2.1 Reset Input (RESET Input) Table 27.15...
Page 752 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 5 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.2.2.3 Timer A Input Table 27.17 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol...
Page 753 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 5 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T Table 27.21 Timer A Input (Two-Phase Pulse Input in Event Counter Mode) Standard Symbol Parameter...
Page 754 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 5 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.2.2.4 Timer B Input Table 27.22 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol...
Page 755 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 5 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.2.2.5 Timer S Input Table 27.25 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode) Standard Symbol...
Page 756 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 5 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.2.2.6 Serial Interface Table 27.26 Serial Interface Standard Symbol...
Page 757 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 5 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.2.2.8 Multi-master I C-bus Table 27.28 Multi-master I C-bus Standard Clock Mode...
Page 758 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics 27.3 Electrical Characteristics (J-Version, V = 3 V) 27.3.1 Electrical Characteristics J-Version, V = 3 V Table 27.29 Electrical Characteristics (1) = − 40 ° C to 85 ° C, f = 3.0 to 3.6 V, V = 0 V at T = 32 MHz unless otherwise specified.
Page 759 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 3 V Table 27.30 Electrical Characteristics (2) Topr = − 40 to 85 ° C unless otherwise specified. ° C Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. = 32 MHz, (BCLK) XIN = 8 MHz (square wave), PLL multiply-by-8 125 kHz on-chip oscillator operating...
Page 760 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 3 V 27.3.2 Timing Requirements (Peripheral Functions and Others) = − 40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.3.2.1 Reset Input (RESET Input) Table 27.31...
Page 761 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 3 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.3.2.3 Timer A Input Table 27.33 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol...
Page 762 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 3 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T Table 27.37 Timer A Input (Two-Phase Pulse Input in Event Counter Mode) Standard Symbol Parameter...
Page 763 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 3 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.3.2.4 Timer B Input Table 27.38 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol...
Page 764 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 3 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.3.2.5 Timer S Input Table 27.41 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode) Standard Symbol...
Page 765 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 3 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.3.2.6 Serial Interface Table 27.42 Serial Interface Standard Symbol...
Page 766 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics J-Version, V = 3 V Timing Requirements = − 40 ° C to 85 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.3.2.8 Multi-master I C-bus Table 27.44 Multi-master I C-bus Standard Clock Mode...
Page 767 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version 27.4 Electrical Characteristics (K-Version, Common to 3 V and 5 V) 27.4.1 Absolute Maximum Rating Table 27.45 Absolute Maximum Ratings Symbol Characteristic Condition Rated Value Unit Supply voltage = AV -0.3 to 6.5 Analog supply voltage = AV -0.3 to 6.5...
Page 768 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version 27.4.2 Recommended Operating Conditions Table 27.46 Operating Conditions (1) = 3.0 V to 5.5 V, T = -40°C to 125°C unless otherwise specified. Standard Symbol Characteristic Unit Min. Typ. Max. Supply voltage Analog supply voltage Ground voltage Analog ground voltage...
Page 769 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version Main clock input oscillation frequency PLL clock oscillation frequency 32.0 20.0 MHz 32.0 MHz 20.0 10.0 10.0 Vcc [V] (main clock: no division) Vcc [V] (PLL clock oscillation) Figure 27.24 Main Clock Input Oscillation Frequency, PLL Clock Oscillation Frequency Table 27.47 Recommended Operating Conditions (2/2) = -40 °...
Page 770 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version 27.4.3 A/D Conversion Characteristics Table 27.48 A/D Conversion Characteristics = -40 ° C to 125°C unless otherwise specified. = AV = 3.0 to 5.5 V, V = AV = 0 V at T Standard Symbol Parameter...
Page 771 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version 27.4.4 Flash Memory Electrical Characteristics Table 27.49 CPU Clock When Operating Flash Memory (f (BCLK) = -40 ° C to 125 ° C, unless otherwise specified. = 3.0 to 5.5 V at T Standard Symbol Parameter...
Page 772 Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office. The data hold time includes time that the power supply is off or the clock is not supplied.
Page 773 Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office. The data hold time includes time that the power supply is off or the clock is not supplied.
Page 774 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version 27.4.5 Voltage Detector and Power Supply Circuit Electrical Characteristics Table 27.52 Voltage Detector 0 Electrical Characteristics = -40 ° C to 125 ° C, unless otherwise specified. The measurement condition is V = 3.0 to 5.5 V, T Standard Symbol...
Page 775 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version Table 27.54 Power-On Reset Circuit = -40 ° C to 125 ° The measurement condition is T C, unless otherwise specified. Standard Symbol Parameter Condition Unit Min. Typ. Max. External power V rise gradient 50000 mV/ms External power V...
Page 776 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version Recommended operating voltage d(P-R) Time to stabilize internal supply voltage during powering-on d(P-R) CPU clock (a) Interrupt to exit from stop mode (b) Interrupt to exit from wait mode d(R-S) STOP release time d(W-S) Low power consumption mode wait mode exit time...
Page 777 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics 27.5 Electrical Characteristics (K-Version, V = 5 V) 27.5.1 Electrical Characteristics K-Version, V = 5 V Table 27.57 Electrical Characteristics (1) = − 40 ° C to 125 ° C, f = 4.2 to 5.5 V, V = 0 V at T = 32 MHz unless otherwise specified.
Page 778 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 5 V Table 27.58 Electrical Characteristics (2) = − 40 ° C to 125 ° C unless otherwise specified. Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. = 32 MHz, (BCLK) XIN = 8 MHz (square wave), PLL multiply-by-8 125 kHz on-chip oscillator operating...
Page 779 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 5 V 27.5.2 Timing Requirements (Peripheral Functions and Others) = − 40 ° C to 125 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.5.2.1 Reset Input (RESET Input) Table 27.59...
Page 780 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 5 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.5.2.3 Timer A Input Table 27.61 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol...
Page 781 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 5 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 5 V, V = 0 V, at T Table 27.65 Timer A Input (Two-Phase Pulse Input in Event Counter Mode) Standard Symbol Parameter...
Page 782 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 5 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.5.2.4 Timer B Input Table 27.66 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol...
Page 783 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 5 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.5.2.5 Timer S Input Table 27.69 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode) Standard Symbol...
Page 784 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 5 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.5.2.6 Serial Interface Table 27.70 Serial Interface Standard Symbol...
Page 785 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 5 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 5 V, V = 0 V, at T 27.5.2.8 Multi-master I C-bus Table 27.72 Multi-master I C-bus Standard Clock Mode...
Page 786 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics 27.6 Electrical Characteristics (K-Version, V = 3 V) 27.6.1 Electrical Characteristics K-Version, V = 3 V Table 27.73 Electrical Characteristics (1) = − 40 ° C to 125 ° C, f = 3.0 to 3.6 V, V = 0 V at T =32 MHz unless otherwise specified.
Page 787 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 3 V Table 27.74 Electrical Characteristics (2) = − 40 ° C to 125 ° C unless otherwise specified. Standard Symbol Parameter Measuring Condition Unit Min. Typ. Max. = 32 MHz, (BCLK) XIN = 8 MHz (square wave), PLL multiply-by-8 125 kHz on-chip oscillator operating...
Page 788 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 3 V 27.6.2 Timing Requirements (Peripheral Functions and Others) = − 40 ° C to 125 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.6.2.1 Reset Input (RESET Input) Table 27.75...
Page 789 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 3 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.6.2.3 Timer A Input Table 27.77 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol...
Page 790 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 3 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 3 V, V = 0 V, at T Table 27.81 Timer A Input (Two-Phase Pulse Input in Event Counter Mode) Standard Symbol Parameter...
Page 791 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 3 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.6.2.4 Timer B Input Table 27.82 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol...
Page 792 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 3 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.6.2.5 Timer S Input Table 27.85 Timer S Input (Two-Phase Pulse Input in Two-Phase Pulse Signal Processing Mode) Standard Symbol...
Page 793 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 3 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.6.2.6 Serial Interface Table 27.86 Serial Interface Standard Symbol...
Page 794 M16C/5L Group, M16C/56 Group 27. Electrical Characteristics K-Version, V = 3 V Timing Requirements = − 40 ° C to 125 ° C unless otherwise specified) = 3 V, V = 0 V, at T 27.6.2.8 Multi-master I C-bus Table 27.88 Multi-master I C-bus Standard Clock Mode...
Page 795 M16C/5L Group, M16C/56 Group 28. Usage Notes 28. Usage Notes 28.1 Notes on Noise Connect a bypass capacitor (approximately 0.1 µF) across pins VCC and VSS using the shortest and thickest possible wiring. Figure 28.1 shows the Bypass Capacitor Connection. M16C/5L Group, M16C/56 Group Connecting pattern Connecting pattern...
Page 796 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.2 Notes on SFRs 28.2.1 Register Settings Table 28.1 lists Registers with Write-Only Bits and registers whose function differs between reading and writing. Set these registers with immediate values. Do not use read-modify-write instructions. When establishing the next value by altering the existing value, write the existing value to the RAM as well as to the register.
Page 797 M16C/5L Group, M16C/56 Group 28. Usage Notes Table 28.2 Read-Modify-Write Instructions Function Mnemonic Transfer MOV Dir Bit processing BCLR, BM Cnd , BNOT, BSET, BTSTC, and BTSTS Shifting ROLC, RORC, ROT, SHA, and SHL ABS, ADC, ADCF, ADD, DEC, DIV, DIVU, DIVX, EXTS, INC, MUL, MULU, NEG, Arithmetic operation SBB, and SUB Decimal operation...
Page 798 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.3 Notes on Protection After setting the PRC2 bit to 1 (write enabled), by writing to a given SFR, the PRC2 bit becomes 0 (write disabled). Change the registers protected by the PRC2 bit in the next instruction after setting the PRC2 bit to 1.
Page 799 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.4 Notes on Resets 28.4.1 Power Supply Rising Gradient When supplying power to the MCU, make sure that the power supply voltage applied to the VCC pin meets the SVCC conditions. Standard Symbol Parameter Unit Min.
Page 800 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.5 Notes on Clock Generator 28.5.1 Oscillator Using a Crystal or a Ceramic Resonator To connect a crystal/ceramic resonator follow the instructions below: • The oscillation characteristics are tied closely to the user’s board design. Perform a careful evaluation of the board before connecting an oscillator.
Page 801 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.5.2 Noise Countermeasure 28.5.2.1 Clock I/O Pin Wiring • Connect the shortest possible wiring to the clock I/O pin. • Connect (a) the capacitor's ground lead connected to the crystal/ceramic resonator, and (b) the MCU's VSS pin, with the shortest possible wiring (maximum 20 mm).
Page 802 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.5.2.3 Signal Line Whose Level Changes at a High-Speed For a signal line whose level changes at a high-speed, wire it as far away from the crystal/ceramic resonator and its wiring pattern as possible. Do not wire it across or extend it parallel to a clock- related signal line or other signal lines which are sensitive to noise.
Page 803 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.5.5 PLL Frequency Synthesizer To use the PLL frequency synthesizer, stabilize the supply voltage within the acceptable range of power supply ripple. Table 28.4 Acceptable Range of Power Supply Ripple Standard Symbol Parameter Unit Min.
Page 804 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.6 Notes on Power Control 28.6.1 CPU Clock When switching the CPU clock source, wait until oscillation of the switched clock source is stable. After exiting stop mode, wait until oscillation stabilizes before changing the division. 28.6.2 Wait Mode •...
Page 805 M16C/5L Group, M16C/56 Group 28. Usage Notes The following is an example program for entering stop mode: Program Example: FSET BSET 0, CM1 ; Enter stop mode JMP.B ; Insert a JMP.B instruction ; At least four NOP instructions • The CLKOUT pin outputs a high-level signal in stop mode.
Page 806 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.7 Notes on Programmable I/O Ports Note The 64-pin package has no P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P9_5 to P9_7. 28.7.1 Pin Assignment Control Bits PACR2 to PACR0 in the PACR register are 000b after reset. Set 010b (64-pin package) or 011b (80-pin package) to select the pin package, depending on the product.
Page 807 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.8 Notes on Interrupts 28.8.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from address 00000h during the interrupt sequence.
Page 808 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.8.4 Changing an Interrupt Source When the interrupt source is changed, the IR bit in the interrupt control register may become 1 (interrupt requested). To use an interrupt, change the interrupt source, and then set the IR bit to 0 (interrupt not requested).
Page 809 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.8.5 Rewriting the Interrupt Control Register To modify the interrupt control register, follow either of the procedures below: • Modify in places where no interrupt requests corresponding to the interrupt control register may occur.
Page 810 M16C/5L Group, M16C/56 Group 28. Usage Notes INT Interrupt 28.8.7 • Either a low level of at least tw(INL) width or a high level of at least tw(INH) width is necessary for the signal input to pins INT0 through INT5 , regardless of the CPU operation clock. •...
Page 811 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.9 Notes on the Watchdog Timer After the watchdog timer interrupt is generated, use the WDTR register to refresh the watchdog timer counter. R01UH0127EJ0110 Rev.1.10 Page 774 of 803 Sep 01, 2011...
Page 812 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.10 Notes on DMAC 28.10.1 Write to the DMAE Bit in the DMiCON Register (i = 0 to 3) (Technical update number: TN-M16C-92-0306) When both of the following conditions are met, follow steps (1) and (2) below. Conditions •...
Page 813 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.11 Notes on Timer A 28.11.1 Common Notes on Multiple Modes 28.11.1.1 Register Setting The timer stops after reset. Set the mode, count source, counter value, etc., using registers TAiMR, TAi, TAi1, UDF, TRGSR, PWMFS, TACS0 to TACS2, TAPOFS, TCKDIVC0, PCLKR, and bits TAZIE, TA0TGL, and TA0TGH in the ONSF register before setting the TAiS bit in the TABSR register to 1 (count started) (i = 0 to 4).
Page 814 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.11.2 Timer A (Timer Mode) 28.11.2.1 Reading the Timer The counter value can be read from the TAi register at any time while counting. However, if the counter is read at the same time as it is reloaded, the read value is FFFFh. Also, if the counter is read before it starts counting, or after a value is set in the TAi register while not counting, the set value is read.
Page 815 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.11.5 Timer A (Pulse Width Modulation Mode) 28.11.5.1 Changing Operating Modes The IR bit becomes 1 when setting a timer operating mode with any of the following: • Selecting PWM mode or programmable output mode after reset •...
Page 816 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.11.6 Timer A (Programmable Output Mode) 28.11.6.1 Changing the Operating Mode The IR bit becomes 1 when setting a timer operating mode with any of the following: • Selecting PWM mode or programmable output mode after reset •...
Page 817 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.12 Notes on Timer B 28.12.1 Common Notes on Multiple Modes 28.12.1.1 Register Setting The timer is stopped after reset. Set the mode, count source, etc., using registers TBiMR, TBCS0 to TBCS1, TBi, PCLKR and PPWFS1 before setting the TBiS bit in the TABSR register to 1 (count started) (i = 0 to 2).
Page 818 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.12.4 Timer B (Pulse Period/Pulse Width Measurement Modes) 28.12.4.1 MR3 Bit in the TBiMR Register To clear the MR3 bit to 0 by writing to the TBiMR register while the TBiS bit is 1 (count started), be sure to set the same value as previously set to bits TMOD0, TMOD1, MR0, MR1, TCK0, and TCK1, and set bit 4 to 0.
Page 819 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.13 Notes on Three-Phase Motor Control Timer Function 28.13.1 Timer A and Timer B Refer to 15.5 “Notes on Timer A” and 16.5 “Notes on Timer B”. 28.13.2 Influence of SD When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three- phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance: P7_2/CLK2/TA1OUT/V/RXD1, P7_3/ CTS2 / RTS2 /TA1IN/ V /TXD1, P7_4/TA2OUT/W, P7_5/TA2IN/ W , P8_0/TA4OUT/U/TSUDA, P8_1/TA4IN/ U /TSUDB...
Page 820 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.14 Notes on Timer S 28.14.1 Register Access The explanation for some bits and registers states, “the value written to this register or this bit is reflected to the internal circuit when the clock is synchronized with the base timer count source (fBT1)”. When writing these bits or registers, the written value is not reflected to the internal circuits immediately.
Page 821 M16C/5L Group, M16C/56 Group 28. Usage Notes IC/OC interrupt 0 processing Buffer ← G1IR register Store an interrupt request for each channel in the buffer on RAM. Wait for one fBT1 cycle since the bits in the G1IR register Wait for one fBT1 cycle cannot be set to 0 for this period.
Page 822 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.14.3 Changing Registers ICOCiIC (i = 0, 1) While the G1IEij bit in the G1IEi register is 1 (IC/OC interrupt 1 request enabled), use the AND, OR, BCLR, or BSET instruction to change bits ILVL2 to ILVL0 in the ICOCiIC register at the point where a channel j interrupt request may be generated (j = 0 to 7).
Page 823 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.15 Notes on Task Monitor Timer 28.15.1 Register Settings After reset, the task monitor timer counter is stopped. After setting the counter value and count source by setting registers TMOS register and TMOSCS, set the TMOS0S bit in the TMOSSR register to 1 (start counting).
Page 824 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.16 Notes on Real-Time Clock 28.16.1 Starting and Stopping the Count The real-time clock uses the TSTART bit for instructing the count to start or stop, and the TCSTF bit which indicates count started or stopped. Bits TSTART and TCSTF are in the RTCCR1 register. The real-time clock starts counting and the TCSTF bit becomes 1 (count started) when the TSTART bit is set to 1 (count started).
Page 825 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.16.4 Time Reading Procedure in Real-Time Clock Mode In real-time clock mode, read time data bits when the BSY bit in the RTCSEC register is 0 (not while data is updated). When reading multiple registers, if data is rewritten between reading registers, an errant time will be read.
Page 826 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.17 Notes on Serial Interface UARTi (i = 0 to 4) Note Pins CLK4, RXD4, and TXD4 do not exist in the 64-pin package. Do not access the UART4 associated registers. 28.17.1 Common Notes on Multiple Modes 28.17.1.1 Influence of SD When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three- phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance:...
Page 827 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.17.2.3 Reception In clock synchronous serial I/O mode, a shift clock is generated by activating a transmitter. Set the UARTi-associated registers for a transmit operation even if the MCU is used for a receive operations only.
Page 828 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.17.3.3 Setup and Hold Times When Generating a Start/Stop Condition When generating a start condition, the hold time (t :STA) is a half cycle of the SCL clock. When generating a stop condition, the setup time (t :STO) is a half cycle of the SCL clock.
Page 829 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.17.3.5 Restart Condition in Slave Mode When a restart condition is detected in slave mode, the successive processes may not be executed correctly. In slave mode, do not use a restart condition. 28.17.3.6 Requirements to Start Transmission/Reception in Slave Mode When transmission/reception is started in slave mode and the TXEPT bit in the UiC0 register is 1 (no data present in transmit register), meet the last requirement when the external clock is high.
Page 830 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.18 Notes on Multi-master I C-bus Interface 28.18.1 Limitation on CPU Clock When the CM07 bit in the CM0 register is 1 (CPU clock is a sub clock), do not access the registers listed in Table 22.4 “Registers”.
Page 831 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.19 Notes on CAN Module Note Do not use CAN function in the M16C/56 Group. R01UH0127EJ0110 Rev.1.10 Page 794 of 803 Sep 01, 2011...
Page 832 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.20 Notes on A/D Converter Note The 64-pin package has no AN0_4 to AN0_7 (P0_4 to P0_7), AN2_0 to AN2_3 (P1_0 to P1_3), AN2_5 to AN2_7 (P9_5 to P9_7). 28.20.1 Analog Input Pin Do not use any pin from AN4 to AN7 as analog input pin if any pin from KI0 to KI3 is used as a key input interrupt.
Page 833 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.20.4 A/D Conversion Start When rewriting the ADSTBY bit in the ADCON1 register from 0 (A/D operation stopped) to 1 (A/D operation enabled), wait for one φ AD cycle or more before starting A/D conversion. 28.20.5 A/D Operation Mode Change When the A/D operation mode has been changed, reselect analog input pins by using bits CH2 to CH0 in the ADCON0 register or bits SCAN1 to SCAN0 in the ADCON1 register.
Page 834 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.21 Notes on Flash Memory Note Pins P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P9_5 to P9_7 cannot be used in the 64-pin package. For the 64-pin package, do not use these pins for the entry of user boot function. 28.21.1 OFS1 Address, OFS2 Address, and ID Code Storage Address The OFS1 address, OFS2 address, and ID code storage address are part of flash memory.
Page 835 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.21.3 CPU Rewrite Mode 28.21.3.1 Operating Speed Select a CPU clock frequency of 16 MHz or less by setting the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to 1 (wait state).
Page 836 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.21.3.10 Software Command Observe the notes below when using the following commands. • Program • Block erase • Lock bit program • Read lock bit status • Block blank check (a) The FMR00 bit in the FMR0 register indicates the status while executing these commands. Do not execute other commands while the FMR00 bit is 0 (busy).
Page 837 M16C/5L Group, M16C/56 Group 28. Usage Notes 28.21.4 User Boot 28.21.4.1 User Boot Mode Program Note the following when using user boot mode: • When using user boot mode, make sure to allocate the program to be executed to program ROM 2. •...
Page 838 M16C/5L Group, M16C/56 Group REGISTER INDEX REGISTER INDEX CM2 ............97 CPSRF ........... 234, 283 CRCD ............. 644 CRCIN ............ 644 CRCMR ..........644 AD0 to AD7 ..........620 CRCSAR ..........643 ADCON0 ..........622 CSPR ............. 203 ADCON1 ..........624 ADCON2 ..........
Page 839 M16C/5L Group, M16C/56 Group REGISTER INDEX PUR2 ............155 PWMFS ..........237 ICOC0IC ..........171 ICOC1IC ..........171 ICOCH0IC ..........171 ICOCH1IC ..........171 RMAD0 to RMAD3 ......... 177 ICOCH2IC ..........171 RSTFR ............. 63 ICOCH3IC ..........171 RTCCHR ..........418 ICTB2 .............
Page 840 M16C/5L Group, M16C/56 Group REGISTER INDEX TB0MR ........... 288 TB11 ............285 TB1MR ........... 288 TB2 ............309 TB21 ............285 TB2MR ........... 288 TB2SC ........... 316 TBCS0, TBCS1 ........286 TCKDIVC0 ........235, 287 TCR0 to TCR3 ........216 TMOS .............
Page 841 Date Page Summary 1.10 Sep. 01, 2011 Overall Specified Renesas Electronics sales office as a contact. Modified register names are as follows: • 0075h “CAN0 Receive Completion Interrupt Control Register” to “CAN0 Reception Complete Interrupt Control Register” Overall • 0076h “CAN0 Transmit Completion Interrupt Control Register” to “CAN0 Transmission Complete Interrupt Control Register”...
Page 842 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 Memory Figure 3.1 Memory Map: • Added note 2. • Added footnote reference numbers (1) and (2). Special Function Registers (SFRs) 4.2.1 Register Settings: Added the description regarding read-modify-write instructions. Table 4.33 Read-Modify-Write Instructions: Added.
Page 843 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 8.2.2 System Clock Control Register 1 (CM1): • CM10 bit explanation: Rewrote the condition for the bit to remain unchanged as a bulleted list, and added the last two conditions to the list.
Page 844 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 9.3.1.3 40 MHz On-Chip Oscillator Mode: Changed the description for the clock division of fOCO-F in the first paragraph. 9.3.1.6 Low-Speed Mode: Changed the division of fOCO-F for when bits CM21 and FRA01 are both 1.
Page 845 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 9.6.2 Wait Mode: • Added lines 4 and 5 to the first bullet. • Deleted second bullet in the previous version and added the second to fifth bullets. 9.6.3 Stop Mode: •...
Page 846 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 Figure 14.1 DMAC Block Diagram: Unified data buses for low/high-order bits with a single data bus. Table 14.7 Timing at Which the DMAS Bit Value Changes: Changed “selected by setting bits DSEL4 to DSEL0”...
Page 847 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 Table 16.9 Specifications of Pulse Period/Pulse Width Measurement Modes: • Moved previous note 3 to the description for TBiS above notes. • Added note 3. Table 16.10 Registers and Settings in Pulse Period/Pulse Width Measurement Modes: Modified “TBCS0 to TBCS3”...
Page 848 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 18.2.8 Time Measurement Prescaler Register j (G1TPRj) (j = 6 and 7): Added the Set Value column. 18.2.13 Waveform Output Master Enable Register (G1OER): Changed “set the EOCj bit to 0”...
Page 849 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 Figure 18.14 Single-Phase Waveform Output Mode Operation (1/2): Changed “fBTi” to “fBT1” in (1). Figure 18.15 Single-Phase Waveform Output Mode Operation (2/2): • Added “when bits IOj1 and IOj0 are 10b” to the description “Output high by compare match”. •...
Page 850 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 21.2.5 UARTi Transmit Buffer Register (UiTB) (i = 0 to 4): Added “or I C mode” after “When character length is 9 bits long...”. 21.2.6 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 4): •...
Page 851 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 Table 21.14 Registers Used and Settings in I C Mode (1/2): • Added UCLKSEL0 and PCLKR to the Register column. • Added “When receiving, set FFh.” to b0 to b7 of U2TB in the Function column. •...
Page 852 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 22.3.1.2 Bit Rate and Duty Cycle: Added more details to the explanation of the relation between low/high period and bit rate. 22.3.1.3 Receiving a Slave Address in Wait Mode and Stop Mode: Rewritten. Figure 22.15 Operation When Transmitted/Received a Slave Address or Data: Changed the description of bits TRX, ADR0, and AAS in parenthesis for when a slave address is received.
Page 853 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 26.7 User Boot Mode: Added. 26.7.1 User Boot Function • Changed “with the input of the selected port” to “with the input level of the selected port” in the first paragraph below Table 26.6.
Page 854 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 Figure 26.27 Circuit Application in Standard Serial I/O Mode 2: Moved P6_5/CLK1 to a lower position. 26.10 Parallel I/O Mode: Changed the title number from “29.9.6.” to “26.10”. 26.10.1 ROM Code Protect Function: Added the description for the ROMCR bit.
Page 855 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 Figure 27.37 Multi-master I C-bus: Changed t ;DTA to t ;DAT and t ;DTA to t ;DAT. K-Version, V = 3 V Table 27.73 Electrical Characteristics (1): Changed the maximum value of V , which includes TA0IN and others in Hysteresis, from “1.8”.
Page 856 REVISION HISTORY M16C/5L, M16C/56 Group User's Manual: Hardware Description Rev. Date Page Summary 1.10 Sep. 01, 2011 28.18.2.4 S3D0 Register and 28.18.2.6 S10 Register: Added “Use the MOV instruction to write to this register.” to the first bullet. 28.20.1 Analog Input Pin: Changed the description. 28.20.2 Pin Configuration: Rewritten.
Page 857 Items revised or added in previous versions REVISION HISTORY M16C/5L Group, M16C/56 Group Hardware Manual Rev. Date Page Revision History 0.61 Jul. 31, 2009 — Initial release 0.70 Oct. 09, 2009 The manual in general — Description for M16C/56 Group added —...
Page 858 REVISION HISTORY M16C/5L Group, M16C/56 Group Hardware Manual Rev. Date Page Revision History 0.70 Oct. 09, 2009 Table 9.7 “Resets and Interrupts to Exit Wait Mode and Usage Conditions” partially modified Table 9.9 “Resets and Interrupts to Exit Stop Mode and Usage Conditions” partially modified Figure 9.2 “Setting Procedures to Stop and Restart the Flash Memory”...
Page 859 REVISION HISTORY M16C/5L Group, M16C/56 Group Hardware Manual Rev. Date Page Revision History 0.70 Oct. 09, 2009 16.2.5 “Pulse Period/Pulse Width Measurement Mode Function Select Register 1 (PPWFS1)” partially modified 16.3.1.3 “Count Source” partially modified Table 16.8 “Registers and the Setting in Event Counter Mode ”...
Page 860 REVISION HISTORY M16C/5L Group, M16C/56 Group Hardware Manual Rev. Date Page Revision History 0.70 Oct. 09, 2009 Multi-Master I C-bus Interface Table 22.4 “Register List” reset values for S1D0 and S4D0 modified 22.2.3 “I2C0 Control Register 0 (S1D0)” reset value modified 22.2.6 “I2C0 Control Register 1 (S3D0)”...
Page 861 REVISION HISTORY M16C/5L Group, M16C/56 Group Hardware Manual Rev. Date Page Revision History 1.00 Jan. 31, 2010 Table 1.10 “Pin Names, 64-Pin Package (2/2)” TB2IN moved from 63 pin to 64 pin Table 1.11 “Pin Functions (64-Pin and 80-Pin Packages)” “Three-phase motor control timer output”...
Page 862 REVISION HISTORY M16C/5L Group, M16C/56 Group Hardware Manual Rev. Date Page Revision History 1.00 Jan. 31, 2010 Watchdog Timer Table 13.1 “Watchdog Timer Specification” “Dedicated 125-kHz on-chip oscillator for watchdog timer” added to fWDT Figure 13.1 “Watchdog Timer Block Diagram” “Dedicated 125-kHz on-chip oscillator for watchdog timer”...
Page 863 REVISION HISTORY M16C/5L Group, M16C/56 Group Hardware Manual Rev. Date Page Revision History 1.00 Jan. 31, 2010 Table 22.9 “Functions by Write Access to the S10 Register” “Selects communication mode” divided into four modes “PIN (I2C-bus Interface Interrupt Request Bit) (b4)” description added to the third bullet in “Conditions to become 0”...
Page 864 REVISION HISTORY M16C/5L Group, M16C/56 Group Hardware Manual Rev. Date Page Revision History 1.00 Jan. 31, 2010 Table 27.3 “Recommended Operating Conditions (2/2) ” added; Figure 27.2 “Ripple Waveform” added Table 27.4 “A/D Conversion Characteristics ” “A/D operating clock frequency” added; Note 3 added Table 27.5 “CPU Clock When Operating Flash Memory (f )”...
Page 865 REVISION HISTORY M16C/5L Group, M16C/56 Group Hardware Manual Rev. Date Page Revision History 1.00 Jan. 31, 2010 K-Version, VCC = 5 V Table 27.57 “Electrical Characteristics (1)” Parameter for V modified: “SCL, SDA”, and “TA2OUT“ modified to “SCL2, SDA2”, and “TA0OUT” respectively; “ZP, IDU, IDW, IDV, SD, INPC1_0 to INPC1_7, CRX0”...
Page 866 M16C/5L Group, M16C/56 Group User’s Manual: Hardware Publication Date: Rev.0.61 Jul 31, 2009 Rev.1.10 Sep 01, 2011 Published by: Renesas Electronics Corporation...
Page 867 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada...
Page 868 M16C/5L Group, M16C/56 Group R01UH0127EJ0110 (Previous Number: REJ09B0461-0100)

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